rtd DM34116HR User manual

RTD Embedded Technologies, Inc.
AS9100 and ISO 9001 Certified
DM34116HR
1-25MHz A/D Digitizer with 25Mhz D/A Outputs
User’s Manual
BDM-610010057 Rev A

RTD Embedded Technologies, Inc. | www.rtd.com ii DM34116HR User’s Manual
BDM-610010057 Rev A
RTD Embedded Technologies, Inc.
103 Innovation Boulevard
State College, PA 16803 USA
Telephone: [phone]
Fax: [phone]
www.rtd.com
[email protected]
[email protected]

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BDM-610010057 Rev A
Revision History
Rev A Initial Release
Advanced Analog I/O, Advanced Digital I/O, aAIO, aDIO, a2DIO, Autonomous SmartCal, “Catch the Express”, cpuModule, dspFramework, dspModule, expressMate, ExpressPlatform, HiDANplus, “MIL Value for
COTS prices”, multiPort, PlatformBus, and PC/104EZ are trademarks, and “Accessing the Analog World”, dataModule, IDAN, HiDAN, RTD, and the RTD logo are registered trademarks of RTD Embedded
Technologies, Inc (formerly Real Time Devices, Inc.). PS/2 is a trademark of International Business Machines Inc. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PC/104, PC/104-Plus, PCI-104, PCIe/104,
PCI/104-Express and 104 are trademarks of the PC/104 Embedded Consortium. All other trademarks appearing in this document are the property of their respective owners.
Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed
by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not
be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.
Copyright © 2019 by RTD Embedded Technologies, Inc. All rights reserved.
Advanced Analog I/O, Advanced Digital I/O, aAIO, aDIO, a2DIO, Autonomous SmartCal, “Catch the Express”, cpuModule, dspFramework, dspModule, expressMate, ExpressPlatform, HiDANplus, “MIL Value for
COTS prices”, multiPort, PlatformBus, and PC/104EZ are trademarks, and “Accessing the Analog World”, dataModule, IDAN, HiDAN, RTD, and the RTD logo are registered trademarks of RTD Embedded
Technologies, Inc (formerly Real Time Devices, Inc.). PS/2 is a trademark of International Business Machines Inc. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PC/104, PC/104-Plus, PCI-104, PCIe/104,
PCI/104-Express and 104 are trademarks of the PC/104 Embedded Consortium. All other trademarks appearing in this document are the property of their respective owners.
Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed
by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not
be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.
Copyright © 2019 by RTD Embedded Technologies, Inc. All rights reserved.

RTD Embedded Technologies, Inc. | www.rtd.com iv DM34116HR User’s Manual
BDM-610010057 Rev A
Table of Contents
1Introduction 10
1.1 Product Overview...................................................................................................................................................................... 10
1.2 Board Features ......................................................................................................................................................................... 10
1.3 Ordering Information................................................................................................................................................................. 11
1.4 Contact Information .................................................................................................................................................................. 11
1.4.1 Sales Support 11
1.4.2 Technical Support 11
2Specifications 12
2.1 Operating Conditions ................................................................................................................................................................ 12
2.2 Electrical Characteristics .......................................................................................................................................................... 12
2.1 Functional Characteristics ........................................................................................................................................................ 13
2.1.1 Analog Input FFT plots 13
3Board Connection 15
3.1 Board Handling Precautions ..................................................................................................................................................... 15
3.2 Physical Characteristics............................................................................................................................................................ 15
3.3 Connectors and Jumpers.......................................................................................................................................................... 16
3.3.1 Bus Connectors 16
3.3.2 External I/O Connectors 17
3.3.3 Jumpers 18
3.3.4 LEDs 18
3.4 Steps for Installing .................................................................................................................................................................... 19
4IDAN Connections 20
4.1 Module Handling Precautions................................................................................................................................................... 20
4.2 Physical Characteristics............................................................................................................................................................ 20
4.3 Connectors................................................................................................................................................................................ 21
4.3.1 External I/O Connectors 21
4.3.2 Bus Connectors 22
4.4 Steps for Installing .................................................................................................................................................................... 23
5Functional Description 24
5.1 Block Diagram........................................................................................................................................................................... 24
5.2 FPGA with DMA Engine ........................................................................................................................................................... 24
5.3 Programmable Clock ................................................................................................................................................................ 25
5.4 SyncBus.................................................................................................................................................................................... 25
5.4.1 Clock Generator Sync 25
5.5 Capture Window ....................................................................................................................................................................... 26
5.6 Advanced Digital I/O ................................................................................................................................................................. 26
5.6.1 Quad Pulse Width Modulator 27
5.6.2 Incremental Encoder 27
5.6.3 External Clocking 28
5.7 Temperature Sensor................................................................................................................................................................. 29
5.8 Analog input.............................................................................................................................................................................. 29
5.8.1 Initializing the ADC Converter 30
5.8.2 Simplified block diagram of analog input 30
5.8.3 Input connection examples 31
5.9 Analog Output........................................................................................................................................................................... 32
5.9.1 Initializing the DAC Converter 32

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5.9.2 Simplified block diagram of analog output 33
6Register Address Space 34
6.1 BAR0: General Board Control .................................................................................................................................................. 35
6.1.1 GBC_FMT (Read-Only) 35
6.1.2 GBC_REV (Read-Only) 35
6.1.3 GBC_BRD_RST (Read/Write) 35
6.1.4 GBC_PDP (Read-Only) 35
6.1.5 GBC_BUILD (Read-Only) 35
6.1.6 GBC_SYS_CLK_FREQ (Read Only) 36
6.1.7 GBC_USER_ID (Read Only) 36
6.1.8 GBC_IRQ_STATUS (Read/Clear) 36
6.1.9 GBC_DIRQ_STATUS (Read/Clear) 36
6.1.10 GBC_EOI (Read/Clear) 36
6.1.11 FBn_ID (Read-Only) 36
6.1.12 FBn_Offset (Read-Only) 36
6.1.13 FBn_Offset_DMA (Read-Only) 36
6.2 BAR2: Functional Block Standard DMA ................................................................................................................................... 37
6.2.1 FB_DMAm_Action (Read/Write) 37
6.2.2 FB_DMAm_Last_Action (Read/Write) 37
6.2.3 FB_DMAm_Setup (Read/Write) 37
6.2.4 FB_DMAm_Stat_Used (Read/Write) 38
6.2.5 FB_DMAm_Stat_Invalid (Read/Write) 38
6.2.6 FB_DMAm_Stat_Overflow (Read/Write) 38
6.2.7 FB_DMAm_Stat_Underflow (Read/Write) 38
6.2.8 FB_DMAm_Stat_Complete (Read/Write) 38
6.2.9 FB_DMAm_Current_Buffer (Read-Only) 38
6.2.10 FB_DMAm_COUNT (Read-Only) 38
6.2.11 FB_DMAm_RD_FIFO_CNT(Read-Only) 38
6.2.12 FB_DMAm_WR_FIFO_CNT(Read-Only) 38
6.2.13 FB_DMAm_ADDRESSn (Read/Write) 38
6.2.14 FB_DMAm_SIZEn (Read/Write) 38
6.2.15 FB_DMAm_CTRLn (Read/Write) 39
6.2.16 FB_DMAm_STATn (Read/Clear) 39
6.3 BAR2: Functional Block Header Registers............................................................................................................................... 39
6.3.1 FB_ID (Read-Only) 39
6.3.2 FB_DMA_CHANNELS (Read -Only) 39
6.3.3 FB_DMA_BUFFERS (Read-Only) 39
6.3.4 FB_CONTROL_SIZE (Read -Only) 39
6.3.5 FB_CHANNEL_SIZE (Read-Only) 39
6.4 BAR2: Analog to Digital Converter (ADC) ................................................................................................................................ 40
6.4.1 Function Block Register Map 40
6.4.2 Mode_Status (Read/Write, Read-Only) 40
6.4.3 START_TRIG (Read/Write) 41
6.4.4 STOP_TRIG (Read/Write) 41
6.4.5 CLK_DIV(Read/Write) 41
6.4.6 CLK_DELAY(Read/Write) 42
6.4.7 CLK_READY 42
6.4.8 PRE_TRIGGER_CAPTURE (Read/Write) 42
6.4.9 POST_STOP_CAPTURE (Read/Write) 42
6.4.10 SAMPLE_CNT (Read Only) 42
6.4.11 INT_ENA (Maskable Read/Write) 42
6.4.12 INT_STAT (Read/Clear) 42
6.4.13 CLK_BUSn 43
6.4.14 AD_CONFIG (Maskable Read/Write) 43
6.4.15 ADC_TRIM (Read/Write) 43
6.4.16 ADC_TRIM_BUSY (Read Only) 43
6.4.17 FRONT_END_CONFIG (Maskable Read/Write) 43
6.4.18 FIFO_DATA_CNT (Read) 43
6.4.19 MAX_FIFO_SIZE (Read) 44
6.4.20 FILTER (Read/Write) 44
6.4.21 INT_STAT(Read/Clear) 44
6.4.22 INT_ENA (Read/Write) 45
6.4.23 THRESH_LOW (Read/Write) 45

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6.4.24 THRESH_HIGH (Read/Write) 45
6.4.25 LAST_SAMPLE (Read-Only) 45
6.4.26 CH_FIFO_ACCESS (Read/Write) 45
6.5 BAR2: Digital to Analog Converter (DAC) ................................................................................................................................ 46
6.5.1 Function Block Register Map 46
6.5.2 Mode_Status (Read/Write, Read-Only) 46
6.5.3 START_TRIG (Read/Write) 47
6.5.4 STOP_TRIG (Read/Write) 47
6.5.5 CLK_DIV(Read/Write) 47
6.5.6 CLK_DELAY(Read/Write) 48
6.5.7 CLK_READY 48
6.5.8 POST_STOP_CONVERSIONS (Read/Write) 48
6.5.9 CONVERSION_CNT (Read Only) 48
6.5.10 INT_ENA (Maskable Read/Write) 48
6.5.11 INT_STAT (Read/Clear) 48
6.5.12 CLK_BUSn 49
6.5.13 DA_CONFIG (Maskable Read/Write) 49
6.5.14 DAC_TRIM (Read/Write) 49
6.5.15 DAC_TRIM_BUSY (Read Only) 49
6.5.16 DAC_OFFSET (Read/Write) 49
6.5.17 DAC_OFFSET_BUSY (Read Only) 49
6.5.18 FRONT_END_CONFIG (Maskable Read/Write) 49
6.5.19 FIFO_DATA_CNT (Read) 50
6.5.20 MAX_FIFO_SIZE (Read) 50
6.5.21 INT_STAT (Read/Clear) 50
6.5.22 INT_ENA (Read/Write) 50
6.5.23 LAST_CONVERSION (Read/Write) 50
6.5.24 FIFO_ACCESS (Read/Write) 50
6.6 BAR2: Advanced Digital I/O...................................................................................................................................................... 51
6.6.1 Function Block Register Map 51
6.6.2 Mode_Status (Read/Write, Read-Only) 51
6.6.3 CLK_SRC (Read/Write) 52
6.6.4 START_TRIG (Read/Write) 52
6.6.5 STOP_TRIG (Read/Write) 52
6.6.6 CLK_DIV (Read/Write) 53
6.6.7 CLK_DIV_CNTR (Read Only) 53
6.6.8 PRE_START_COUNT (Read/Write) 53
6.6.9 POST_STOP_COUNT (Read/Write) 53
6.6.10 SAMPLE_CNT (Read Only) 53
6.6.11 INT_ENA (Maskable Read/Write) 53
6.6.12 INT_STAT (Read/Clear) 53
6.6.13 CLK_BUSn 53
6.6.14 ADV_INT_MODE (Read/Write) 54
6.6.15 ADV_INT_MASK (Read/Write) 54
6.6.16 ADV_INT_COMP (Read/Write) 54
6.6.17 ADV_INT_CAPT (Read/Write) 54
6.6.18 MODE_CONFIG (MASKABLE READ/WRITE) 55
6.6.19 PERIPH_SEL_BIT_n (Read/Write) 55
6.6.20 CHn_FIFO_DATA_CNT (Read) 55
6.6.21 CHn_MAX_FIFO_SIZE (Read) 55
6.6.22 CH0_DATA (DIG_IN) (Read Only) 56
6.6.23 CH1_DATA (DIG_OUT) (Read/Write) 56
6.6.24 CH2_DATA (DIG_DIR) (Read/Write) 56
6.6.25 CHn_FIFO_ACCESS (Read/Write) 56
6.1 BAR2: PWM.............................................................................................................................................................................. 57
6.1.1 Function Block Register Map 57
6.1.2 Mode_Status (Read/Write, Read-Only) 57
6.1.3 CLK_SRC (Read/Write) 58
6.1.4 START_TRIG (Read/Write) 58
6.1.5 STOP_TRIG (Read/Write) 58
6.1.6 CLK_DIV (Read/Write) 58
6.1.7 CLK_DIV_CNTR (Read Only) 58
6.1.8 PERIOD_COUNT (Read Only) 59
6.1.9 INT_ENA (Maskable Read/Write) 59

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6.1.10 INT_STAT (Read/Clear) 59
6.1.11 CLK_BUSn 59
6.1.12 CHn_FIFO_DATA_CNT (Read) 59
6.1.13 CHn_MAX_FIFO_SIZE (Read) 59
6.1.14 CHn_PWM_WIDTH (Read/Write) 60
6.1.15 CHn_FIFO_ACCESS (Read/Write) 60
6.2 BAR2: Incremental Encoder ..................................................................................................................................................... 61
6.2.1 Function Block Register Map 61
6.2.2 Mode_Status (Read/Write, Read-Only) 61
6.2.3 CLK_SRC (Read/Write) 62
6.2.4 START_TRIG (Read/Write) 62
6.2.5 STOP_TRIG (Read/Write) 62
6.2.6 CLK_DIV (Read/Write) 62
6.2.7 CLK_DIV_CNTR (Read Only) 62
6.2.8 PRE_START_COUNT (Read/Write) 63
6.2.9 POST_STOP_COUNT (Read/Write) 63
6.2.10 SAMPLE_CNT (Read Only) 63
6.2.11 INT_ENA (Maskable Read/Write) 63
6.2.12 INT_STAT (Read/Clear) 63
6.2.13 CLK_BUSn 63
6.2.14 MODE_CONFIG (MASKABLE READ/WRITE) 64
6.2.15 FIFO_DATA_CNT (Read) 64
6.2.16 MAX_FIFO_SIZE (Read) 64
6.2.17 THRESH_LOW (Read/Write) 64
6.2.18 THRESH_HIGH (Read/Write) 64
6.2.19 INCENC_VALUE (Read/Write) 64
6.2.20 FIFO_ACCESS (Read) 64
6.3 BAR2: External Clocking .......................................................................................................................................................... 65
6.3.1 Function Block Register Map 65
6.3.2 EXT_CLK_IN (Read-Only) 65
6.3.3 EXT_CLK_GATE_IN (Read Only) 65
6.3.4 EXT_CLK_DIR (Read/Write) 65
6.3.5 EXT_CLK_EDGE (Read/Write) 66
6.3.6 EXT_CLKn_PW (Read/Write) 66
6.3.7 EXT_CLKn_CFG (Read/Write) 66
6.4 BAR2: Temperature Sensor ..................................................................................................................................................... 67
6.4.1 Function Block Register Map 67
6.4.2 TEMPERATURE_VAL (Read Only) 67
6.5 BAR2: Clock Generator ............................................................................................................................................................ 67
6.5.1 Function Block Register Map 67
6.5.2 CLK_SEL (Read/Write) 67
6.5.3 PLL_STATUS (Read Only) 68
6.5.4 CLK_SYNC (READ/CLEAR) 68
6.6 BAR2: Capture Window............................................................................................................................................................ 69
6.6.1 Function Block Register Map 69
6.6.2 Mode_Status (Read/Write, Read-Only) 69
6.6.3 CLK_SRC (Read/Write) 70
6.6.4 START_TRIG (Read/Write) 70
6.6.5 CLK_DIV (Read/Write) 70
6.6.6 CLK_DIV_CNTR (Read Only) 70
6.6.7 SAMPLE_CNT (Read Only) 70
6.6.8 INT_ENA (Maskable Read/Write) 70
6.6.9 INT_STAT (Read/Clear) 71
6.6.10 CLK_BUSn 71
6.6.11 CONFIG (Maskable Read/Write) 72
6.6.12 DELAY_COUNTER_n (Read/Write) 72
6.6.13 CAPTURE_COUNTER_n (Read/Write) 72
6.7 BAR2: SyncBus ........................................................................................................................................................................ 73
6.7.1 Function Block Register Map 73
6.7.2 CLK_SEL (Read) 73
6.7.3 PLL_LOCKED (Read Only) 73
6.7.4 TERM_ENABLE (Read/Write) 73

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6.7.5 ENABLE (Read/Write) 73
6.7.6 SB_ n_CLK_SRC (Read/Write) 74
6.7.7 DIRECTION (Read/Write) 74
6.7.8 CLK_BUSn 74
6.7.9 PLL_SYNC (Read/Write) 74
6.7.10 SYNCBUS_MODE (Read/Write) 75
6.7.11 DIG_IN (Read-Only) 75
6.7.12 DIG_OUT (Read/Write) 75
6.8 BAR2: Programmable Clock..................................................................................................................................................... 76
6.8.1 Function Block Register Map 76
6.8.2 Mode_Status (Read/Write, Read-Only) 76
6.8.3 CLK_SRC (Read/Write) 77
6.8.4 START_TRIG (Read/Write) 77
6.8.5 STOP_TRIG (Read/Write) 77
6.8.6 CLK_DIV (Read/Write) 77
6.8.7 CLK_DIV_CNTR (Read Only) 77
6.8.8 COUNT (Read Only) 78
6.8.9 INT_ENA (Maskable Read/Write) 78
6.8.10 INT_STAT (Read/Clear) 78
6.8.11 CLK_BUSn 78
6.8.12 MODE_CONFIG (MASKABLE READ/WRITE) 78
6.8.13 CHn_FIFO_DATA_CNT (Read) 78
6.8.14 CHn_MAX_FIFO_SIZE (Read) 79
6.8.15 INTERVAL_CLK_DIV (Read/Write) 79
6.8.16 LAST_INTERVAL_COUNT (Read-Only) 79
6.8.17 CHn_FIFO_ACCESS (Read/Write) 79
7Troubleshooting 80
8Additional Information 81
8.1 PC/104 Specifications............................................................................................................................................................... 81
8.2 PCI and PCI Express Specification .......................................................................................................................................... 81
9Limited Warranty 82

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BDM-610010057 Rev A
Table of Figures
Figure 1: Gain of 1 FFT .......................................................................................................................................................................................... 13
Figure 2: Gain of 6 FFT .......................................................................................................................................................................................... 14
Figure 3: Board Dimensions ................................................................................................................................................................................... 15
Figure 4: Board Connections .................................................................................................................................................................................. 16
Figure 5: Example 104™Stack............................................................................................................................................................................... 19
Figure 6: IDAN Dimensions .................................................................................................................................................................................... 20
Figure 7: Example IDAN System ............................................................................................................................................................................ 23
Figure 8: DM34116HR Block Diagram ................................................................................................................................................................... 24
Figure 9: Incremental Encoder Signals................................................................................................................................................................... 28
Figure 10: Analog Front End................................................................................................................................................................................... 30
Figure 11:High Impedance Bipolar Example .......................................................................................................................................................... 31
Figure 12:High Impedance Unipolar Example........................................................................................................................................................ 32
Figure 13: Output Circuit......................................................................................................................................................................................... 33
Figure 14: Filter Response with each ORDER Value............................................................................................................................................. 44
Table of Tables
Table 1: Ordering Options ...................................................................................................................................................................................... 11
Table 2: Operating Conditions ................................................................................................................................................................................ 12
Table 3: Electrical Characteristics .......................................................................................................................................................................... 12
Table 4: Functional Characteristics ........................................................................................................................................................................ 13
Table 5: CN3 Digital I/O Pin-out ............................................................................................................................................................................. 17
Table 6: CN5 Pin-out .............................................................................................................................................................................................. 18
Table 7: JP1 User ID Jumper ................................................................................................................................................................................. 18
Table 8: IDAN- DM34116HR 37-Pin High Density "D" Connector ......................................................................................................................... 21
Table 9: Incremental Encoder Inputs...................................................................................................................................................................... 28
Table 10: ADC Full-Scale Settings ......................................................................................................................................................................... 31
Table 11: Function Block Mapping ......................................................................................................................................................................... 34
Table 12: Base Functional Block ............................................................................................................................................................................ 35
Table 13: DMA Registers........................................................................................................................................................................................ 37
Table 14: Functional Block Header......................................................................................................................................................................... 39
Table 15: High Speed A/D Functional Block .......................................................................................................................................................... 40
Table 16: High Speed D/A Functional Block .......................................................................................................................................................... 46
Table 17: Advance DIO Functional Block............................................................................................................................................................... 51
Table 18:PWM Functional Block............................................................................................................................................................................. 57
Table 19: Incremental Encoder Functional Block ................................................................................................................................................... 61
Table 20:External Clocking Functional Block ......................................................................................................................................................... 65
Table 21: Temperature Sensor Functional Block ................................................................................................................................................... 67
Table 22: Clock Generator Functional Block .......................................................................................................................................................... 67
Table 23: Capture Window Functional Block.......................................................................................................................................................... 69
Table 24: SyncBus Functional Block ...................................................................................................................................................................... 73
Table 25: Programmable Clock Functional Block................................................................................................................................................... 76

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1Introduction
1.1 Product Overview
The DM34116HR dataModule is a rugged high-speed data acquisition (DAQ) module in the PCIe/104 format which
boasts two 16-bit 25 MHz A/D converters and two 16-bit 25Mhz D/A converters.
This module provides 2 single-ended analog input channels with software-selectable input ranges and input
impedances. It also providing 2 single-ended analog output channels with a ± 2.5V range and a fixed 50 ohm output
impedance. Each channel has a dedicated converter, permitting both independent or simultaneous conversions.
Additionally, each channel also has a dedicated DMA channel, which ensures the ability for the host controller or a
DSP to continuously collect data from all four channels across the PCIe x4 interfaces.
The DM34116HR also features 32-bit advanced DIO with peripheral output capabilities including a quad PWM and
external clocking. The SyncBus permits multiple DAQ cards to be synchronized within the system.
When used with the RTD’s SPM34CP high-performance DSP, data can be transferred directly to the DSP’s memory
using ta CPU’s PCIe connection.
1.2 Board Features
•PCI Express Bus:
oPCIe/104 Type 2 Board
oPCIe x4 interface (Gen 2 20 GT/s)
oIn-band interrupts and messages
oMessage Signaled Interrupt (MSI) support
•Analog inputs:
o2 high-speed inputs with independent sampling, or simultaneous sampling
o25 MSPS maximum input sampling rate
o16-bit resolution
oSingle-ended inputs
oProgrammable 50 ohm or high impedance input
oProgrammable input full-scale ranges in bipolar mode: ±1.667V, ±1.25V, ±0.833V, ±0.625V,
±0.4167V
▪Only available in high impedance mode: ±5V, ±3.3V
oProgrammable input full-scale ranges in Unipolar mode: 0-3.3V, 0-2.5V, 0-1.67V, 0-1.25V, 0-
0.8333V
▪Only available in high impedance mode: 0-5V
oSampling modes and triggers are configurable independently
oThreshold detection can generate an interrupt, or be used as a start or stop trigger
o2 MMCX connectors
•Analog Outputs:
o2 high-speed inputs with independent, or simultaneous operation
o1-25Mhz DAC update rates
o16-bit resolution
oSingle-ended outputs
o50 ohm output impedance
o±2.5V Output range with adjustable offset
o2 MMCX connectors
•SyncBus
oAllows synchronization of the sampling clock on multiple boards
oAllows synchronization of start and stop triggers on multiple boards
oSoftware selectable Master/Slave
oSoftware selectable termination
•Selectable 10Mhz Reference
oOnboard
oSyncBus
oExternal via MMCX connector
•Digital I/O
o32 channels