rtd DM35418HR User manual

RTD Embedded Technologies, Inc.
AS9100 and ISO 9001 Certified
DM35418HR/DM35218HR
PCI Express Data Acquisition Board
User’s Manual
BDM-610010041 Rev F

RTD Embedded Technologies, Inc. | www.rtd.com ii DM35418HR/DM35218HR User’s Manual
BDM-610010041 Rev F
RTD Embedded Technologies, Inc.
103 Innovation Boulevard
State College, PA 16803 USA
Telephone: [phone]
Fax: [phone]
www.rtd.com
[email protected]
[email protected]

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BDM-610010041 Rev F
Revision History
Rev A Initial Release
Rev B Added DM35218 information, updated 68-pin IDAN connector pin out
Rev C Updated 62-Pin IDAN connector pin out, changed all reference of A/D to ADC, changed all reference of D/A to DAC
Rev D Added Section 3.3.5 LEDs
CN5 was removed from factory use only
Removed generic text from sections 6.3.17 and 6.4.16
Removed gain from ADC voltage formula
Removed Note from sections 6.3.17 and 6.4.16
Added table to section 6.4.16
CN3’s 3.3V load capability added to section 2.2
Add Clock Source description
Added CHn_FIFO_DATA_CNT register description to ADC and DAC Functional Blocks
Updated IDAN dimension drawing
Updated FFT Specifications
Rev E 40 MHz system clock frequency specified in section 6.1.7
In the digital IO section of Table 3, the symbols for the Input High Voltage and Input Low Voltage were swapped.
Rev F Changed formatting to Section 6
Added sections Temperature Sensor, Digital I/O and Functional Characteristics
Updated power consumption
Advanced Analog I/O, Advanced Digital I/O, aAIO, aDIO, a2DIO, Autonomous SmartCal, “Catch the Express”, cpuModule, dspFramework, dspModule, expressMate, ExpressPlatform, HiDANplus, “MIL Value for
COTS prices”, multiPort, PlatformBus, and PC/104EZ are trademarks, and “Accessing the Analog World”, dataModule, IDAN, HiDAN, RTD, and the RTD logo are registered trademarks of RTD Embedded
Technologies, Inc (formerly Real Time Devices, Inc.). PS/2 is a trademark of International Business Machines Inc. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PC/104, PC/104-Plus, PCI-104, PCIe/104,
PCI/104-Express and 104 are trademarks of the PC/104 Embedded Consortium. All other trademarks appearing in this document are the property of their respective owners.
Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed
by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not
be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.
Copyright © 2016 by RTD Embedded Technologies, Inc. All rights reserved.
Advanced Analog I/O, Advanced Digital I/O, aAIO, aDIO, a2DIO, Autonomous SmartCal, “Catch the Express”, cpuModule, dspFramework, dspModule, expressMate, ExpressPlatform, HiDANplus, “MIL Value for
COTS prices”, multiPort, PlatformBus, and PC/104EZ are trademarks, and “Accessing the Analog World”, dataModule, IDAN, HiDAN, RTD, and the RTD logo are registered trademarks of RTD Embedded
Technologies, Inc (formerly Real Time Devices, Inc.). PS/2 is a trademark of International Business Machines Inc. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PC/104, PC/104-Plus, PCI-104, PCIe/104,
PCI/104-Express and 104 are trademarks of the PC/104 Embedded Consortium. All other trademarks appearing in this document are the property of their respective owners.
Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed
by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not
be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.
Copyright © 2016 by RTD Embedded Technologies, Inc. All rights reserved.

RTD Embedded Technologies, Inc. | www.rtd.com iv DM35418HR/DM35218HR User’s Manual
BDM-610010041 Rev F
Table of Contents
1Introduction 8
1.1 Product Overview........................................................................................................................................................................ 8
1.2 Board Features ........................................................................................................................................................................... 8
1.3 Ordering Information................................................................................................................................................................... 8
1.4 Contact Information .................................................................................................................................................................... 9
1.4.1 Sales Support 9
1.4.2 Technical Support 9
2Specifications 10
2.1 Operating Conditions ................................................................................................................................................................ 10
2.2 Electrical Characteristics .......................................................................................................................................................... 10
2.1 Functional Characteristics ........................................................................................................................................................ 11
2.1.1 Analog Input FFT plots 12
2.1.2 Analog input histograms 12
3Board Connection 13
3.1 Board Handling Precautions ..................................................................................................................................................... 13
3.2 Physical Characteristics............................................................................................................................................................ 13
3.3 Connectors and Jumpers.......................................................................................................................................................... 14
3.3.1 Bus Connectors 14
CN1(Top) & CN2(Bottom): PCIe Connector 14
3.3.2 External I/O Connectors 15
CN3: Digital I/O Connector 15
CN4: Analog I/O Connector 16
CN5: SyncBus Connector 16
Other Connectors 16
3.3.3 Jumpers 16
3.3.4 LEDs 17
LED 0: Clock Reset 17
LED 1: Clock Status 17
LED 2: SYNCBUS Lock 17
LED 3: Clock Select 17
3.4 Steps for Installing .................................................................................................................................................................... 18
4IDAN Connections 19
4.1 Module Handling Precautions................................................................................................................................................... 19
4.2 Physical Characteristics............................................................................................................................................................ 19
4.3 Connectors................................................................................................................................................................................ 20
4.3.1 DM35418 External I/O Connectors 20
Analog I/O and SyncBus Connector - 68-pin Subminiature “D” Female Connector 20
Analog I/O and SyncBus Connector - 62-pin High Density “D” Female Connector 21
Digital I/O Connector - 37-pin High Density “D” Female Connector 22
4.3.2 DM35218 External I/O Connectors 23
Analog I/O and SyncBus Connector - 68-pin Subminiature “D” Female Connector 23
Analog I/O and SyncBus Connector - 62-pin High Density “D” Female Connector 24
Digital I/O Connector - 37-pin High Density “D” Female Connector 25
4.3.3 Bus Connectors 26
CN1(Top) & CN2(Bottom): PCIe Connector 26
4.4 Steps for Installing .................................................................................................................................................................... 26
5Functional Description 27
5.1 Block Diagram........................................................................................................................................................................... 27
5.2 FPGA with DMA Engine ........................................................................................................................................................... 27

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BDM-610010041 Rev F
5.3 SyncBus.................................................................................................................................................................................... 27
5.4 Digital I/O .................................................................................................................................................................................. 28
5.5 Temperature Sensor................................................................................................................................................................. 28
5.6 Analog input.............................................................................................................................................................................. 28
Single-Ended Input Mode 28
Differential Input Mode 28
Full-Scale Input Range 28
Bipolar/Unipolar Mode 28
5.6.1 Initializing the ADC Converter 29
5.6.2 Simplified block diagram of analog input 29
5.6.3 Input connection examples 30
5.4.3.1. Single Ended, Bipolar, ±10V Full-scale range 30
5.4.3.2. Differential, Bipolar, ±10V Full-scale range 30
5.4.3.3. Single Ended, Unipolar, 0-10V Full-scale range 31
5.4.3.4. Differential, Unipolar, 0-10V Full-scale range 31
5.4.3.5. ADC Gain and Offset Test 32
5.7 Analog output............................................................................................................................................................................ 32
5.7.1 Initializing the DAC Converter 32
5.7.2 Simplified block diagram of analog output 33
6Register Address Space 34
Register Types 34
Function Block Mapping 34
6.1 BAR0: General Board Control .................................................................................................................................................. 35
6.1.1 GBC_FMT (Read-Only) 35
6.1.2 GBC_REV (Read-Only) 35
6.1.3 GBC_BRD_RST (Read/Write) 35
6.1.4 GBC_PDP (Read-Only) 35
6.1.5 GBC_BUILD (Read-Only) 35
6.1.6 GBC_SYS_CLK_FREQ (Read Only) 35
6.1.7 GBC_USER_ID (Read Only) 36
6.1.8 GBC_IRQ_STATUS (Read/Clear) 36
6.1.9 GBC_DIRQ_STATUS (Read/Clear) 36
6.1.10 GBC_EOI (Read/Clear) 36
6.1.11 FBn_ID (Read-Only) 36
6.1.12 FBn_Offset (Read-Only) 36
6.1.13 FBn_Offset_DMA (Read-Only) 36
6.2 BAR2: Functional Block Standard DMA ................................................................................................................................... 37
6.2.1 FB_DMAm_Action (Read/Write) 37
6.2.2 FB_DMAm_Last_Action (Read/Write) 37
6.2.3 FB_DMAm_Setup (Read/Write) 37
6.2.4 FB_DMAm_Stat_Used (Read/Write) 38
6.2.5 FB_DMAm_Stat_Invalid (Read/Write) 38
6.2.6 FB_DMAm_Stat_Overflow (Read/Write) 38
6.2.7 FB_DMAm_Stat_Underflow (Read/Write) 38
6.2.8 FB_DMAm_Stat_Complete (Read/Write) 38
6.2.9 FB_DMAm_Current_Buffer (Read-Only) 38
6.2.10 FB_DMAm_COUNT (Read-Only) 38
6.2.11 FB_DMAm_RD_FIFO_CNT(Read-Only) 38
6.2.12 FB_DMAm_WR_FIFO_CNT(Read-Only) 38
6.2.13 FB_DMAm_ADDRESSn (Read/Write) 38
6.2.14 FB_DMAm_SIZEn (Read/Write) 38
6.2.15 FB_DMAm_CTRLn (Read/Write) 39
6.2.16 FB_DMAm_STATn (Read/Clear) 39
6.3 BAR2: Functional Block Header Registers............................................................................................................................... 39
6.3.1 FB_ID (Read-Only) 39
6.3.2 FB_DMA_CHANNELS (Read -Only) 39
6.3.3 FB_DMA_BUFFERS (Read-Only) 39
6.4 BAR2: Analog to Digital Converter (ADC) ................................................................................................................................ 40
6.4.1 Function Block Register Map 40
6.4.2 Mode_Status (Read/Write, Read-Only) 40
6.4.3 CLK_SRC (Read/Write) 41

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BDM-610010041 Rev F
6.4.4 START_TRIG (Read/Write) 41
6.4.5 STOP_TRIG (Read/Write) 41
6.4.6 CLK_DIV (Read/Write) 41
6.4.7 CLK_DIV_CNTR (Read Only) 41
6.4.8 PRE_TRIGGER_CAPTURE (Read/Write) 42
6.4.9 POST_STOP_CAPTURE (Read/Write) 42
6.4.10 SAMPLE_CNT (Read Only) 42
6.4.11 INT_ENA (Maskable Read/Write) 42
6.4.12 INT_STAT (Read/Clear) 42
6.4.13 CLK_SRC_GBLn 42
6.4.14 AD_CONFIG (Maskable Read/Write) 42
6.4.15 CH_FRONT_END_CONFIG (Maskable Read/Write) 43
6.4.16 CHn_FIFO_DATA_CNT (Read) 43
6.4.17 CH_FILTER (Read/Write) 43
6.4.18 CH_INT_STAT(Read/Clear) 44
6.4.19 CH_INT_ENA (Read/Write) 44
6.4.20 CH_THRESH_LOW (Read/Write) 44
6.4.21 CH_THRESH_HIGH (Read/Write) 44
6.4.22 CH_LAST_SAMPLE (Read-Only) 44
6.5 BAR2: Digital to Analog Converter (DAC) ................................................................................................................................ 45
6.5.1 Function Block Register Map 45
6.5.2 Mode_Status (Read/Write, Read-Only) 45
6.5.3 CLK_SRC (Read/Write) 46
6.5.4 START_TRIG (Read/Write) 46
6.5.5 STOP_TRIG (Read/Write) 46
6.5.6 CLK_DIV (Read/Write) 46
6.5.7 CLK_DIV_CNTR (Read Only) 46
6.5.8 POST_STOP_CONVERSIONS (Read/Write) 47
6.5.9 CONVERSION_CNT (Read Only) 47
6.5.10 INT_ENA (Maskable Read/Write) 47
6.5.11 INT_STAT (Read/Clear) 47
6.5.12 CLK_SRC_GBLn 47
6.5.13 DA_CONFIG (Maskable Read/Write) 47
6.5.14 CH_FRONT_END_CONFIG (Maskable Read/Write) 47
6.5.15 CHn_FIFO_DATA_CNT (Read) 48
6.5.16 CH_INT_STAT (Read/Clear) 48
6.5.17 CH_INT_ENA (Read/Write) 48
6.5.18 CH_LAST_CONVERSION (Read/Write) 48
6.6 BAR2: Digital I/O (DIO)............................................................................................................................................................. 49
6.6.1 Function Block Register Map 49
6.6.2 DIO_INPUT_VAL (Read Only) 49
6.6.3 DIO_OUTPUT_VAL (Read/Write) 49
6.6.4 DIO_DIRECTION (Read/Write) 49
6.7 BAR2: Temperature Sensor ..................................................................................................................................................... 50
6.7.1 Function Block Register Map 50
6.7.2 TEMPERATURE_VAL (Read Only) 50
6.8 BAR2: SyncBus Driver.............................................................................................................................................................. 51
6.8.1 Function Block Register Map 51
6.8.2 CLK_SEL (Read/Clear) 51
6.8.3 PLL_LOCKED (Read Only) 51
6.8.4 TERM_ENABLE (Read/Write) 51
6.8.5 ENABLE (Read/Write) 51
6.8.6 SB_ n_CLK_SRC (Read/Write) 52
6.8.7 DIRECTION (Read/Write) 52
6.8.8 CLK_SRC_GBLn 52
7Troubleshooting 53
8Additional Information 54
8.1 PC/104 Specifications............................................................................................................................................................... 54
8.2 PCI and PCI Express Specification .......................................................................................................................................... 54
9Limited Warranty 55

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BDM-610010041 Rev F
Table of Figures
Figure 1: Channel FFT............................................................................................................................................................................................ 12
Figure 2: Histogram ................................................................................................................................................................................................ 12
Figure 3: Board Dimensions ................................................................................................................................................................................... 13
Figure 4: Board Connections .................................................................................................................................................................................. 14
Figure 5: Example 104™Stack............................................................................................................................................................................... 18
Figure 6: IDAN Dimensions .................................................................................................................................................................................... 19
Figure 7: Example IDAN System ............................................................................................................................................................................ 26
Figure 8: DM35418HR/DM35218HR Block Diagram ............................................................................................................................................. 27
Figure 9: Analog Input Front End............................................................................................................................................................................ 29
Figure 10: Bipolar Single-Ended Example.............................................................................................................................................................. 30
Figure 11: Bipolar Differential Example .................................................................................................................................................................. 30
Figure 12: Unipolar Single Ended Example............................................................................................................................................................ 31
Figure 13: Unipolar Differential Example................................................................................................................................................................ 31
Figure 14: Bipolar Offset and Gain Test Circuit...................................................................................................................................................... 32
Figure 15: Analog Output........................................................................................................................................................................................ 33
Figure 16: Filter Response with each ORDER Value............................................................................................................................................. 43
Table of Tables
Table 1: Ordering Options ........................................................................................................................................................................................ 8
Table 2: Operating Conditions ................................................................................................................................................................................ 10
Table 3: Electrical Characteristics .......................................................................................................................................................................... 10
Table 4: Functional Characteristics ........................................................................................................................................................................ 11
Table 5: CN3 Single-Ended Mode Pin-out.............................................................................................................................................................. 15
Table 6: CN4 Differential Mode Pin-out.................................................................................................................................................................. 16
Table 7: CN4 Single-Ended Mode Pin-out.............................................................................................................................................................. 16
Table 8: CN5 Pin-out ............................................................................................................................................................................................. 16
Table 9: IDAN- DM35418 68-Pin Subminiature "D" Connector.............................................................................................................................. 20
Table 10: IDAN- DM35418 62-Pin High Density "D" Connector............................................................................................................................. 21
Table 11: IDAN- DM35418 37-Pin High Density "D" Connector............................................................................................................................. 22
Table 12: IDAN- DM35218 68-Pin Subminiature "D" Connector............................................................................................................................ 23
Table 13: IDAN- DM35218 62-Pin High Density "D" Connector............................................................................................................................. 24
Table 14: IDAN- DM35218 37-Pin High Density "D" Connector............................................................................................................................. 25
Table 15: ADC Full-Scale Settings ......................................................................................................................................................................... 29
Table 16: DAC Full-Scale Settings ......................................................................................................................................................................... 33
Table 17: Key DAC Bit Weight................................................................................................................................................................................ 33
Table 18: Function Block Mapping ......................................................................................................................................................................... 34
Table 19: Base Functional Block ............................................................................................................................................................................ 35
Table 20: DMA Registers........................................................................................................................................................................................ 37
Table 21: Functional Block Header......................................................................................................................................................................... 39
Table 22: Multi-Channel A/D Functional Block ....................................................................................................................................................... 40
Table 23: Multi-Channel DAC Functional Block ..................................................................................................................................................... 45
Table 24: DAC Full-Scale Settings ......................................................................................................................................................................... 47
Table 25: Digital I/O Functional Block..................................................................................................................................................................... 49
Table 26: Temperature Sensor Functional Block ................................................................................................................................................... 50
Table 27: SyncBus Functional Block ...................................................................................................................................................................... 51

RTD Embedded Technologies, Inc. | www.rtd.com 8DM35418HR/DM35218HR User’s Manual
BDM-610010041 Rev F
1Introduction
1.1 Product Overview
The DM35418 is a software configurable high-speed, 18-bit data acquisition module in the PCIe/104 format. This module provides 8 differential
or single-ended analog input channels, with programmable gain and input ranges. This module is capable of either independent or simultaneous
sampling. The DM35418 also features eight 16-bit high-speed analog outputs with programmable output ranges, and a 32-bit port of digital I/O,
and synchronization of multiple boards with the SyncBus.
The DM35218 is a software configurable high-speed, 18-bit data acquisition module in the PCIe/104 format. This module provides 4 differential
or single-ended analog input channels, with programmable gain and input ranges. This module is capable of either independent or simultaneous
sampling. The DM35218 also features four 16-bit high-speed analog outputs with programmable output ranges, and a 32-bit port of digital I/O,
and synchronization of multiple boards with the SyncBus.
1.2 Board Features
PCI Express Bus:
oPCIe/104 Universal Board
Interfaces with Type 1 or Type 2 bus
Lane repopulation allows maximum system expansion
oProvides 2.5 Gbps in each direction
oIn-band interrupts and messages
oMessage Signaled Interrupt (MSI) support
Analog inputs:
o4/8 channels, high-speed inputs with independent sampling, or simultaneous sampling
o1.538 MSPS maximum input sampling rate
o18-bit resolution
oProgrammable single ended or differential inputs per channels
oProgrammable input full-scale ranges in bipolar mode: ±10V, ±5V, ±2.5V, ±1.25V, ±0.625V,
oProgrammable input full-scale ranges in unipolar mode: 0-10V, 0-5V, 0-2.5V 0-1.25V
oSampling modes and triggers are configurable independently
oThreshold detection can generate an interrupt, or be used as a start or stop trigger
oConfigurable IIR filter on each channel
Analog outputs:
o4/8 channels high-speed
o16-bit D/A converters
oMSPS maximum update rate
oOutput full-scale ranges: ±2.5V, ±5V, ±10V
SyncBus
oAllows synchronization of the sampling clock on multiple boards
oAllows synchronization of start and stop triggers on multiple boards
oSoftware selectable Master/Slave
oSoftware selectable termination
Digital I/O
o32-bit port of digital I/O
oBit programmable direction
o5V Tolerant TTL Signaling level
1.3 Ordering Information
The DM35418HR/DM35218HR is available with the following options:
Table 1: Ordering Options
Part Number
Description
DM35418HR
PCIe/104 Analog I/O dataModule
DM35218HR
PCIe/104 Analog I/O dataModule
IDAN-DM35418HR-62S
PCIe/104 Analog I/O dataModule in IDAN enclosure with 62-pin D-Sub Connector
IDAN-DM35218HR-62S
PCIe/104 Analog I/O dataModule in IDAN enclosure with 62-pin D-Sub Connector

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BDM-610010041 Rev F
Table 1: Ordering Options
Part Number
Description
IDAN-DM35418HR-68S
PCIe/104 Analog I/O dataModule in IDAN enclosure with 68-pin High-Density
Connector
IDAN-DM35218HR-68S
PCIe/104 Analog I/O dataModule in IDAN enclosure with 68-pin High-Density
Connector
The Intelligent Data Acquisition Node (IDAN®) building block can be used in just about any combination with other IDAN building blocks to
create a simple but rugged 104™ stack. This module can also be incorporated in a custom-built RTD HiDAN®or HiDANplus®High Reliability
Intelligent Data Acquisition Node. Contact RTD sales for more information on our high reliability systems.
1.4 Contact Information
1.4.1 SALES SUPPORT
For sales inquiries, you can contact RTD Embedded Technologies sales via the following methods:
Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]
1.4.2 TECHNICAL SUPPORT
If you are having problems with your system, please try the steps in the Troubleshooting section of this manual on page 53.
For help with this product, or any other product made by RTD, you can contact RTD Embedded Technologies technical support via the following
methods:
Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]

RTD Embedded Technologies, Inc. | www.rtd.com 10 DM35418HR/DM35218HR User’s Manual
BDM-610010041 Rev F
2Specifications
2.1 Operating Conditions
Table 2: Operating Conditions
Symbol
Parameter
Test Condition
Min
Max
Unit
Vcc5
5V Supply Voltage
4.75
5.25
V
Vcc3
3.3V Supply Voltage
n/a
n/a
V
Vcc12
12V Supply Voltage
n/a
n/a
V
Vcc-12
-12V Supply Voltage
n/a
n/a
V
Ta
Operating Temperature
-40
+85
C
Ts
Storage Temperature
-55
+125
C
RH
Relative Humidity
Non-Condensing
0
90%
%
MTBF
Mean Time Before Failure
Telcordia Issue 2
30°C, Ground
benign, controlled
DM35418HR
970,115
Hours
DM35218HR
1,106,548
Hours
2.2 Electrical Characteristics
Table 3: Electrical Characteristics
Symbol
Parameter
Test Condition
Min
Typical
Max
Unit
P
Power Consumption1
DM35418HR: Vcc5 = 5.0V
8.85
W
DM35218HR: Vcc5 = 5.0V
5.9
W
Icc5
5V Input Supply Current
DM35418HR: Active
1.77
A
DM35218HR: Active
1.18
A
PCIe/104 Bus
Differential Output Voltage
0.8
1.2
V
DC Differential TX Impedance
80
120
Ω
Differential Input Voltage
0.175
1.2
V
DC Differential RX Impedance
80
120
Ω
Electrical Idle Detect Threshold
65
175
mV
Analog to Digital Converter
Linear Input Voltage
IN+ or IN -
-10
10
V
FSR
Full-scale Differential Input
Voltage
VIN = (IN+ - IN-)
G = PGA Gain
-5
G
4.99996
G
V
Resolution
18
Bits
Data Rate
1.5385
MSPS
Input Impedance
1.25
MΩ
ENOB
Input = 0.5dBFS @ 10kHz
Differential Inputs, ±10V
15.03
Bits
SNR
Input = 0.5dBFS @ 10kHz
Differential Inputs, ±10V
92.24
dB
SINAD
Input = 0.5dBFS @ 10kHz
Differential Inputs, ±10V
81.83
dB
THD
Input = 0.5dBFS @ 10kHz
Differential Inputs, ±10V
-82.19
dB
SFDR
Input = 0.5dBFS @ 10kHz
Differential Inputs, ±10V
92.19
dB
Third Order Intermodulation
Input = Combination of
10Khz @ -8dB and 11Khz
@ -8dB
83.36
dB
Noise Free Bits
Inputs Grounded
Differential Inputs, ±10V
14.19
Bits
G
Gains
0.5,1,2,4,8
Digital to Analog Converter
Full-scale Analog Output Voltage
G=1
-2.5
+2.49998
V
Resolution
16
Bits
INL
Relative Accuracy
±2
LSB