Samsung BL8531H User manual

TheBL8531H_ADCisaCMOS12bit analog-to-digital
converter (ADC).Itconvertsthe analog inputsignal
into 12bit binary digitalcodesatamaximum
sampling rateof10MHz.
Thedevice isamonolithicADCwithan on-chip,
high-performance,sample-and-holdAmplifier (SHA)
and currentreferenc.Thestructure allowsboth
differentialand single-endedinput.
This12bit ADChasalso3channelMUX,so 3
channel inputsare acceptable.
-Resolution :12bit
-MaximumConversion Rate:10MHz
-PowerSupply:5V
-PowerConsumption :100mW(typical)
-Reference Voltage:3.5V,1.5V(dualreference)
-InputRange:0.5V~4.5V(4.0VP-P)
-DifferentialLinearityError:±0.7LSB
-IntegralLinearityError:±1.0LSB
-Signal toNoise&Distortion Ratio:65dB
-TotalHarmonicDistortion :74dB
-3ChannelInputs
-DigitalOutput:CMOSLevel
-Operating TemperatureRange:0ºC~70ºC
GENERALDESCRIPTIONFEATURES
FUNCTIONAL BLOCKDIAGRAM
CCDImaging (Copiers,Scanners,Cameras)
MedicalInstruments
DigitalCommunication Systems
TYPICALAPPLICATIONS
12BIT10MSPSADC BL8531H_ADC
SAMSUNG ELECTRONICSCo.LTD
Ver 1.1(Apr.2002)
Noresponsibilityisassumed by SECforitsusenor forany infringementsofpatents
orother rightsofthird partiesthatmayresult fromitsuse.The contentofthis
datasheet is subject tochangewithoutany notice.
SHA MDAC
2
MDAC
1MDAC 3
FLASH
1FLASH
2FLASH
3FLASH
4
DIGITAL
LOGIC
CLOCK
GEN.
3CH.
Analog
Inputs
Reference
Input
Clock
Digital
Output
Main
Bias
12
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12BIT10MSPSADC
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COREPIN DESCRIPTION
NAMEI/OTYPEI/OPAD PIN DESCRIPTION
REFTOPAO poar10_bb Reference Top Force (3.5V)
REFBOTAO poar10_bb Reference BottomForce (1.5V)
CMLAO poar10_bb InternalBias
VDDA APvddaAnalog Power (5V)
VBB AG vbbaAnalog Sub Bias
VSSA AG vssaAnalog Ground
R_INPAIpiar10_bb Analog Input(RED)+
(InputRange:1.5V~3.5V)
R_INN AIpiar10_bb Analog Input(RED) -
(InputRange:1.5V~3.5V)
G_INPAIpiar10_b Analog Input(GREEN)+
(InputRange:1.5V~3.5V)
G_INN AIpiar10_bb Analog Input(GREEN) -
(InputRange:1.5V~3.5V)
B_INPAIpiar10_bb Analog Input(BLUE)+
(InputRange:1.5V~3.5V)
B_INN AIpiar10_bb Analog Input(BLUE) -
(InputRange:1.5V~3.5V)
REDBDIpicc_bb REDChannelSelect(0:select)
GREENBDIpicc_bb GREENChannelSelect(0:select)
BLUEBDIpicc_bb BLUEChannelSelect(0:select)
STBY DIpicc_bb VDD=powersaving (standby),
GND=normal
CKIN DIpicc_bb Sampling ClockInput
D[11:0]DO pot4_bb DigitalOutput
VSSD DG vssdDigitalGND
VDDD DPvddd DigitalPower (5V)
I/OTYPE ABBR.
-AI:Analog Input
-DI:DigitalInput
-AO :Analog Output
-DO :Analog Output
-AP:Analog Power
-AG :Analog Ground
-DP:DigitalPower
-DG :DigitalGround
-AB:Analog Bidirection
-DB:DigitalBidirection
STBYCKIN
REFBOTCML
bl8531h_adc
R_INN
R_INP
REFTOP
vddavssavbb vddd vssd
D[11:0]
[MSB:LSB]
B_INN
B_INP
G_INN
G_INP
¢¸ REDB
¢¸ GREENB
¢¸ BLUEB
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ABSOLUTE MAXIMUMRATINGS
CharacteristicsSymbolValueUnit
SupplyVoltageVDD 6.0V
Analog InputVoltageR_INP/R_INN G_INP/G_INN
B_INP/B_INN VSS toVDD V
DigitalInputVoltageCLK VSS toVDD V
StorageTemperatureRangeTstg-45 to 150 ºC
Operating TemperatureRangeTopr0to 70 ºC
NOTES
1.Absolutemaximumrating specifiesthevaluesbeyond whichthedevice may bedamaged permanently.Exposureto
ABSOLUTE MAXIMUMRATING conditionsforextended periodsmayaffectreliability.Eachcondition valueis
appliedwiththeothervalueskeptwithinthefollowing operating conditionsand function operation underany ofthese
conditionsisnot implied.
2.All voltagesaremeasuredwithrespect toVSS unless otherwisespecified.
3.100pFcapacitorisdischargedthrough a1.5kΩresistor (Human body model)
RECOMMENDEDOPERATINGCONDITIONS
CharacteristicsSymbolMinTypMax Unit
SupplyVoltage
VDDA1
VDDA2
VDDA3
4.75 5.0 5.25 V
Analog InputVoltageR_INP/G_INP/B_INP
R_INN/G_INN/B_INN
0.5-
2.5
4.5V
Operating TemperatureToper0-70 ºC
NOTES
It is stronglyrecommendedthatall thesupply pins(VDDA,VDDD)bepoweredfromthesamesource toavoid power
latch-up.
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DCELECTRICALCHARACTERISTICS
CharacteristicsSymbolMinTypMax UnitTestCondition
Differential
NonlinearityDNL-±0.7±1LSB
REFTOP=3.5V
REFBOT=1.5V
Integral
NonlinearityINL-±1.0-LSB
Offset
VoltageOFF -10 -mV
(ConverterSpecifications:VDDA=VDDD=5V,VSSA=VSSD=0V,
Toper=25°C,REFTOP=3.5V,REFBOT=1.5Vunless otherwisespecified)
AC ELECTRICALCHARACTERISTICS
CharacteristicsSymbolMinTypMax UnitTestCondition
Maximum
Conversion Ratefc-10 MHz
AINR=R_INP-R_INN
AING=G_INP-G_INN
AING=B_INP-B_INN
DynamicSupply
CurrentIVDD -20 mAfc=10MHz (withoutsystemload)
Signal-to-Noise&
Distortion RatioSNDR-65 -dBAIN=1MHz, DifferentialInput
TotalHarmonic
Distortion THD -74 -dBAIN=1MHz, DifferentialInput
(Conversion Specifications:VDDA=VDDD=5V,VSSA=VSSD=0V,
Toper=25°C,REFTOP=3.5V,REFBOT=1.5Vunless otherwisespecified)
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I/OCHART
IndexR_INPInput (V)R_INN Input (v)DigitalOutput
0 0.500 ~0.501 2.5 0000 0000 0000
REDChannelInput
Full Scale=4V
1LSB=0.977mV
REFTOP=3.5V
REFBOT=1.5V
1 0.501 ~1.502 2.5 0000 0000 0001
2 0.502 ~1.503 2.5 0000 0000 0010
¡¦ ¡¦ ¡¦
8197 2.499 ~2.5000 2.5 0111 1111 1111
8192 2.500 ~2.501 2.5 1000 0000 0000
8193 2.501 ~2.502 2.5 1000 0000 0001
¡¦ ¡¦ ¡¦
16381 4.497 ~4.498 2.5 1111 1111 1101
16382 4.498 ~4.499 2.5 1111 1111 1110
16383 4.499 ~4.500 2.5 1111 1111 1111
TIMINGDIAGRAM
A1A2
D1D2D3D4D5
A5
R_INP
G_INP
B_INP
CKIN
D[11:0]
InputSampling Period
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FUNCTIONALDESCRIPTION
1.TheBL8531H_ADCisaCMOSfourstep pipelinedAnalog-to-DigitalConverter.Itcontains4-bit flashA/D
Converters,three 3bit flashA/Dconvertersand three multiplying D/AConvertors.TheN-bit flashADCis
composed of2N-1latchedcomparators,and multiplying DACiscomposed of2*(2N+1)capacitorsand two
fully-differentialamplifiers.
2.TheBL8531H_ADCoperatesasfollows.During thefirst"L"cycleofexternalclockthe analog inputdatais
sampled,and theinput isheldfromtherising edgeofthe externalclock,whichisfedtothefirst4-bit flash
ADC,and thefirstmultiplying DAC.Multiplying DACreconstructsavoltage corresponding tothefirst4-bit
ADC'soutput,and finallyamplifiesaresiduevoltageby 24.Thesecond and thirdflashADC,and MDACare
workedas samemanner.Finallyamplifiedresiduevoltage at thethirdmultiplying DACisfedtothelast3-bit
flashADCdecidesfinal3-bit digitaldigitalcode.
3.BL8531H_ADChasthe errorcorrection scheme,which handlestheoutputfrom mismatchinthefirst,second,third
and fourthflashADC.
MAINBLOCKDESCRIPTION
1.SHA
SHA (Sample-and-HoldAmplifier) isthe circuit thatsamplesthe analog inputsignaland holdthatvalueuntil next
sample-time.It isgood as small asitsdifferentvaluebetweenanalog inputsignaland outputsignal.SHA amp
gainishigherthan 70dBat10MHz conversion rate,its settling-timemustbeshortenthan 38nswithless than 1/2
LSBerrorvoltage at12bit resolution.ThisSHA isconsistof fully differentialop amp,switching tr.and sampling
capacitor.Thesampling clockisnon-overlapping clock(Q1,Q2)and sampling capacitorvalueisabout4pF.SHA
usesindependentbiasto protect interruption ofany othercircuit.SHA ampisdesignedthatopen-loop dcgainis
higherthan 70dB,phasemarginishigherthan 60 degrees.Itsinputblockisdesignedto betherail-to-rail
architectureusing complementary differentpair.
2.FLASH
The4-bit flashconverterscompare analog signal(SAH output)withreference voltage,and thatresultstransferto
MDACand digitalcorrection logicblock.It isrealizedfully differentialcomparatorsof15EA.Considering
self-offset,dynamicfeedthrough error,it should distinguish 40mVat least.First,the comparatorschargethe
reference voltage at thesampling capacitorsbeforetransferredSHA output.Thatoperation isperformed on thephase
ofQ2,and discharging on thephaseofQ1.That is,the comparatorscomparerelativedifferentvaluesdual input
voltagewith dualreference voltage.Itsoutputduring Q1 operation is storedat thepre-latch blockbyQ1P.
3.MDAC
MDACisthemost importantblockat thisADCand it decidesthe characteristics.MDACisconsistoftwostage
op amp,selection logic and capacitorarray(c_array).c_array'scompositionsarethe capacitorstochargethe analog
inputand and thereference voltage,switchestocontrol thepath.Selection logic controlsthe c_arrayinternal
switches.If Q1ishigh,selection'soutputare all low,theswitchesoftsw1areoff,theswitchesoftsw2are all
on.Thereforethe capacitorsofc_arraycancharge analog inputvaluesheldatSHA.
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CORE EVALUATIONGUIDE
1.ADCfunction isevaluatedbyexternalcheck on thebidirectionalpadsconnectedtoinputnodesofHOSTDSP
back-end circuit.
2.If Userwant thespecific analog inputrange,thereference voltagesmay beforced.
D[110]
DigitalMux
Bidirectional
PAD
HOST
DSP
CORE
D[11:0]
D[110]
(ADCFunction Test&
externallyforcedDigitalInput)
bl8531h_adc
R_INN
R_INP
REFTOP
vddavssavbb vddd vssd
D[11:0]
[MSB:LSB]
B_INN
B_INP
G_INN
G_INP
¢¸ REDB
¢¸ GREENB
¢¸ BLUEB
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USERGUIDE
1.InputChannelSelect
-REDB,GREENB,BLUEB
-only 1 channelshoud beselected
- forexampleforREDchannelselect:REDB=0,GREENB=1,BLUEB=1
2.InputRange(forexample:REDchannel)
-Ifyou want to using thesingle-endedinputand REDchannel is selected,
you should useheinputrange asbelow.
R_INP:0.5V~4.5V
R_INN :2.5V
-Ifyou want to using thedifferential input,you should usetheinputrange asbelow.
R_INP:1.5V~3.5V,
R_INN :1.5V~3.5V.
AINR:R_INP−R_INN
-Ifyou want tochanging inputrange(AINRspan),you canforce reference voltages.
AINspan=−REF~+REF
REF=REFTOP−REFBOT
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PHANTOMCELL INFORMATION
-Pinsofthe core can be assignedexternally(Packagepins)orinternally(internalports)depending
on design methods.
Theterm"External"impliesthat thepins should be assignedexternallylikepowerpins.
Theterm"External/internal"impliesthat the applicationsofthesepinsdepend on theuser.
9/11
PinNamePinUsagePinLayoutGuide
VDDA External-Maintainthelargewidth oflinesas
farasthepads.
-place theportpositionstominimize
thelength ofpowerlines.
-Do notmergethe analog powerswith
anoterpower fromotherblocks.
-Usegood powerand ground source
on board.
VSSAExternal
VBB External
VDDD External
VSSDExternal
R_INPExternal/Internal
-Do notoverlapwith digtal lines.
-Maintaintheshotestpathto pads.
R_INN External/Internal
G_INPExternal/Internal
G_INN External/Internal
B_INPExternal/Internal
B_INN External/Internal
CKINExternal/Internal-Separatefromall otheranalog signals
REFTOPExternal/Internal-Maintainthelargerwidthand the
shorterlengthasfarasthepads.
-Separatefromall otherdigital lines.
REFBOT External/Internal
STBYExternal/Internal
REDBExternal/Internal
GREENBExternal/Internal
BLUEBExternal/Internal
DO[11]External/Internal
-Separatedfromthe analog clean
signalsifpossible.
-Do notexceedthelength by 1,000um.
DO[10]External/Internal
DO[9]External/Internal
DO[8]External/Internal
DO[7]External/Internal
DO[6]External/Internal
DO[5]External/Internal
DO[4]External/Internal
DO[3]External/Internal
DO[2]External/Internal
DO[1]External/Internal
DO[0]External/Internal
bl8531h_adc
12bit10MSPSADC
REFBOT REFTOP
VSSA VBB VDDA
GREENB
R_INN
BUEB
REDB
R_INP
DO[0] DO[1] DO[2] DO[3] DO[4] DO[5] DO[6] DO[7] DO[8] DO[9]
STBY
VDDD
VBB
VSSD
CKIN
G_INN
G_INP
B_INN
B_INP
DO[10] DO[11]
VSSA VBB VDDA

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FEEDBACKREQUEST
Itshould bequitehelpful to ourADCcoredevelopment ifyou specify yoursystemrequirementson ADCinthe
following characteristic checking table and fill out the additionalquestions.
We appreciateyourinterest in ourproducts.Thank you verymuch.
CharacteristicMinTypMax UnitRemarks
Analog PowerSupplyVoltageV
DigitalPowerSupplyVoltageV
Bit Resolution Bit
Reference InputVoltageV
Analog InputVoltageVpp
Operating TemperatureºC
IntegralNon-linearityErrorLSB
DifferentialNon-linearityErrorLSB
BottomOffsetVoltageErrormV
Top OffsetVoltageErrormV
MaximumConversion RateMSPS
DynamicSupplyCurrentmA
PowerDissipation mW
Signal-to-noiseRatio dB
PipelineDelayCLK
DigitalOutputFormat
(Providedetailed description &
timing diagram)
1.Betweensingleinput-outputand differential input-outputconfigurations,which oneis suitableforyoursystemand
why?
2.Please commenton theinternal/externalpinconfigurationsyou wantourADCto have,ifyou have any reason to
prefersometypeofconfiguration.
3.Freelylist thosefunctionsyou want to beimplementedin ourADC,ifyou have any.
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HISTORY CARD
11 /11
VersionDateModifiedItemsComments
ver1.0 99.12 Originalversion published(preliminary)
ver1.1 02.4.17 Phantominformation addedand theformatchanged