SBE wanPTMC-256T3 Use and care manual

wanPTMC-256T3
High-Performance PTMC Communications Controller
Hardware Technical Reference, Rev. 0.A, August 5, 2002
Primary Text Number M8258
SBE, Inc.
SBE, Inc.SBE, Inc.
SBE, Inc.
2305 Camino Ramon #200, San Ramon, California 94583
[phone] Technical Support [phone]
Fax: [phone] FaxBack Service: [phone]
Website: http://www.sbei.com

2 wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
Copyright ©2002 by SBE, Inc. All rights reserved.
No part of this manual may be reproduced by any means without written
permission from SBE, Inc., except that the purchaser may copy necessary
portions for internal use only.
While every effort has been made to ensure the accuracy of this manual, SBE
cannot be held responsible for damage resulting from information herein. All
specifications are subject to change without notice.
SBE, Inc. and the SBE logo are trademarks of SBE, Inc.
All other trademarks and copyrights are owned by their respective companies.
About SBE, Inc. SBE, Inc., provides a broad range of intelligent communications
controllers used primarily in networking systems applications. These products
are sold worldwide through direct sales and distribution channels.
SBE is based in San Ramon, California, and can be reached at 925-355-2000
or online at http://www.sbei.com

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Contents 3
Contents
1. About This Manual ..................................................................................................................................... 7
1-1. Documentation Conventions ................................................................................................................8
1-2. Related Documents ..............................................................................................................................9
2. Introduction ..............................................................................................................................................11
2-1. Product Description and Functional Characteristics ....................................................................... 11
2-2. Unpacking Instructions ...................................................................................................................... 12
2-3. Handling Procedures .......................................................................................................................... 12
2-4. Installation .......................................................................................................................................... 13
Installing the wanPTMC-256T3 onto a host board ....................................................................... 13
2-5. Returns/Service ................................................................................................................................. 14
3. Specifications ...........................................................................................................................................15
3-1. Devices ............................................................................................................................................... 16
Conexant CN8478 communications controller ............................................................................ 16
Framer ............................................................................................................................................. 16
Line Interface Unit .......................................................................................................................... 16
T8110 time slot interchanger ........................................................................................................ 16
3-2. Compatibility ....................................................................................................................................... 16
3-3. Operating Requirements ................................................................................................................... 17
3-4. Physical Characteristics ..................................................................................................................... 18
PTMC bezel ...................................................................................................................................... 19
Part number and serial number ..................................................................................................... 19
Keying .............................................................................................................................................. 19
Power ............................................................................................................................................... 19
Switches .......................................................................................................................................... 19
3-5. Mean Time Between Failures ............................................................................................................ 19
3-6. Industry Standards Compliance ........................................................................................................ 20
3-7. Agency Compliance ............................................................................................................................ 20
3-8. Certifications ...................................................................................................................................... 20
4. Functional Interfaces ..............................................................................................................................21
4-1. PCI Bus Interface ................................................................................................................................ 21
BUSMODE pins ................................................................................................................................ 22
4-2. HDLC/SS7 Packet Processor ............................................................................................................ 23
4-3. Line Interface Unit .............................................................................................................................. 24
4-4. DS3 Framer and Multiplexer ............................................................................................................. 25
4-5. T8110 Time Slot Interchange ........................................................................................................... 25
4-6. Rear I/O Support ................................................................................................................................ 26
4-7. Connectors ......................................................................................................................................... 27
PMC connector ................................................................................................................................ 27
Pn4 user I/O connector .................................................................................................................. 29
Pn3 PTMC connector ...................................................................................................................... 30

4 Contents wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
5. Power-Up, Reset, and Initialization ........................................................................................................31
5-1. Reset Functions ................................................................................................................................. 31
5-2. Under Voltage Detection .................................................................................................................... 31
5-3. MUSYCC Initialization ......................................................................................................................... 32
EBUS configuration ......................................................................................................................... 32
6. Architecture ..............................................................................................................................................33
6-1. Data Path Architecture ...................................................................................................................... 33
6-2. Clocking and Data Timing .................................................................................................................. 34
6-3. Interrupts ............................................................................................................................................ 36
DTACK interrupt .............................................................................................................................. 38
7. Programming Information .......................................................................................................................39
7-1. Memory Map ....................................................................................................................................... 39
7-2. Serial EEPROM ................................................................................................................................... 40
7-3. DS3 Framer and Multiplexer ............................................................................................................. 44
7-4. T8110 Programming .......................................................................................................................... 44
7-5. CPLD .................................................................................................................................................... 48
Serial EEPROM control ................................................................................................................... 48
EBUS control ................................................................................................................................... 48
CPLD registers ................................................................................................................................. 48
Board ID Register (BID) .................................................................................................................. 49
Interrupt Enable Register (IER) ...................................................................................................... 49
Interrupt Pending Register (IPR) .................................................................................................... 50
LIU Transmit Control Register (LTXR) ............................................................................................ 51
LIU Receive Control Register (LRXR) ............................................................................................. 52
LED Registers .................................................................................................................................. 53
General Purpose Register (GPR) .................................................................................................... 54
8. Appendix: Design Considerations for DS3 Application .........................................................................55
8-1. Use of Receive Equalizer ................................................................................................................... 55
8-2. Line Build-Out Criteria ........................................................................................................................ 56
8-3. Use of LOSTHR ................................................................................................................................... 56
9. Appendix: RTM Design Guidelines ..........................................................................................................57

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Contents 5
Figures
2-1 Installing the wanPTMC-256T3............................................................................................................... 13
3-1 wanPTMC-256T3 functional block diagram........................................................................................... 15
3-2 wanPTMC-256T3 physical profile ........................................................................................................... 18
4-1 Serial port mapping (PORTMAP=2)......................................................................................................... 23
4-2 TEMUX block diagram.............................................................................................................................. 25
4-3 Rear I/O support ...................................................................................................................................... 26
6-1 wanPTMC-256T3 TDM data path structure ........................................................................................... 33
6-2 wanPTMC-256T3 clocking structure....................................................................................................... 34
6-3 Clock and frame phase relationship....................................................................................................... 35
6-4 wanPTMC-256T3 interrupt structure...................................................................................................... 37
7-1 Data timing between LIU and TEMUX..................................................................................................... 44
8-1 Typical DS3 application ........................................................................................................................... 55
9-1 Rear I/O receive ....................................................................................................................................... 58
9-2 Rear I/O transmit ..................................................................................................................................... 58
9-3 Routing from the CM choke to BNC........................................................................................................ 59

6 Contents wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
Tables
3-1 wanPTMC-256T3 dimensions ................................................................................................................. 18
4-1 BUSMODE support ................................................................................................................................... 22
4-2 PMC Pn1 and Pn2 connector pin assignments ..................................................................................... 27
4-3 Pn4 user I/O pin assignments ................................................................................................................ 29
4-4 Pn3 PTMC configuration 2 pin assignments.......................................................................................... 30
5-1 MUSYCC registers to set for proper connectivity with T8110............................................................... 32
5-2 Global configuration descriptor settings for EBUS access.................................................................... 32
6-1 INTB# interrupt sources .......................................................................................................................... 36
7-1 wanPTMC-256T3 memory map .............................................................................................................. 39
7-2 Instruction set for 93LC46A .................................................................................................................... 40
7-3 EEPROM byte write example ................................................................................................................... 42
7-4 EEPROM byte read example.................................................................................................................... 43
7-5 T8110 address map (as seen from host)............................................................................................... 45
7-6 T8110 register map (as seen from host) ............................................................................................... 46
7-7 CPLD registers.......................................................................................................................................... 48
7-8 BID: PCI offset address D0000............................................................................................................... 49
7-9 IER: PCI offset address D0004 ............................................................................................................... 49
7-10 IPR: PCI offset address D0008 ............................................................................................................... 50
7-11 LTXR: PCI offset address D000C ............................................................................................................ 51
7-12 LRXR: PCI offset address D0010............................................................................................................ 52
7-13 LED01: PCI offset address D0014 ......................................................................................................... 53
7-14 LED23: PCI offset address D0018 ......................................................................................................... 53
7-15 GPR: PCI offset address D000C.............................................................................................................. 54
9-1 PTMC Pn4 connector pin assignments................................................................................................... 60

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 7
1. About This Manual
This manual is the technical reference for the wanPTMC-256T3 HDLC/SS7
communications module. This manual is intended for hardware and software
engineers who are incorporating the wanPTMC-256T3 into a system.
The wanPTMC-256T3 Technical Reference includes the following:
• Introduction and background on the wanPTMC-256T3 communications
controller
• Installation instructions
• Physical characteristics and specifications of the adapter
• Programming information

8 About This Manual wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
1-1. Documentation Conventions
In this manual, the term DS3 is used interchangeably with T3. DS3 refers to a
44.736Mbps, channelized data stream consisting of 672 DS0s.
The term DS0 is used to mean either one of 24 64Kbps T1/J1 channels, or
one of 32 64Kbps E1 channels, or one of 672 T3 channels.
The term “channel” connotes “full duplex channel” unless otherwise
specified.
PTMC refers to the proposed PCI Telecom Mezzanine Card standard.
Signal names with a # after the name indicates a low active signal.
Signal names with a / in front of the signal name indicates a low active signal.
The term CPLD refers to Complex Programmable Logic Device.
WORD in terms of addressing refers to 32-bit addressing.
Registers Register bits are numbered starting with 0. Bit 0 is the
least significant and bit 7 is the most significant bit of a
byte. Unless otherwise noted, register bits that are
identified as “unused” do not affect the function of the
register, and, if read, yield no information.
Signals When referring to a signal function in text, signal names do
not indicate polarity, and the / is not used. Occasionally a
signal name may be followed by an asterisk (*), a pound
sign (#), a #
##
# after the name, or with a / in front of the signal
name. These are valid ways of indicating active low signals.
Code Code is represented in New Courier
typeface.
Throughout this manual you may find notes, cautions, and warnings that
emphasize certain portions of the material presented in the text.
Caution! Points out possible ways the product can be damaged if proper precautions
are not followed.
Warning! States potential dangers to the user if a procedure is not properly followed.
Note: Provides information that is important to the surrounding text.

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Related Documents 9
1-2. Related Documents
The following references can be used for background or additional
information about this product. References are for informational purposes
only and do not express or imply wanPTMC-256T3 product features and
functions.
• Conexant CN8478/4A/2A/1A Product Manual, document # 100660E.
• Conexant CN8478/4/2A Non-Conformance Information.
• PMC-Sierra PM8315 TEMUX Data Sheet, Issue 5: Jan. 2000.
• Exar XRT7300 E3/DS3/STS-1 Line Interface Unit Data Sheet, Rev. 1.0.7.
• Lucent Ambassador T8110 Data Sheet, Jan. 2001.
• PICMG 2.3 R1.0, PMC on CompactPCI Specification, August 7, 1998,
PICMG.
• PICMG 2.5 R1.0, CompactPCI Telephony Specification, 1997, PICMG.
• PICMG 2.15 Draft 1.0, CompactPCI Telecom Mezzanine Specification,
April 3, 2001, PICMG.
• H.110 Hardware Compatibility Specification: CT Bus, Rev. 1.0, 1997,
ECTF.
• H.100 Hardware Compatibility Specification: CT Bus, Rev. 1.0, 1997,
ECTF.
• 1386 Draft 2.4 Draft Standard for a Common Mezzanine Card Family:
CMC, January 12, 2001, IEEE.
• 1386.1 Draft 2.4, Draft Standard Physical and Environmental Layers for
PCI Mezzanine Cards: PMC, January 12, 2001, IEEE.

10 About This Manual wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002