SBE wanPTMC-256T3 Use and care manual

wanPTMC-256T3
High-Performance PTMC Communications Controller
Hardware Technical Reference, Rev. 0.A, August 5, 2002
Primary Text Number M8258
SBE, Inc.
SBE, Inc.SBE, Inc.
SBE, Inc.
2305 Camino Ramon #200, San Ramon, California 94583
[phone] Technical Support [phone]
Fax: [phone] FaxBack Service: [phone]
Website: http://www.sbei.com

2 wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
Copyright ©2002 by SBE, Inc. All rights reserved.
No part of this manual may be reproduced by any means without written
permission from SBE, Inc., except that the purchaser may copy necessary
portions for internal use only.
While every effort has been made to ensure the accuracy of this manual, SBE
cannot be held responsible for damage resulting from information herein. All
specifications are subject to change without notice.
SBE, Inc. and the SBE logo are trademarks of SBE, Inc.
All other trademarks and copyrights are owned by their respective companies.
About SBE, Inc. SBE, Inc., provides a broad range of intelligent communications
controllers used primarily in networking systems applications. These products
are sold worldwide through direct sales and distribution channels.
SBE is based in San Ramon, California, and can be reached at 925-355-2000
or online at http://www.sbei.com

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Contents 3
Contents
1. About This Manual ..................................................................................................................................... 7
1-1. Documentation Conventions ................................................................................................................8
1-2. Related Documents ..............................................................................................................................9
2. Introduction ..............................................................................................................................................11
2-1. Product Description and Functional Characteristics ....................................................................... 11
2-2. Unpacking Instructions ...................................................................................................................... 12
2-3. Handling Procedures .......................................................................................................................... 12
2-4. Installation .......................................................................................................................................... 13
Installing the wanPTMC-256T3 onto a host board ....................................................................... 13
2-5. Returns/Service ................................................................................................................................. 14
3. Specifications ...........................................................................................................................................15
3-1. Devices ............................................................................................................................................... 16
Conexant CN8478 communications controller ............................................................................ 16
Framer ............................................................................................................................................. 16
Line Interface Unit .......................................................................................................................... 16
T8110 time slot interchanger ........................................................................................................ 16
3-2. Compatibility ....................................................................................................................................... 16
3-3. Operating Requirements ................................................................................................................... 17
3-4. Physical Characteristics ..................................................................................................................... 18
PTMC bezel ...................................................................................................................................... 19
Part number and serial number ..................................................................................................... 19
Keying .............................................................................................................................................. 19
Power ............................................................................................................................................... 19
Switches .......................................................................................................................................... 19
3-5. Mean Time Between Failures ............................................................................................................ 19
3-6. Industry Standards Compliance ........................................................................................................ 20
3-7. Agency Compliance ............................................................................................................................ 20
3-8. Certifications ...................................................................................................................................... 20
4. Functional Interfaces ..............................................................................................................................21
4-1. PCI Bus Interface ................................................................................................................................ 21
BUSMODE pins ................................................................................................................................ 22
4-2. HDLC/SS7 Packet Processor ............................................................................................................ 23
4-3. Line Interface Unit .............................................................................................................................. 24
4-4. DS3 Framer and Multiplexer ............................................................................................................. 25
4-5. T8110 Time Slot Interchange ........................................................................................................... 25
4-6. Rear I/O Support ................................................................................................................................ 26
4-7. Connectors ......................................................................................................................................... 27
PMC connector ................................................................................................................................ 27
Pn4 user I/O connector .................................................................................................................. 29
Pn3 PTMC connector ...................................................................................................................... 30

4 Contents wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
5. Power-Up, Reset, and Initialization ........................................................................................................31
5-1. Reset Functions ................................................................................................................................. 31
5-2. Under Voltage Detection .................................................................................................................... 31
5-3. MUSYCC Initialization ......................................................................................................................... 32
EBUS configuration ......................................................................................................................... 32
6. Architecture ..............................................................................................................................................33
6-1. Data Path Architecture ...................................................................................................................... 33
6-2. Clocking and Data Timing .................................................................................................................. 34
6-3. Interrupts ............................................................................................................................................ 36
DTACK interrupt .............................................................................................................................. 38
7. Programming Information .......................................................................................................................39
7-1. Memory Map ....................................................................................................................................... 39
7-2. Serial EEPROM ................................................................................................................................... 40
7-3. DS3 Framer and Multiplexer ............................................................................................................. 44
7-4. T8110 Programming .......................................................................................................................... 44
7-5. CPLD .................................................................................................................................................... 48
Serial EEPROM control ................................................................................................................... 48
EBUS control ................................................................................................................................... 48
CPLD registers ................................................................................................................................. 48
Board ID Register (BID) .................................................................................................................. 49
Interrupt Enable Register (IER) ...................................................................................................... 49
Interrupt Pending Register (IPR) .................................................................................................... 50
LIU Transmit Control Register (LTXR) ............................................................................................ 51
LIU Receive Control Register (LRXR) ............................................................................................. 52
LED Registers .................................................................................................................................. 53
General Purpose Register (GPR) .................................................................................................... 54
8. Appendix: Design Considerations for DS3 Application .........................................................................55
8-1. Use of Receive Equalizer ................................................................................................................... 55
8-2. Line Build-Out Criteria ........................................................................................................................ 56
8-3. Use of LOSTHR ................................................................................................................................... 56
9. Appendix: RTM Design Guidelines ..........................................................................................................57

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Contents 5
Figures
2-1 Installing the wanPTMC-256T3............................................................................................................... 13
3-1 wanPTMC-256T3 functional block diagram........................................................................................... 15
3-2 wanPTMC-256T3 physical profile ........................................................................................................... 18
4-1 Serial port mapping (PORTMAP=2)......................................................................................................... 23
4-2 TEMUX block diagram.............................................................................................................................. 25
4-3 Rear I/O support ...................................................................................................................................... 26
6-1 wanPTMC-256T3 TDM data path structure ........................................................................................... 33
6-2 wanPTMC-256T3 clocking structure....................................................................................................... 34
6-3 Clock and frame phase relationship....................................................................................................... 35
6-4 wanPTMC-256T3 interrupt structure...................................................................................................... 37
7-1 Data timing between LIU and TEMUX..................................................................................................... 44
8-1 Typical DS3 application ........................................................................................................................... 55
9-1 Rear I/O receive ....................................................................................................................................... 58
9-2 Rear I/O transmit ..................................................................................................................................... 58
9-3 Routing from the CM choke to BNC........................................................................................................ 59

6 Contents wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
Tables
3-1 wanPTMC-256T3 dimensions ................................................................................................................. 18
4-1 BUSMODE support ................................................................................................................................... 22
4-2 PMC Pn1 and Pn2 connector pin assignments ..................................................................................... 27
4-3 Pn4 user I/O pin assignments ................................................................................................................ 29
4-4 Pn3 PTMC configuration 2 pin assignments.......................................................................................... 30
5-1 MUSYCC registers to set for proper connectivity with T8110............................................................... 32
5-2 Global configuration descriptor settings for EBUS access.................................................................... 32
6-1 INTB# interrupt sources .......................................................................................................................... 36
7-1 wanPTMC-256T3 memory map .............................................................................................................. 39
7-2 Instruction set for 93LC46A .................................................................................................................... 40
7-3 EEPROM byte write example ................................................................................................................... 42
7-4 EEPROM byte read example.................................................................................................................... 43
7-5 T8110 address map (as seen from host)............................................................................................... 45
7-6 T8110 register map (as seen from host) ............................................................................................... 46
7-7 CPLD registers.......................................................................................................................................... 48
7-8 BID: PCI offset address D0000............................................................................................................... 49
7-9 IER: PCI offset address D0004 ............................................................................................................... 49
7-10 IPR: PCI offset address D0008 ............................................................................................................... 50
7-11 LTXR: PCI offset address D000C ............................................................................................................ 51
7-12 LRXR: PCI offset address D0010............................................................................................................ 52
7-13 LED01: PCI offset address D0014 ......................................................................................................... 53
7-14 LED23: PCI offset address D0018 ......................................................................................................... 53
7-15 GPR: PCI offset address D000C.............................................................................................................. 54
9-1 PTMC Pn4 connector pin assignments................................................................................................... 60

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 7
1. About This Manual
This manual is the technical reference for the wanPTMC-256T3 HDLC/SS7
communications module. This manual is intended for hardware and software
engineers who are incorporating the wanPTMC-256T3 into a system.
The wanPTMC-256T3 Technical Reference includes the following:
• Introduction and background on the wanPTMC-256T3 communications
controller
• Installation instructions
• Physical characteristics and specifications of the adapter
• Programming information

8 About This Manual wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
1-1. Documentation Conventions
In this manual, the term DS3 is used interchangeably with T3. DS3 refers to a
44.736Mbps, channelized data stream consisting of 672 DS0s.
The term DS0 is used to mean either one of 24 64Kbps T1/J1 channels, or
one of 32 64Kbps E1 channels, or one of 672 T3 channels.
The term “channel” connotes “full duplex channel” unless otherwise
specified.
PTMC refers to the proposed PCI Telecom Mezzanine Card standard.
Signal names with a # after the name indicates a low active signal.
Signal names with a / in front of the signal name indicates a low active signal.
The term CPLD refers to Complex Programmable Logic Device.
WORD in terms of addressing refers to 32-bit addressing.
Registers Register bits are numbered starting with 0. Bit 0 is the
least significant and bit 7 is the most significant bit of a
byte. Unless otherwise noted, register bits that are
identified as “unused” do not affect the function of the
register, and, if read, yield no information.
Signals When referring to a signal function in text, signal names do
not indicate polarity, and the / is not used. Occasionally a
signal name may be followed by an asterisk (*), a pound
sign (#), a #
##
# after the name, or with a / in front of the signal
name. These are valid ways of indicating active low signals.
Code Code is represented in New Courier
typeface.
Throughout this manual you may find notes, cautions, and warnings that
emphasize certain portions of the material presented in the text.
Caution! Points out possible ways the product can be damaged if proper precautions
are not followed.
Warning! States potential dangers to the user if a procedure is not properly followed.
Note: Provides information that is important to the surrounding text.

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Related Documents 9
1-2. Related Documents
The following references can be used for background or additional
information about this product. References are for informational purposes
only and do not express or imply wanPTMC-256T3 product features and
functions.
• Conexant CN8478/4A/2A/1A Product Manual, document # 100660E.
• Conexant CN8478/4/2A Non-Conformance Information.
• PMC-Sierra PM8315 TEMUX Data Sheet, Issue 5: Jan. 2000.
• Exar XRT7300 E3/DS3/STS-1 Line Interface Unit Data Sheet, Rev. 1.0.7.
• Lucent Ambassador T8110 Data Sheet, Jan. 2001.
• PICMG 2.3 R1.0, PMC on CompactPCI Specification, August 7, 1998,
PICMG.
• PICMG 2.5 R1.0, CompactPCI Telephony Specification, 1997, PICMG.
• PICMG 2.15 Draft 1.0, CompactPCI Telecom Mezzanine Specification,
April 3, 2001, PICMG.
• H.110 Hardware Compatibility Specification: CT Bus, Rev. 1.0, 1997,
ECTF.
• H.100 Hardware Compatibility Specification: CT Bus, Rev. 1.0, 1997,
ECTF.
• 1386 Draft 2.4 Draft Standard for a Common Mezzanine Card Family:
CMC, January 12, 2001, IEEE.
• 1386.1 Draft 2.4, Draft Standard Physical and Environmental Layers for
PCI Mezzanine Cards: PMC, January 12, 2001, IEEE.

10 About This Manual wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Product Description and Functional Characteristics 11
2. Introduction
2-1. Product Description and Functional Characteristics
The wanPTMC-256T3 is a single channel DS3 PCI Telecom Mezzanine Module
(PTMC) for use on PTMC “Configuration #2” carrier platforms such as SBE's
HW400c/M. It combines a fully channelized DS3 interface (down to DS0s), a
256 channel “layer one” protocol processor, and a full matrix DS0 level switch
in a single PTMC slot. The wanPTMC-256T3 supports DS3, DS2, and DS1
level framing including C-bit, CAS, and CCS signaling channels. Protocol
processing capabilities include HDLC and SS7 MTP1 support. A combined
time slot interchange and CT-Bus time slot assigner allows switching of data
streams between the CT-Bus, protocol processor, and DS3 interfaces without
consuming host board resources.
The wanPTMC-256T3 incorporates a fully channelized T3 port with an HDLC/
SS7/transparent controller and a PTMC interface.
This product uses the Conexant CN8478 MUlti-channel SYnchronous
Communications Controller (MUSYCC) as the PCI interface and HDLC
controller. Its function is to provide the PCI Bus interface, control the local
Expansion Bus (EBUS) for board configuration and control, and
frame/deframe HDLC/SS7/transparent data to its own TDM ports.
The PCI interface conforms to the PCI 2.1 specification. It transfers 32 bits of
data at up to 33MHz. 3.3V and 5V PCI bus signaling is supported. DMA
transfers to and from host memory are also supported.
An H.110 controller (Agere Systems’ T8110) is used to interface to the data
paths to the PTMC CT-Bus connections on Pn3. This controller also provides a
time slot interchange (TSI) function.
The PMC Sierra TEMUX (PM8315) is used to translate data between the local
TDM lines and the DS3 LIU. This includes 28 T1/E1 framers.
Exar's XRT7300 Line Interface Unit (LIU) provides signal conditioning and
loopback capability.
Figure 3-1 shows the block diagram of wanPTMC-256T3.

12 Introduction wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
2-2. Unpacking Instructions
1. If the carton is damaged when you receive it, request that the carrier's
agent be present when you unpack and inspect the equipment.
2. After unpacking, verify that all items listed in the packing list are
present.
3. Inspect the equipment for shipping damage.
4. Save all packing material for storage or return shipment of the
equipment.
5. For repairs or replacement of equipment damaged during shipment,
contact SBE, Inc. to obtain a Return Materials Authorization (RMA)
number and further shipping instructions.
2-3. Handling Procedures
The wanPTMC-256T3 adapter uses CMOS components that can be easily
damaged by static electrical discharge. To avoid damage, familiarize yourself
with electrostatic discharge (ESD) procedures, which include the following
precautions:
Caution! The adapter should be handled only by trained service personnel at an
approved ESD workstation.
• Refer to ANSI/IPC-A-610 developed by the Institute for Interconnecting
and Packaging Electronic Circuits (IPC).
Caution! DO NOT insert the adapter into or remove it from the adapter cage while
power is applied.
• Keep the adapter in a sealed conductive plastic bag while in transit.
• When installing the adapter in the field, ground yourself to the computer
before removing the adapter from the sealed conductive plastic bag (the
power plug must be installed on the computer for this to be effective).
• Any equipment used to work on the adapter must be grounded. Any
person handling the adapter must be grounded.
• Check alignment and polarization of cables and connectors before
applying power.
•Donot
Do notDo not
Do not apply external voltages to any devices on the adapter with power
removed from the adapter.
•Donot
Do notDo not
Do not attempt to straighten any part soldered to the adapter, as pin
breakage or internal damage could occur.

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Installation 13
2-4. Installation
Installing the wanPTMC-256T3 onto
a host board
The primary component sides of the wanPTMC-256T3 and the host board
face each other when connected. See Figure 2-1.
Caution! Be sure to follow safe ESD procedures when handling electronic hardware.
1. Remove the wanPTMC-256T3 from the protective bag.
2. Press the wanPTMC-256T3 bezel into the cutout in the PTMC carrier I/O
panel. The gasket around the wanPTMC-256T3 bezel makes a tight fit to
ensure an electromagnetic seal. Check that the bezel and gasket are
pressed firmly into the carrier I/O.
3. Press the wanPTMC-256T3 down onto the carrier so PN1–PN4 plug into
JN1–JN4 on the PTMC carrier.
4. Install four screws to secure the wanPTMC-256T3 in place.
Figure 2-1 Installing the wanPTMC-256T3
Note: Check the alignment and polarization of connectors before applying any
power to the module. Failure to install the module correctly can cause
damage to the board.
PTMC carrier card
PTMC carrier card
two screws
wanPTMC-256T3
wanPTMC-256T3
two screws
two screws two screws

14 Introduction wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
2-5. Returns/Service
Before returning any equipment for service you must obtain a Return Material
Authorization (RMA) number from SBE:
TEL: [phone] (Toll free, USA)
TEL: [phone] (Outside of USA)
FAX: [phone]
Ship all returns to SBE’s USA service center:
SBE, Inc.
2305 Camino Ramon, Suite 200
San Ramon, CA 94583
SBE’s customer service department can be reached at 800-444-0990.

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Returns/Service 15
3. Specifications
This chapter details the physical characteristics and specifications for the
wanPTMC-256T3 communications controller. Figure 3-1 is a block diagram of
the wanPTMC-256T3 functionality.
Figure 3-1 wanPTMC-256T3 functional block diagram
CT bus
rear I/O support
magnetics
Pn4
Pn3
Pn1
&
Pn2
cPLD
XRT7300 LIU
serial
EEPROM
dvr
PM8315 TEMUX
host PCI bus 32 bit/33MHz
MUSYCC CN8478A
T8110
local Ebus
TDMsTDMs
Tx bi-color
LED

16 Specifications wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
3-1. Devices
Conexant CN8478 communications
controller
The wanPTMC-256T3 uses a Conexant CN8478 communications controller as
the HDLC processing engine.
• The CN8478 Multichannel Synchronous Communications Controller
(MUSYCC) is an advanced, multichannel, synchronous communications
controller that formats and deformats 256 HDLC channels in a single
CMOS IC.
• The MUSYCC provides HDLC channels for internetworking applications
such as Frame Relay, X.25, Signaling System 7 (SS7), ISDN D-channel
signaling, and LAN/WAN data transport.
• Under minimal host supervision, the MUSYCC manages a linked list of
channel data buffers in host memory by performing direct memory
access (DMA) for the 256 channels, Tx and Rx.
The MUSYCC interfaces with two serial data streams, and then transfers data
across the peripheral component interface (PCI) bus to system memory at a
rate of 132MBps. Logical channels can be mapped as any combination of
DS0 time slots to support ISDN hyperchannels (Nx64Kbps) or as any number
of bits in a DS0 for subchanneling applications (Nx8Kbps).
Framer The wanPTMC-256T3 uses a PMC-Sierra TEMUX (PM8315) as the Framer. It
has the following characteristics:
• Integrates a DS3 framer, an M13 multiplexer, and 28 T1 (or 21 E1
framers) into a 324-ball PBGA package.
• Requires 3.3V for I/O and all pins are 5V tolerant.
Line Interface Unit The wanPTMC-256T3 uses an EXAR XRT73L00AIV for the Line Interface Unit
(LIU). This device is packaged in a 44 pin TQFP package and operates at 3.3V.
T8110 time slot interchanger The Agere Systems’ T8110 implements a timeslot switching matrix to enable
the routing of data between the DS3 port, CT-Bus, and packet processor. The
T8110 is a 272-ball PBGA package and requires 3.3V for its operation. The
T8110's microprocessor interface is configured for 16-bit operation.
3-2. Compatibility
The wanPTMC-256T3 is compatible with systems with a carrier card or
motherboard with one or more configuration #2 PTMC slots.

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Operating Requirements 17
3-3. Operating Requirements
The wanPTMC-256T3 is designed to function within these environmental
parameters:
The PCI interface conforms to the PCI 2.1 specification. It will transfer 32 bits
of data at up to 33MHz. Both 3.3V and 5V PCI bus signaling are supported.
The wanPTMC-256T3 requires both 5V and 3.3V power.
Caution! Bring the wanPTMC-256T3 communications controller to operating
temperature in a noncondensing environment. The rate of change in board
temperature should not exceed 2 °C (35.6 °F) per minute.
Storage temperature: −40 to 85 °C (−40 to 176 °F)
Operating temperature: −5 to 55 °C (23 to 136 °F) ambient temperature
with power applied
Relative humidity: 10% to 85% noncondensing
Storage humidity: 5% to 95% noncondensing
Power requirements: 7.5 watts maximum
Voltages: 5V ±10% and 3.3V ±10%

18 Specifications wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
3-4. Physical Characteristics
Figure 3-2 shows the physical profile of the wanPTMC-256T3 adapter.
Table 3-1 lists the dimensions.
Figure 3-2 wanPTMC-256T3 physical profile
Agere
T8110
MUSYCC
CN8478A
PMC
TEMUX
Altera Max
PMC-Pn1 PMC-Pn2
PMC-Pn3 PMC-Pn4
Table 3-1 wanPTMC-256T3 dimensions
Depth: 5.866 inches
Width: 2.913 inches
Primary side maximum component height;
I/O area:
0.393 inches
Primary side maximum component height;
component area:
0.185 inches
Secondary side maximum component height: 0.078 inches
Board thickness: 0.062 inches

wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Mean Time Between Failures 19
PTMC bezel The PTMC bezel has two BNC connectors and one stacked four-high bi-color
LED.
Part number and serial number All boards are marked with the manufacturing part number and assembly
revision. This is marked in ink directly on the PCB.
All boards are serialized physically by applying a serial number label directly to
the secondary side of the PCB. A unique, electronically accessible serial
number is also programmed into non-volatile memory during the
manufacturing process.
Keying The wanPTMC-256T3 can be operated in a 5V or 3.3V signaling environment.
The signaling environment is determined by the voltage on the PCI VIO pins
and is host-specific.
Power Power is supplied to the wanPTMC-256T3 by the carrier board. Current is
drawn from the 5V and 3.3V power pins. The tolerance on the 5V and 3.3V
supply is ±10% in accordance with the PCI Local Bus Specification.
Switches wanPTMC-256T3 contains no shorting jumpers or switches that are required
for normal operation.
3-5. Mean Time Between Failures
pending
Tx
Rx
D
C
B
A

20 Specifications wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
3-6. Industry Standards Compliance
The wanPTMC-256T3 complies with the following industry standard
specifications:
• PCI Local Bus Specification Revision 2.1.
3-7. Agency Compliance
The wanPTMC-256T3 is designed to comply with the following standards or
requirements:
•BABT
•NEBS
•VCCI
3-8. Certifications
pending