SBS Technologies P-Octal Series User manual

Artisan Technology Group is your source for quality
new and certied-used/pre-owned equipment
• FAST SHIPPING AND
DELIVERY
• TENS OF THOUSANDS OF
IN-STOCK ITEMS
• EQUIPMENT DEMOS
• HUNDREDS OF
MANUFACTURERS
SUPPORTED
• LEASING/MONTHLY
RENTALS
• ITAR CERTIFIED
SECURE ASSET SOLUTIONS
SERVICE CENTER REPAIRS
Experienced engineers and technicians on staff
at our full-service, in-house repair center
WE BUY USED EQUIPMENT
Sell your excess, underutilized, and idle used equipment
We also offer credit for buy-backs and trade-ins
www.artisantg.com/WeBuyEquipment
REMOTE INSPECTION
Remotely inspect equipment before purchasing with
our interactive website at www.instraview.com
LOOKING FOR MORE INFORMATION?
Visit us on the web at www.artisantg.com for more
information on price quotations, drivers, technical
specications, manuals, and documentation
Contact us: (888) 88-SOURCE | [e-mail] | www.artisantg.com
SM
View
Instra

Px-Octal
PC•MIP Modules with
Eight Serial Channels
User Manual
© SBS Technologies, Inc.
Subject to change without notice.
Part No. 89004225 Rev. 3.0 20050114
Hardware Revision: P1: B P2: B
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

Px-Octal
PC•MIP Modules with
Eight Serial Channels
SBS Technologies, Inc.
1284 Corporate Center Drive
St. Paul, MN 55121-1245
Tel [phone]
FAX [phone]
Email: [email protected]
www.sbs.com
©2000, 2002, 2005 SBS Technologies, Inc.
IndustryPack is a registered trademark of SBS
Technologies, Inc. QuickPack, SDpacK and Unilin
are trademarks of SBS Technologies, Inc. PC•MIP
is a trademark of SBS Technologies, Inc. and MEN
Micro Inc.
SBS Technologies, Inc. acknowledges the
trademarks of other organizations for their
respective products mentioned in this document.
A
ll rights are reserved: No one is permitted to
reproduce or duplicate, in any form, the whole or
part of this document without the express consent of
SBS Technologies, Inc. This document is meant
solely for the purpose for which it was delivered.
SBS Technologies reserves the right to make any
changes in the devices or device specifications
contained herein at any time and without notice.
Customers are advised to verify all information
contained in this document.
The electronic equipment described herein
generates, uses, and may radiate radio frequency
energy, which can cause radio interference. SBS
Technologies assumes no liability for any damages
caused by such interference.
SBS Technologies’ products are not authorized for
use as critical components in medical applications,
such as life support equipment, without the express
consent of the General Manager of SBS
Technologies, Inc. Commercial Group.
This product has been designed to operate with
IndustryPack, PC•MIP or PMC modules or carriers,
and compatible user-provided equipment.
Connection of incompatible hardware is likely to
cause serious damage. SBS Technologies assumes
no liability for any damages caused by such
incompatibility.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

Table of Contents
PRODUCT DESCRIPTION________________________________________________ 1
BLOCK DIAGRAMS_____________________________________________________ 2
QUICK START _________________________________________________________ 5
UART RESET_________________________________________________________ 5
CHANNEL 1CONFIGURATION ____________________________________________ 6
CHANNEL 8CONFIGURATION ____________________________________________ 6
TRANSMITTING AND READING ___________________________________________ 6
CHANNEL NUMBERING _________________________________________________ 7
PCI CONFIGURATION REGISTERS ________________________________________ 8
MEMORY SPACE______________________________________________________ 10
ALTERA-IMPLEMENTED REGISTERS ______________________________________ 11
CR Control Register ________________________________________________ 11
FRR14 FIFO Ready Channels 1-4 _____________________________________ 12
FRR58 FIFO Ready Channels 5-8 _____________________________________ 14
GISR Global Interrupt Status Register __________________________________ 16
UART-IMPLEMENTED REGISTERS _______________________________________ 17
INTERRUPTS _________________________________________________________ 18
INTERRUPT ARCHITECTURE ____________________________________________ 18
ENABLING INTERRUPTS _______________________________________________ 18
SERVICING INTERRUPTS _______________________________________________ 18
DISABLING INTERRUPTS _______________________________________________ 18
ADVANCED INTERRUPT FEATURES ______________________________________ 18
USER OPTIONS_______________________________________________________ 19
USER-SUPPLIED OSCILLATOR __________________________________________ 19
USER-SWITCHABLE TERMINATION RESISTORS _____________________________ 19
CONNECTOR PIN ASSIGNMENTS________________________________________ 20
J1_________________________________________________________________ 20
J2_________________________________________________________________ 21
J3_________________________________________________________________ 22
J4_________________________________________________________________ 25
P1-OCTAL-232 SPECIFICATIONS ________________________________________ 27
P1-OCTAL-422 SPECIFICATIONS ________________________________________ 28
P1-OCTAL-TTL SPECIFICATIONS ________________________________________ 29
P2-OCTAL-232 SPECIFICATIONS ________________________________________ 30
P2-OCTAL-422 SPECIFICATIONS ________________________________________ 31
REPAIR _____________________________________________________________ 32
SERVICE POLICY _____________________________________________________ 32
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

List of Figures
FIGURE 1. BLOCK DIAGRAM -VERSION 232 ___________________________________ 2
FIGURE 2. BLOCK DIAGRAM -VERSION 422 ___________________________________ 3
FIGURE 3. BLOCK DIAGRAM -TTL VERSION___________________________________ 4
FIGURE 4. QUICK START PIN CONNECTIONS TO TRANSMIT CHARACTERS -232
VERSIONS _____________________________________________________________ 5
FIGURE 5. QUICK START PIN CONNECTIONS TO TRANSMIT CHARACTERS -422
VERSIONS _____________________________________________________________ 5
FIGURE 6. QUICK START PIN CONNECTIONS TO TRANSMIT CHARACTERS -TTL
VERSION_______________________________________________________________ 5
FIGURE 7. CHANNEL NUMBERING___________________________________________ 7
FIGURE 8. PCI CONFIGURATION REGISTERS __________________________________ 8
FIGURE 9. READ-ONLY PCI CONFIGURATION REGISTER VALUES –RS-232 VERSIONS _9
FIGURE 10. READ-ONLY PCI CONFIGURATION REGISTER VALUES –RS-422 VERSIONS 9
FIGURE 11. READ-ONLY PCI CONFIGURATION REGISTER VALUES -TTL VERSION ____ 9
FIGURE 12. MEMORY ADDRESS MAP _______________________________________ 10
FIGURE 13. UART REGISTER MAP _________________________________________ 17
FIGURE 14. USER-SUPPLIED OSCILLATOR DIMENSIONS ________________________ 19
FIGURE 15. CONNECTOR J1 PIN ASSIGNMENTS ______________________________ 20
FIGURE 16. CONNECTOR J2 PIN ASSIGNMENTS ______________________________ 21
FIGURE 17. THE P1-OCTAL-232 FLEXIBLE I/O CONNECTOR J3 PIN ASSIGNMENTS ___ 22
FIGURE 18. THE P1-OCTAL-422 FLEXIBLE I/O CONNECTOR J3 PIN ASSIGNMENTS ___ 23
FIGURE 19. THE P1-OCTAL-TTL FLEXIBLE I/O CONNECTOR J3 PIN ASSIGNMENTS ___ 24
FIGURE 20. THE P2-OCTAL-232 FRONT PANEL CONNECTOR J4 PIN ASSIGNMENTS __ 25
FIGURE 21. THE P2-OCTAL-422 FRONT PANEL CONNECTOR J4 PIN ASSIGNMENTS __ 26
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

1
Product Description
The Px-Octal product family provides eight channels of EIA-232, EIA-422, or TTL-compatible
(3.3V) asynchronous serial communication on a Type I (flexible I/O) or Type II (front panel
I/O) PC•MIP module. The high channel density makes the Px-Octal module ideal for
communications applications that require a large number of serial channels in a small space.
Five versions of the Px-Octal family are documented here:
•P1-Octal-TTL is a Type I (flexible I/O) module with TTL-compatible (3.3V) driver support.
•P1-Octal-232 is a Type I (flexible I/O) module with EIA-232 driver support.
•P1-Octal-422 is a Type I (flexible I/O) module with EIA-422 driver support.
•P2-Octal-232 is a Type II (front panel I/O) module with EIA-232 driver support.
•P2-Octal-422 is a Type II (front panel I/O) module with EIA-422 driver support.
In addition to the common core design features of these modules, this manual documents the
differences in serial drivers and I/O routing for these products.
The Px-Octal family features two quad UART SCCs with 128 bytes of transmit FIFO and 128
bytes of receive FIFO per channel. Data rates of up to 460.8 kbaud are supported for RS-422
communications, and up to 115.2 kbaud for the RS-232 and TTL (3.3V) communications.
Serial signals for each channel are routed to the flexible I/O connector for rear-panel access.
For the RS-232 and RS-422 options, all signals are ESD-protected up to ±15 kV, according
to IEC 1000.4.2 specifications.
Baud rate is software-configurable from 50 bps to the maximum rate via the on-board
programmable baud rate generator. Interrupts are fully supported per channel with four
programmable transmit/receive FIFO interrupt trigger levels. In addition, programmable bit
length, parity, and stop bits are provided to support all asynchronous protocols.
A VxWorks 5.3 driver and a Windows NT 4.0 are available. The Px-Octal modules are
compatible with the PC•MIP draft specification (ANSI/VITA-29).
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

2
Block Diagrams
Figure 1. Block Diagram - Version 232
PCI BUS ALTERA EPF6016
QUAD
UART
QUAD
UART
DATA
ADDRESS
CONTROL
7.3728
MHz
CLOCK
OPTIONAL
CUSTOM
CLOCK
CLOCK
DATA
ADDRESS
CONTROL
CLOCK
CONTROL
REGISTER
FIFO READY
REGISTER
GLOBAL
INTERUPT
VECTOR
PCI
TARGET
MEGA
CORE
CONTROL
LOGIC
TXD
RXD
RTS
CTS
TXD
RXD
RTS
CTS
CHAN 1
CHAN 8
RS232
TRANSCEIVERS
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

3
Figure 2. Block Diagram - Version 422
PCI BUS ALTERA EPF6016
QUAD
UART
QUAD
UART
DATA
ADDRESS
CONTROL
7.3728
MHz
CLOCK
OPTIONAL
CUSTOM
CLOCK
CLOCK
DATA
ADDRESS
CONTROL
CLOCK
CONTROL
REGISTER
FIFO READY
REGISTER
GLOBAL
INTERUPT
STATUS
PCI
TARGET
MEGA
CORE
CONTROL
LOGIC
TXD
RXD
TXD
RXD
CHAN 1
CHAN 8
RS422
TRANCEIVERS
Switchable
Termination
Resistors
Switchable
Termination
Resistors
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

4
PCI BUS ALTERA EPF6016
QUAD
UART
QUAD
UART
DATA
ADDRESS
CONTROL
7.3728
MHz
CLOCK
OPTIONAL
CUSTOM
CLOCK
CLOCK
DATA
ADDRESS
CONTROL
CLOCK
CONTROL
REGISTER
FIFO READY
REGISTER
GLOBAL
INTERUPT
VECTOR
PCI
TARGET
MEGA
CORE
CONTROL
LOGIC
TXD
RXD
RTS
CTS
TXD
RXD
RTS
CTS
CHAN 1
CHAN 8
DIRECT TTL
CONNECTION
Figure 3. Block Diagram - TTL Version
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

5
Quick Start
Each channel is implemented by a unique set of UART registers but also shares the
global control, FIFO ready, and interrupt status registers implemented in the Altera
device.
This section illustrates how to:
1. Configure Channel 1 and Channel 8 for 9600 baud rate, 8 data bits, 1 stop bit,
and no parity
2. Transmit two bytes from Channel 1
3. Read the two transmitted bytes from Channel 8
All addresses indicate offset from BAR0. To transmit characters from Channel 1 to
Channel 8, Channel 1 TxD pin should be connected to Channel 8 RxD pin as illustrated
in the figure below:
Connect From Connect To
Board Pin Signal Pin Signal
P1-Octal-232 2 49
P2-Octal-232 2 TxD 1 34 RxD 8
Figure 4. Quick Start Pin Connections to Transmit Characters - 232 Versions
Connect From Connect To
Board Pin Signal Pin Signal
2 TxD- 1 51 RxD- 8
P1-Octal-422 3 TxD+ 1 52 RxD+ 8
2 TxD- 1 35 RxD- 8
P2-Octal-422 3 TxD+ 1 36 RxD+ 8
Figure 5. Quick Start Pin Connections to Transmit Characters - 422 Versions
Connect From Connect To
Board Pin Signal Pin Signal
P1-Octal-TTL 2 TxD 1 49 RxD 8
Figure 6. Quick Start Pin Connections to Transmit Characters - TTL Version
On the P1-Octal versions, the connection is made at the backplane or on the carrier
board at a user I/O connector. Be careful to join the correct pins.
UART Reset
•Write 0x10 to offset 0x0500
Write 0x00 to offset 0x0500
(This step resets both UARTs. It is recommended to delay 500ms between the two
writes.)
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

6
Channel 1 Configuration
1. Write 0x80 to offset 0x0030
(Enables access to Special Register.)
2. Write 0x0C to offset 0x0000
Write 0x00 to offset 0x0010
(Sets baud rate to 9600.)
3. Write 0x03 to offset 0x0030
(Exits Special Register mode and sets 8 data bits, 1 stop bit, no parity.)
4. Write 0x00 to offset 0x0010
(Disables all interrupts.)
5. Write 0x01 to offset 0x0020
(Enables FIFO operation.)
Channel 8 Configuration
1. Write 0x80 to offset 0x1330
(Enables access to Special Register.)
2. Write 0x0C to offset 0x1300
Write 0x00 to offset 0x1310
(Sets baud rate to 9600.)
3. Write 0x03 to offset 0x1330
(Exits Special Register mode and sets 8 data bits, 1 stop bit, no parity.)
4. Write 0x00 to offset 0x1310
(Disables all interrupts.)
5. Write 0x01 to offset 0x1320
(Enables FIFO operation.)
Transmitting and Reading
1. Write 0x11 to offset 0x0000
Write 0x22 to offset 0x0000
(Writes two characters to THR register, which transmits them out of Channel 1.)
2. Read from 0x1300
(Reads from Channel 8 RHR register. Result should be 0x11.)
3. Read from 0x1300
(Reads from Channel 8 RHR register. Result should be 0x22.)
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

7
Channel Numbering
The Px-Octal uses two quad UARTs (UART 0 and UART 1). Please refer to the Exar
ST16C854 Data Sheet for a complete definition of all the UART registers. UART
channels are labeled as follows:
Channel Number UART Number UART Channel
1 A
2 B
3 C
4
0
D
5 A
6 B
7 C
8
1
D
Figure 7. Channel Numbering
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

8
PCI Configuration Registers
PCI Configuration Registers can be accessed only through PCI Configuration Read and
Configuration Write cycles. Px-Octal PCI configuration space follows PCI Local Bus
Specification, Revision 2.1, which defines sixteen 32-bit words of block configuration
space. The registers within this range identify the device, control PCI bus functions, and
indicate PCI bus status. The table below summarizes PCI configuration registers
supported by the Px-Octal.
Address
Offset
(Hex)
Range
Reserved
(Hex)
Read/Write Mnemonic Register Name
00 00-01 Read ven_id Vendor ID
02 02-03 Read dev_id Device ID
04 04-05 Read/Write Comd Command
06 06-07 Read/Write status Status
08 08-08 Read rev_id Revision ID
09 09-0B Read class Class Code
0E 0E-0E Read header Header type
10 10-13 Read/Write bar0 Base address register zero
2C 2C-2D Read sub_ven_id Subsystem Vendor ID
2E 2E-2F Read sub_id Subsystem ID
3C 3C-3C Read/Write int_ln Interrupt line
3D 3D-3D Read int_pin Interrupt pin
Note: Unused registers ignore write operations and produce a zero when read.
Figure 8. PCI Configuration Registers
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

9
The following table specifies read-only PCI Configuration register values. For a detailed
description of these registers, please refer to PCI Local Bus Specification, Revision 2.1.
Register Value
Vendor ID 0x124b
Device ID 0x0001
Revision ID 0x0001
Class Code 0x0007
Header Type 0x0000
Subsystem Vendor ID 0x124b
Subsystem ID 0x0308
Figure 9. Read-Only PCI Configuration Register Values – RS-232 Versions
Register Value
Vendor ID 0x124b
Device ID 0x0001
Revision ID 0x0001
Class Code 0x0007
Header Type 0x0000
Subsystem Vendor ID 0x124b
Subsystem ID 0x0408
Figure 10. Read-Only PCI Configuration Register Values – RS-422 Versions
Register Value
Vendor ID 0x124b
Device ID 0x0001
Revision ID 0x0001
Class Code 0x0007
Header Type 0x0000
Subsystem Vendor ID 0x124b
Subsystem ID 0x0308
Figure 11. Read-Only PCI Configuration Register Values - TTL Version
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

10
Memory Space
The host system accesses the Px-Octal via a 33 MHz, 32-bit PC•MIP interface that is
PCI Specification 2.1 compliant.
The board contains two sets of registers. One set is implemented in the Altera device and
consists of the Control Register (CR), FIFO Ready Registers (FRR), and the Global
Interrupt Status Register (GISR). The second set of registers is built into the UART and
provides access to UART’s status and control registers. All are accessible through the
PCI BAR0.
The PCI BAR0 is mapped in PCI Memory Space and consumes 8Kbytes of space. The
registers are 8 bits wide and 8-, 16-, or 32-bit accessible.
The following table lists the base address offset for all registers accessible from the
memory space.
Name Description Size
(bytes) Access Type Address Offset
CB1 Channel 1 Base 0x80 Read/Write 0x0000
CB2 Channel 2 Base 0x80 Read/Write 0x0100
CB3 Channel 3 Base 0x80 Read/Write 0x0200
CB4 Channel 4 Base 0x80 Read/Write 0x0300
CR Control Register Channels 1-8 0x01 Read/Write 0x0500
FRR14 FIFO Ready Register Channels 1-4 0x01 Read 0x0600
GISR Global Interrupt Status Register 0x01 Read 0x0700
CB5 Channel 5 Base 0x80 Read/Write 0x1000
CB6 Channel 6 Base 0x80 Read/Write 0x1100
CB7 Channel 7 Base 0x80 Read/Write 0x1200
CB8 Channel 8 Base 0x80 Read/Write 0x1300
Reserved --- --- 0x1500
FRR58 FIFO Ready Register Channels 5-8 0x01 Read 0x1600
Reserved --- --- 0x1700
Figure 12. Memory Address Map
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

11
Altera-Implemented Registers
Registers implemented in the Altera device consist of the Control Register (CR), FIFO
Ready Registers (FRR), and the Global Interrupt Status Register (GISR).
CR Control Register
7 6 5 4 3 2 1 0 Bit
OSC1_PRSNT 0 0 UART_RESET OSCSEL INTENABLE CLKSEL_1 CLKSEL_0 Read
X X X UART_RESET OSCSEL INTENABLE CLKSEL_1 CLKSEL_0 Write
OSC1_PRSNT 0 0 0 0 0 0 0 Reset
The Control Register controls clock and oscillator selection, enables interrupts, and
indicates installation status of a user-supplied oscillator.
7 OSC1_PRSNT Oscillator 1 Present R
This bit indicates whether a user-supplied oscillator (OSC1) is installed. Logic one
indicates that OSC1 is installed. Logic zero indicates that OSC1 is not installed.
6..5 Reserved R
These bits are reserved for future use. They are read as zeros and are ignored on writes.
Resets to zero.
4 UART_RESET UART Reset R/W
Writing a one to this bit places both UARTs in the reset state. Writing a zero discontinues
the reset state for both UARTs. Resets to zero.
3 OSCSEL Oscillator Select R/W
This bit selects one of two oscillators. A zero value enables Oscillator 2 and a one value
enables Oscillator 1. Resets to zero.
2 INTENABLE Interrupt Enable R/W
When set to one, this bit enables interrupts. When set to zero, this bit disables interrupts.
(Note: interrupts can be further controlled through the IER.) Resets to zero.
1 CLKSEL_1 Clock Select 1 R/W
This bit controls the CLKSEL pin on the UART 1 (Channels 5-8). A one value selects the
1x clock. A zero value selects the 4x clock. Resets to zero.
0 CLKSEL_0 Clock Select 0 R/W
This bit controls the CLKSEL pin on the UART 0 (Channels 1-4). A one value selects the
1x clock. A zero value selects the 4x clock. Resets to zero.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

12
FRR14 FIFO Ready Channels 1-4
7 6 5 4 3 2 1 0 Bit
C4_RXRDY C3_RXRDY C2_RXRDY C1_RXRDY C4_TXRDY C3_TXRDY C2_TXRDY C1_TXRDY Read
X X X X X X X X Write
1 1 1 1 0 0 0 0 Reset
FIFO Ready Channels 1-4 reflect the status of Transmit FIFO Channels 1-4 and Receive
FIFO Channels 1-4.
7 C4_RXRDY Channel 4 RXRDY R
This bit reflects status of the RXRDY pin on Channel 4 of the UART, which in turn
indicates status of the Channel 4 Receive FIFO. A zero indicates that the FIFO has either
reached the programmed trigger level or a time-out has occurred. A one indicates that
the FIFO is below the programmed trigger level. Resets to one.
6 C3_RXRDY Channel 3 RXRDY R
This bit reflects status of the RXRDY pin on Channel 3 of the UART, which in turn
indicates status of the Channel 3 Receive FIFO. A zero indicates that the FIFO has either
reached the programmed trigger level or a time-out has occurred. A one indicates that
the FIFO is below the programmed trigger level. Resets to one.
5 C2_RXRDY Channel 2 RXRDY R
This bit reflects status of the RXRDY pin on Channel 2 of the UART, which in turn
indicates status of the Channel 2 Receive FIFO. A zero indicates that the FIFO has either
reached the programmed trigger level or a time-out has occurred. A one indicates that
the FIFO is below the programmed trigger level. Resets to zero.
4 C1_RXRDY Channel 1 RXRDY R
This bit reflects status of the RXRDY pin on Channel 1 of the UART, which in turn
indicates status of the Channel 1 Receive FIFO. A zero indicates that the FIFO has either
reached the programmed trigger level or a time-out has occurred. A one indicates that
the FIFO is below the programmed trigger level. Resets to one.
3 C4_TXRDY Channel 4 TXRDY R
This bit reflects status of the TXRDY pin on Channel 4 of the UART, which in turn
indicates status of the Channel 4 Transmit FIFO. A one indicates that the Transmit FIFO
trigger level has been reached. A zero indicates that the Transmit FIFO is below the
trigger level. Resets to zero.
2 C3_TXRDY Channel 3 TXRDY R
This bit reflects status of the TXRDY pin on Channel 3 of the UART, which in turn
indicates status of the Channel 3 Transmit FIFO. A one indicates that the Transmit FIFO
trigger level has been reached. A zero indicates that the Transmit FIFO is below the
trigger level. Resets to zero.
1 C2_TXRDY Channel 2 TXRDY R
This bit reflects status of the TXRDY pin on Channel 2 of the UART, which in turn
indicates status of the Channel 2 Transmit FIFO. A one indicates that the Transmit FIFO
trigger level has been reached. A zero indicates that the Transmit FIFO is below the
trigger level. Resets to zero.
0 C1_TXRDY Channel 1 TXRDY R
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

13
This bit reflects status of the TXRDY pin on Channel 1 of the UART, which in turn
indicates status of the Channel 1 Transmit FIFO. A one indicates that the Transmit FIFO
trigger level has been reached. A zero indicates that the Transmit FIFO is below the
trigger level. Resets to zero.
Note: For information on setting Receive and Transmit FIFO trigger levels, please refer to
the XR16C854 UART data sheet. (The XR16C854 UART data sheet contains a
discrepancy in its description of the TXRDY pin. The TXRDY pin does not indicate if at
least one empty location is available in Transmit FIFO. Instead, it indicates whether the
trigger level is reached as described in the FIFO Ready Register Definition.)
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

14
FRR58 FIFO Ready Channels 5-8
7 6 5 4 3 2 1 0 Bit
C8_RXRDY C7_RXRDY C6_RXRDY C5_RXRDY C8_TXRDY C7_TXRDY C6_TXRDY C5_TXRDY Read
X X X X X X X X Write
1 1 1 1 0 0 0 0 Reset
FIFO Ready Channels 5-8 reflect the status of Transmit FIFO Channels 5-8 and Receive
FIFO Channels 5-8.
7 C8_RXRDY Channel 8 RXRDY R
This bit reflects status of the RXRDY pin on Channel 8 of the UART, which in turn
indicates status of the Channel 8 Receive FIFO. A zero indicates that the FIFO has
reached the programmed trigger level or a time-out has occurred. A one indicates that
the FIFO is below the programmed trigger level. Resets to one.
6 C7_RXRDY Channel 7 RXRDY R
This bit reflects status of the RXRDY pin on Channel 7 of the UART, which in turn
indicates status of the Channel 7 Receive FIFO. A zero indicates that the FIFO has
reached the programmed trigger level or a time-out has occurred. A one indicates that
the FIFO is below the programmed trigger level. Resets to one.
5 C6_RXRDY Channel 6 RXRDY R
This bit reflects status of the RXRDY pin on Channel 6 of the UART, which in turn
indicates status of the Channel 6 Receive FIFO. A zero indicates that the FIFO has
reached the programmed trigger level or a time-out has occurred. A one indicates that
the FIFO is below the programmed trigger level. Resets to one.
4 C5_RXRDY Channel 5 RXRDY R
This bit reflects status of the RXRDY pin on Channel 5 of the UART, which in turn
indicates status of the Channel 5 Receive FIFO. A zero indicates that the FIFO has
reached the programmed trigger level or a time-out has occurred. A one indicates that
the FIFO is below the programmed trigger level. Resets to one.
3 C8_TXRDY Channel 8 TXRDY R
This bit reflects status of the TXRDY pin on Channel 8 of the UART, which in turn
indicates status of the Channel 8 Transmit FIFO. A one indicates that the Transmit FIFO
trigger level has been reached. A zero indicates that the Transmit FIFO is below the
trigger level. Resets to zero.
2 C7_TXRDY Channel 7 TXRDY R
This bit reflects status of the TXRDY pin on Channel 7 of the UART, which in turn
indicates status of the Channel 7 Transmit FIFO. A one indicates that the Transmit FIFO
trigger level has been reached. A zero indicates that the Transmit FIFO is below the
trigger level. Resets to zero.
1 C6_TXRDY Channel 6 TXRDY R
This bit reflects status of the TXRDY pin on Channel 6 of the UART, which in turn
indicates status of the Channel 6 Transmit FIFO. A one indicates that the Transmit FIFO
trigger level has been reached. A zero indicates that the Transmit FIFO is below the
trigger level. Resets to zero.
0 C5_TXRDY Channel 5 TXRDY R
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

15
This bit reflects status of the TXRDY pin on Channel 5 of the UART, which in turn
indicates status of the Channel 5 Transmit FIFO. A one indicates that the Transmit FIFO
trigger level has been reached. A zero indicates that the Transmit FIFO is below the
trigger level. Resets to zero.
Note: For information on setting Receive and Transmit FIFO trigger levels, please refer to
the XR16C854 UART data sheet. (The XR16C854 UART data sheet contains a
discrepancy in its description of the TXRDY pin. The TXRDY pin does not indicate if at
least one empty location is available in Transmit FIFO. Instead, it indicates whether the
trigger level is reached as described in the FIFO Ready Register Definition.)
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com