SBS Technologies P-Octal Series User manual

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Instra

Px-Octal
PC•MIP Modules with
Eight Serial Channels
User Manual
© SBS Technologies, Inc.
Subject to change without notice.
Part No. 89004225 Rev. 3.0 20050114
Hardware Revision: P1: B P2: B
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Px-Octal
PC•MIP Modules with
Eight Serial Channels
SBS Technologies, Inc.
1284 Corporate Center Drive
St. Paul, MN 55121-1245
Tel [phone]
FAX [phone]
Email: [email protected]
www.sbs.com
©2000, 2002, 2005 SBS Technologies, Inc.
IndustryPack is a registered trademark of SBS
Technologies, Inc. QuickPack, SDpacK and Unilin
are trademarks of SBS Technologies, Inc. PC•MIP
is a trademark of SBS Technologies, Inc. and MEN
Micro Inc.
SBS Technologies, Inc. acknowledges the
trademarks of other organizations for their
respective products mentioned in this document.
A
ll rights are reserved: No one is permitted to
reproduce or duplicate, in any form, the whole or
part of this document without the express consent of
SBS Technologies, Inc. This document is meant
solely for the purpose for which it was delivered.
SBS Technologies reserves the right to make any
changes in the devices or device specifications
contained herein at any time and without notice.
Customers are advised to verify all information
contained in this document.
The electronic equipment described herein
generates, uses, and may radiate radio frequency
energy, which can cause radio interference. SBS
Technologies assumes no liability for any damages
caused by such interference.
SBS Technologies’ products are not authorized for
use as critical components in medical applications,
such as life support equipment, without the express
consent of the General Manager of SBS
Technologies, Inc. Commercial Group.
This product has been designed to operate with
IndustryPack, PC•MIP or PMC modules or carriers,
and compatible user-provided equipment.
Connection of incompatible hardware is likely to
cause serious damage. SBS Technologies assumes
no liability for any damages caused by such
incompatibility.
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Table of Contents
PRODUCT DESCRIPTION________________________________________________ 1
BLOCK DIAGRAMS_____________________________________________________ 2
QUICK START _________________________________________________________ 5
UART RESET_________________________________________________________ 5
CHANNEL 1CONFIGURATION ____________________________________________ 6
CHANNEL 8CONFIGURATION ____________________________________________ 6
TRANSMITTING AND READING ___________________________________________ 6
CHANNEL NUMBERING _________________________________________________ 7
PCI CONFIGURATION REGISTERS ________________________________________ 8
MEMORY SPACE______________________________________________________ 10
ALTERA-IMPLEMENTED REGISTERS ______________________________________ 11
CR Control Register ________________________________________________ 11
FRR14 FIFO Ready Channels 1-4 _____________________________________ 12
FRR58 FIFO Ready Channels 5-8 _____________________________________ 14
GISR Global Interrupt Status Register __________________________________ 16
UART-IMPLEMENTED REGISTERS _______________________________________ 17
INTERRUPTS _________________________________________________________ 18
INTERRUPT ARCHITECTURE ____________________________________________ 18
ENABLING INTERRUPTS _______________________________________________ 18
SERVICING INTERRUPTS _______________________________________________ 18
DISABLING INTERRUPTS _______________________________________________ 18
ADVANCED INTERRUPT FEATURES ______________________________________ 18
USER OPTIONS_______________________________________________________ 19
USER-SUPPLIED OSCILLATOR __________________________________________ 19
USER-SWITCHABLE TERMINATION RESISTORS _____________________________ 19
CONNECTOR PIN ASSIGNMENTS________________________________________ 20
J1_________________________________________________________________ 20
J2_________________________________________________________________ 21
J3_________________________________________________________________ 22
J4_________________________________________________________________ 25
P1-OCTAL-232 SPECIFICATIONS ________________________________________ 27
P1-OCTAL-422 SPECIFICATIONS ________________________________________ 28
P1-OCTAL-TTL SPECIFICATIONS ________________________________________ 29
P2-OCTAL-232 SPECIFICATIONS ________________________________________ 30
P2-OCTAL-422 SPECIFICATIONS ________________________________________ 31
REPAIR _____________________________________________________________ 32
SERVICE POLICY _____________________________________________________ 32
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List of Figures
FIGURE 1. BLOCK DIAGRAM -VERSION 232 ___________________________________ 2
FIGURE 2. BLOCK DIAGRAM -VERSION 422 ___________________________________ 3
FIGURE 3. BLOCK DIAGRAM -TTL VERSION___________________________________ 4
FIGURE 4. QUICK START PIN CONNECTIONS TO TRANSMIT CHARACTERS -232
VERSIONS _____________________________________________________________ 5
FIGURE 5. QUICK START PIN CONNECTIONS TO TRANSMIT CHARACTERS -422
VERSIONS _____________________________________________________________ 5
FIGURE 6. QUICK START PIN CONNECTIONS TO TRANSMIT CHARACTERS -TTL
VERSION_______________________________________________________________ 5
FIGURE 7. CHANNEL NUMBERING___________________________________________ 7
FIGURE 8. PCI CONFIGURATION REGISTERS __________________________________ 8
FIGURE 9. READ-ONLY PCI CONFIGURATION REGISTER VALUES –RS-232 VERSIONS _9
FIGURE 10. READ-ONLY PCI CONFIGURATION REGISTER VALUES –RS-422 VERSIONS 9
FIGURE 11. READ-ONLY PCI CONFIGURATION REGISTER VALUES -TTL VERSION ____ 9
FIGURE 12. MEMORY ADDRESS MAP _______________________________________ 10
FIGURE 13. UART REGISTER MAP _________________________________________ 17
FIGURE 14. USER-SUPPLIED OSCILLATOR DIMENSIONS ________________________ 19
FIGURE 15. CONNECTOR J1 PIN ASSIGNMENTS ______________________________ 20
FIGURE 16. CONNECTOR J2 PIN ASSIGNMENTS ______________________________ 21
FIGURE 17. THE P1-OCTAL-232 FLEXIBLE I/O CONNECTOR J3 PIN ASSIGNMENTS ___ 22
FIGURE 18. THE P1-OCTAL-422 FLEXIBLE I/O CONNECTOR J3 PIN ASSIGNMENTS ___ 23
FIGURE 19. THE P1-OCTAL-TTL FLEXIBLE I/O CONNECTOR J3 PIN ASSIGNMENTS ___ 24
FIGURE 20. THE P2-OCTAL-232 FRONT PANEL CONNECTOR J4 PIN ASSIGNMENTS __ 25
FIGURE 21. THE P2-OCTAL-422 FRONT PANEL CONNECTOR J4 PIN ASSIGNMENTS __ 26
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1
Product Description
The Px-Octal product family provides eight channels of EIA-232, EIA-422, or TTL-compatible
(3.3V) asynchronous serial communication on a Type I (flexible I/O) or Type II (front panel
I/O) PC•MIP module. The high channel density makes the Px-Octal module ideal for
communications applications that require a large number of serial channels in a small space.
Five versions of the Px-Octal family are documented here:
•P1-Octal-TTL is a Type I (flexible I/O) module with TTL-compatible (3.3V) driver support.
•P1-Octal-232 is a Type I (flexible I/O) module with EIA-232 driver support.
•P1-Octal-422 is a Type I (flexible I/O) module with EIA-422 driver support.
•P2-Octal-232 is a Type II (front panel I/O) module with EIA-232 driver support.
•P2-Octal-422 is a Type II (front panel I/O) module with EIA-422 driver support.
In addition to the common core design features of these modules, this manual documents the
differences in serial drivers and I/O routing for these products.
The Px-Octal family features two quad UART SCCs with 128 bytes of transmit FIFO and 128
bytes of receive FIFO per channel. Data rates of up to 460.8 kbaud are supported for RS-422
communications, and up to 115.2 kbaud for the RS-232 and TTL (3.3V) communications.
Serial signals for each channel are routed to the flexible I/O connector for rear-panel access.
For the RS-232 and RS-422 options, all signals are ESD-protected up to ±15 kV, according
to IEC 1000.4.2 specifications.
Baud rate is software-configurable from 50 bps to the maximum rate via the on-board
programmable baud rate generator. Interrupts are fully supported per channel with four
programmable transmit/receive FIFO interrupt trigger levels. In addition, programmable bit
length, parity, and stop bits are provided to support all asynchronous protocols.
A VxWorks 5.3 driver and a Windows NT 4.0 are available. The Px-Octal modules are
compatible with the PC•MIP draft specification (ANSI/VITA-29).
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2
Block Diagrams
Figure 1. Block Diagram - Version 232
PCI BUS ALTERA EPF6016
QUAD
UART
QUAD
UART
DATA
ADDRESS
CONTROL
7.3728
MHz
CLOCK
OPTIONAL
CUSTOM
CLOCK
CLOCK
DATA
ADDRESS
CONTROL
CLOCK
CONTROL
REGISTER
FIFO READY
REGISTER
GLOBAL
INTERUPT
VECTOR
PCI
TARGET
MEGA
CORE
CONTROL
LOGIC
TXD
RXD
RTS
CTS
TXD
RXD
RTS
CTS
CHAN 1
CHAN 8
RS232
TRANSCEIVERS
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3
Figure 2. Block Diagram - Version 422
PCI BUS ALTERA EPF6016
QUAD
UART
QUAD
UART
DATA
ADDRESS
CONTROL
7.3728
MHz
CLOCK
OPTIONAL
CUSTOM
CLOCK
CLOCK
DATA
ADDRESS
CONTROL
CLOCK
CONTROL
REGISTER
FIFO READY
REGISTER
GLOBAL
INTERUPT
STATUS
PCI
TARGET
MEGA
CORE
CONTROL
LOGIC
TXD
RXD
TXD
RXD
CHAN 1
CHAN 8
RS422
TRANCEIVERS
Switchable
Termination
Resistors
Switchable
Termination
Resistors
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4
PCI BUS ALTERA EPF6016
QUAD
UART
QUAD
UART
DATA
ADDRESS
CONTROL
7.3728
MHz
CLOCK
OPTIONAL
CUSTOM
CLOCK
CLOCK
DATA
ADDRESS
CONTROL
CLOCK
CONTROL
REGISTER
FIFO READY
REGISTER
GLOBAL
INTERUPT
VECTOR
PCI
TARGET
MEGA
CORE
CONTROL
LOGIC
TXD
RXD
RTS
CTS
TXD
RXD
RTS
CTS
CHAN 1
CHAN 8
DIRECT TTL
CONNECTION
Figure 3. Block Diagram - TTL Version
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5
Quick Start
Each channel is implemented by a unique set of UART registers but also shares the
global control, FIFO ready, and interrupt status registers implemented in the Altera
device.
This section illustrates how to:
1. Configure Channel 1 and Channel 8 for 9600 baud rate, 8 data bits, 1 stop bit,
and no parity
2. Transmit two bytes from Channel 1
3. Read the two transmitted bytes from Channel 8
All addresses indicate offset from BAR0. To transmit characters from Channel 1 to
Channel 8, Channel 1 TxD pin should be connected to Channel 8 RxD pin as illustrated
in the figure below:
Connect From Connect To
Board Pin Signal Pin Signal
P1-Octal-232 2 49
P2-Octal-232 2 TxD 1 34 RxD 8
Figure 4. Quick Start Pin Connections to Transmit Characters - 232 Versions
Connect From Connect To
Board Pin Signal Pin Signal
2 TxD- 1 51 RxD- 8
P1-Octal-422 3 TxD+ 1 52 RxD+ 8
2 TxD- 1 35 RxD- 8
P2-Octal-422 3 TxD+ 1 36 RxD+ 8
Figure 5. Quick Start Pin Connections to Transmit Characters - 422 Versions
Connect From Connect To
Board Pin Signal Pin Signal
P1-Octal-TTL 2 TxD 1 49 RxD 8
Figure 6. Quick Start Pin Connections to Transmit Characters - TTL Version
On the P1-Octal versions, the connection is made at the backplane or on the carrier
board at a user I/O connector. Be careful to join the correct pins.
UART Reset
•Write 0x10 to offset 0x0500
Write 0x00 to offset 0x0500
(This step resets both UARTs. It is recommended to delay 500ms between the two
writes.)
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