SDS 925 User manual

Price:
$3.50
SDS
925/930/9300
INPUT/OUTPUT
INTERFACE
DESIGN MANUAL
SDS
900561 A
December 1965
SCIENTIFIC
DATA
SYSTEMS. 1649 Seventeenth
Street.
Santa Monica, Calif
.•
(213) 871-0960
©1965,
Scientific Data Systems, Inc.

ii
PREFACE
This manual describes
the
Input/Output
System
available
with
the
SDS
925/930/9300
Computers with special emphasis
placed
on
the
available
interface
signals and
con-
nections. The
interface
described represents
the
junction between
the
Input/Output
communication channels and
the
external equipment. In
the
case of System Priority
Interrupts
it
describes
the
junction requirements between external interrupt input
sig-
nals
and
the
Priority Interrupt Chassis.
Detailed
descriptions of
each
available
interface
connection
is
stressed to
facilitate
the
efficient
design
or
implementation
of
the
coupling
electronics
required to
connect
external units to
the
computeri therefore,
the
reader should
be
familiar with
the
following publications
pertinent
to his
specific
appl ication.
SDS
925 Reference Manual
SDS
925 Theory of Operation Manual
SD
S 930 Reference ManuaI
SDS
930 Theory of Operation Manuai
SDS
9300 Reference Manual
SDS
9300 Theory
of
Operation
ManuaI
Models 93200/93202
TMCC
Model 91602 Data Multiplex Channel -
DMC
Model 91500 Memory
Interface
Connection
900099A
900633
9000648
900066
900050C
900570
900685
900828
900808

CONTENTS
Section
Page
Section
Page
INPUT/OUTPUT
SYSTEMS
1-1
Output
Termination
3-8
Interlace
Operation
3-8
General
Description 1-1
Direct
Access Communication
Time-Mu
Itiplexed
Communication
Channel
(DACC)
3-9
Channel
(TMCC) 1-1 Memory
Interface
Connection
(MIC)
3-12
POT, PIN Instructions
1-3
Data
Multiplexing
System (DMS)
3-12
Single-Bit
Input/Output
1-3
Data
Subchannel (DSC)
3-14
Mu Itiple Access to Memory
1-3
DSC-I
Operation
3-14
Direct
Access Communication DSC-II
Operation
3-14
Channe
I (DACC)
1-3
Input/Output
Usi
ng ExternaI
Data
Multiplexing
System (DMS)
1-3
Interlace
3-19
Data
Multiplex
Channel
(DMC)
1-3
Word
Increment
Function
3-19
Data
Subchannels (DSC)
1-3
Priority
Interrupt
Operation
3-20
External
Interlace
(EIN)
1-4
Interrupt
States
3-20
Memory
Interface
Connection
(MIC)
1-4
Interface
Signals 3-21
Priority Interrupt
1-4
II INPUT/OUTPUT INSTRUCTIONS 2-1 IV INTERFACE CIRCUIT
AND
CABLE
REQUIREMENTS 4-1
General
2-1
Energize
Output
M (EOM) 2-1
General
4-1
Buffer Control E
OM
2-1
Cable
Requirements 4-1
Internal
Control EOM 2-1
Connector
Requirements
4-1
Input/Output
Control EOM 2-1
Circuit
Requirements
4-1
System Control EOM 2-1
Output
Circuits
4-1
E
OM
Interface
Signa
Is
2-2
low-Speed
Outputs,
Type
01
4-1
Energize
Output
to
Direct
Access
low-Speed
Outputs,
Circuit
Type
02
4-3
Channels
(EOD)
2-2
High-Speed
Outputs,
Circuit
EOD
Interface
Si
goo
Is
2-2
Type
03
4-3
Parallel
Output
(POT)
2-3
Input
Circuits
4-4
POT
Interface
Si
gna
Is
2-3
Input
Circuit
Type
11
4-4
Parallel
Input
(PIN)
2-4
Input
Circuit
Type
12
4-5
PIN
Interface
Signals
2-4
Input
Circuit
Type
13
4-5
SDS 925
Specia
I
I/O
Operations
2-5
Input
Circuit
Type 14
4-5
Input
(BPI)
2-5
Drivi ng Input Signals
4-5
Output
(BPO)
2-5
Hi
gh-
Speed Inputs
4-6
Skip If Signal
Not
Set (SKS)
2-6
Formulae for lRC
Circuits
4-6
S
KS
Interface
Si
gna
Is
2-6
Standard
Cables
4-6
III INPUT/OUTPUT CHANNEL V INTERFACE
CONNECTOR
PIN
DESCRIPTION 3-1 DESCRIPTIONS
5-1
General
3-1
General
5-1
Time
Multiplexed
Communication TMCC
Interface
Connectors
5-1
Channel
(TMCC) 3-1 DACC
Interface
Connectors
5-21
Interlace
3-1 MIC
Interface
Connector
5-36
Input
3-1 DSC-I
Interface
Connectors 5-41
Input
Clock
Characteristics
3-5
DSC-II
Interface
Connectors
5-41
Input
Termination
3-5
System Priority
Interrupt
Interface
Output
Timing
3-5
Connectors
5-50
iii

Figures
Tables
Page Page
1-1
925/930/9300
General Computer 1-1 TMCC Models 1-1
Configuration
1-2
3-1 Unit Address Codes
3-3
2-1 Signals
Generated
by EOM Instructions
2-2
3-2
Interlace
Extended Mode Termina I
3-8
2-2
Signals
Generated
by EOD Instruction
2-2
3-3
DACC Terminal Functions Extended Mode 3-11
2-3
Signals
Generated
by
POT
Instruction
2-4
3-4
Unit Address Codes 3-11
2-4
Signals
Generated
by PIN Instruction
2-5
3-5
EOM/POT/SKS
Function Combinations
3-15
2-5
Signals
Generated
by 925
BPI
Instruction
2-6
3-6
Relationship
of
DMC Functions
and
2-6
Signals
Generated
by 925 BPO Instruction
2-7
Interface
Signals
3-17
2-7
Signa
Is
Generated
by
S
KS
Instruction
2-7
4-1 R/L Network Values
4-2
3-1 TMCC Simplified Block Diagram
3-2
4-2
Standard Cables Assemblies
4-6
3-2
Input Timing
Characteristics
5-1 TMCC W Buffer
Interface
Connectors
Asynchronous Mode
3-4
(AU)0N~A)
5-1
3-3
Input
Clock
Timing Diagram
3-6
5-2
TMCC W Buffer
Interface
Connector
3-4
TMCC Input Timing, Synchronous
Clock
3-7
(DISCW)
5-3
3-5
TMCC
Output
Timing, Synchronous Clock
3-7
5-3
TMCC W Buffer
Interface
Connectors (PIN)
5-5
3-6
DACC Timing, Asynchronous Input Mode
3-9
5-4
TMCC W Buffer
Interface
Connectors (POT)
5-7
3-7
DACC Timing, Synchronous Input Mode
3-9
5-5
TMCC W Buffer
Interface
Connector
3-8
DACC Timing, High-Speed Synchronous
(MAGW)
5-9
Input Mode
3-10
5-6
TMCC W Buffer
Interface
Connectors
(WRDW)
5-11
3-9
MIC Input Timing ( Zo True)
3-13
5-7
TMCC Y Buffer
Interface
Connectors
3-10
MIC
Output
Timing ( Zo False)
3-13
(AUXY-B)
5-13
3-11 Timing Diagram DSC-II Terminating
5-8
TMCC Y Buffer
Interface
Connector (DISCY)
5-15
Input/Output
with External Address
3-16
5-9
TMCC Y Buffer
Interface
Connector
(MA
GY)
5-17
3-12
Timing Diagram DSC-II Terminating
5-10
TMCC Y Buffer
Interface
Connectors
(WRDY)
5-19
Input/Output
with ExternarAddress
3-18
5-~
11
DACC
Interface
Connectors (AUX) 5-21
3-13
Timing Diagram DSC-II
Input/Output
5-12
DACC
Interface
Connector
(DISC)
5-23
Using Internal
Interlace
3-19
5-13
DACC
Interface
Connector
(MA
G)
5-25
3-14
Timing Diagram DSC-II Word
5-14
DACC
Interface
Connectors (PIN)
5-27
Increment Function
3-20
5-15
DACC
Interface
Connectors (POT)
5-29
3-15
System Priority Interrupt Configuration 3-21
5-16
DACC
Interface
Connectors
(WRD)
5-31
4-1 Typical AND
Gate
4-1
5-17
DACC
Interface
Connectors (ZIN)
5-33
4-2
Cable
Driver AK53 4-1
5-18
DACC
Interface
Connectors (ZOUT)
5-35
4-3
Typical
Interface
Connection, Low-Speed
5-19
MIC
Interface
Connectors
(MCTL)
5-36
Outputs, Type
01
4-2
5-20
MIC
Interface
Connectors (MIN)
5-38
4-4
Cable
Driver AK57
Output
4-3
5-21 MIC
Interface
Connectors (MOUT)
5-39
4-5
Low-Speed Output,
Circuit
Type
02
4-3
5-22
DSC-II
(W)
Interface
Connector
4-6
Cab
Ie
Driver A
K56
4-3
(DSC
Control) 5-41
4-7
High-Speed
Output,
Circuit
Type
03
4-3
5-23
DSC-II
(X)
Interface
Connector
4-8
Cable
Driver AK56 Loading
4-4
(DSC Control)
5-44
4-9
Interface
Inverter,
NB50
4-4
5-24
DSC-II
(W)
Interface
Connector
(DSC
In)
5-46
4-10
Input Signal
Gating
4-4
5-25
DSC-II
(X)
Interface
Connector
(DSC
In)
5-48
4-11 Input
Circuit
Type
13
4-5
5-26
DSC-II
(Wand
X)
Interface
Connectors
4-12
Interrupt Inputs Type
14
4-5
(DSC
Out)
5-49
4-13
Low-Speed Input Cab
Ie
Driver AX14
4-5
5-27
ChanneI Priority Interrupt, Arming
4-14
AX14 Driving Low-Speed Input
4-5
Interrupt 5-51
4-15
High-Speed Input Connection
4-6
5-28
Directory Priority Interrupt
5-52
iv

SECTION
I
INPUT/OUTPUT
SYSTEMS
GENERAL
DESCRIPTION
The standard
I/O
system provided with a
II
SDS
925/930/
9300 Computers allows operations with a
II
standard
SDS
peripheral equipment as
well
as with
special
purpose
devices.
Alternate
I/O
system options
are
available
which
are
of
particular
use for systems handling multiple sources
of
data
and
for systems requiring very high
data
acquisition
rates.
Two
separate
paths
along
which
I/O
data
can
flow
to
and
from memory
are
provided for
the
SDS
925/930/9300
Computers. Figure 1-1 shows
input/output
memory paths
and
systems configuration.
The
first path is the normal path
that
exists
between
memory and
the
central
processor;
the
second path exists between memory
and
the
I/O
control
units
via
a
Multiple
Access to Memory unit (MAM).
Advantages of
the
multiple
access
to memory
feature
are:
I/O
memory accessing without loss of computation time;
higher
data
transfer rates;
and
program simplification.
Although
all
I/O
channels
avai
lable with
the
multiple
access
to
memory option
are
available
to
the
SDS
925, this
computer treats
all
input
and
output
operations on a priority
time multiplexed basis only
since
the
SDS
925 can have no
more
than
one memory bank.
The first path of
data
flow
between
memory and
central
processor uses
the
following methods
of
I/O
information
transfer:
a.
Time
Multiplexed
Communication Channels (TMCC)
b. Parallel Input (PIN)
c.
Parallel
Output
(POT)
d. Single-Bit
Input/Output
The second path of
data
flow
between
memory and
I/O
control units
and
devices
uses
the
following methods of
transfer:
a.
Data
Multiplexing
System (DMS)
b.
Direct
Access Communication Manuals (DACC)
c.
Memory
Interface
Connection
(MIC)
All second path to memory systems communicate with
memory through a
Multiple
Access to Memory unit (MAM).
Two
or more
separate
memory banks
are
a prerequisite for
taking
full
advantage
of the multiple access to memory
option.
TIME-MULTIPLEXED
COMMUNICATION
CHANNEL
(TICC)
The basic
925/930/9300
configuration includes one TMCC
for
6-bit
character
input/output.
This
TMCC
is
referred to
as the W
channel
in
the
925/930
and
as the A channel in
the 9300. The TMCC
is
capable
of
controlling
I/O
devices
such as
typewriter,
paper
tape,
card,
magnetic
tape,
and
line printers on a time multiplexed basis. A computer may
have
from
one
to four TMCC's
connected
to
it. Additional
channels
are
designated Y
(B
on 9300),
C,
and
D.
The
basic model number
is
93200. Model numbers for
additional
channels and optional features
are
listed in
table
1-1.
Any
6-bit
TMCC
can
be
expanded
to
12 bits by
adding
the
Model 93201 option
or
to
24 bits by
addition
of
the
Model
93202 option. With
the
12-
and/or
24-bit
options
character
size
is
controlled
by
the
external
device.
The
24-bit
buffer
can
handle
either
6,
12, or 24
bit
characters
according
to
device
requirements.
Table
1-1.
TMCC Models
Used on
Model Description Channel
93200
6-bit
characters,
without
interlace,
W(A), C
single
channel
91210
Interlace
option for 93200
93201
12-bit
character
extension option
for 93200
93202
24-b
it
character
extension option
for 93200
93221
6-bit
characters,
without
interlace,
W(A}plus
two
channe
Is
Y(B}
or
91210
Interlace
option for
either
channel C plus D
of
93221
93201
12-bit
character
extension option
for
either
channel of 93221
93202
24-b
it
character
extension option
for
either
channel
of 93221
The memory
interlace
feature
may be
added
to
any
TMCC
by
adding the Model 91210 Memory
Interlace
Control unit.
This optional
feature
is
useful for
input/output
of large
blocks of
data
at
high transfer rates.
Jhe
memory
interlace
automatically
controls the transfer of
data
words for its
associated
channel
buffer by maintaining a current memory
address and word
count
during
input/output
operations.
1-1

I
'"
"
to
C
(i
I
-0
'"
01
~
W
o
~
w
o
o
G)
(1)
:J
(1)
a
()
o
3
"0
c
m
....
()
o
:J
:;,:
to
C
9-
o·
:J
~
~
Priority Control
00000000000000
< Single-Bit
I/O
EOM/EOD -
SKS-----:.
< Direct Parallel
I/O
POT/PIN
~
< Block Parallel
Transfer-------
@
~--~x--~
d5:~D::
(1)
Part
of
Standard
925/930/9300
0) Available
on
930/9300 only
--
®
EIN
Option
EIN
Option
Memory
Bank
First Path
to Memory
Second Path to Memory
0000[>
Priority Control
~
.....
IIIIIIII~
Syste~
Interrupt
EIN
Option
.---
....
,0
Priority
DODD
[>Control

The
interlace
also
controls terminal functions
and
provides
end-of-record
and
zero
word
count
interrupts.
Channels C
and
D (and B on the 9300) must always have
interlace
installed
since
no computer instructions
exist
in
the 9300 to a Ilow use of these
channels
without
interlace.
Any TMCC
operating
with
interlace
has priority over the
centra
I processor for memory
access
with
channel
priority
in
the
order:
Channels D,
C,
Y(B), W(A).
The maximum
data
transfer
rate
of a TMCC is one word
every
two memory
cyc
les or
280,000
words per second.
POT
,PIN
INSTRUCTIONS
The
925/930/9300
Computers
include
two instructions,
parallel
output
and
parallel
input, which permit
the
transfer
of words
between
core memory
and
external
equipment
with-
out
interfering
with
the
operation
of
other
I/O
channels.
The
execution
of
either
the
POT
or
PIN instruction causes a
signal
to
be
sent
to
the
external
device
requesting it to
acknowledge
when it
is
ready
to
receive
or transmit the
data
word.
After
the
request signal
is
sent,
the
computer sus-
pends
operations
until
the
acknowledge
signal
is
received.
The maxi
mum
data
transfer
rate
for
PI
N operations
is
114,000
words
per
second
(five
cycles
for
each
word transfer). The
maximum
data
transfer
rate
for POT
operations
is
143,000
words
per
second
(four
cycles
for
each
word transfer).
The Block POT
and
Block PIN (BPO/BPI) operations
which
are
unique
to
the
SDS
925 transfer words
at
a maximum
rate
of
570,
000 words
per
second (one
cyc
Ie for
each
word
transfer).
SINGLE-BIT
INPUT/oUTPUT
The two instructions, Energize
Output
M (EOM)
and
Skip If
Signal
Not
Set
(SKS) when
operating
in the systel1l mode
are
used
to
provide
single-bit
input/output
transmission.
Execu-
tion
of
an
EOM
operating
in
the
system mode causes a
sig-
nal
to
be
transmitted to
one
of a possible
8,
192 signal
des-
tinations.
The maximum signal transfer
rate
is
570,000
pulses
per
second. Execution
of
an
S
KS
in the
specia
I
system
test
mode permits the computer to
test
the
condition
of
anyone
of
a possible
8,
192
input
lines. The maximum
test
rate
depends on
the
condition of
the
line:
286,000
per
second if program does not skip
next
instruction, or
190,000
per
second
if
program does skip
the
next
instruction.
MULTIPLE
ACCESS
TO
MEMORY
The
Mu
Itiple
Access to Memory
feature
(MAM) provides
the
necessary modules on both main frame
and
memory
to
permit
memories
to
be
accessed
via
the
second
memory
path.
Trans-
fer of
one
word
over
this path in
either
direction
requires
one
memory
cycle.
If the computer has two or more memory
banks,
the
main frame
can
communicate
with
one memory
via
the
first
path
to
one memory
while
some peripheral
device
is
communicating with
the
other
memory
via
the
second path
without
interference
or loss
of
computation time.
The
Multiple
Access to Memory
feature
(MAM)
is
required
for the
attachment
of
Direct
Access Communication Channels
(DACC), Data
Multiplex
Channels
(DMC), or Memory
Interface
Connections (MIC).
DIRECT
ACCESS
COMMUNICATION
CHANNEL
(DACC)
The
Direct
Access Communication
Channel,
Model 92220,
is
avai
lab
Ie
for systems
requiring
high-speed
input/output
simultaneous with computation.
Up
to
four
DACCs
may be
connected
to
the
core memory through
the
Multiple
Access
to
Memory (MAM), Model 92990 (Model 92992 for
the
925)
for
each
memory modu Ie. The four
channels
are
designated
E,
F,
G,
and
H.
Simultaneous
access
to
memory wi II
occur
if
the
channel
and
computer
are
addressing
separate
memory
modules.
If
simultaneous
access
to
the
same memory module
is
required,
priority
is
in
the
order:
MAM, TMCC, Central
Processor.
The maximum
data
transfer
rate
in
the
high-speed
mode
is
one
word
every
memory
cycle,
or
approximately
570,000
words
per
second.
The DACC communicates
with
external
equipment
by means
of
a
bidirectional
24-bit
register
using
6-,
8-,
12-,
or
24-bit
characters
plus a
parity
bit.
Character
size
is
con-
trolled
by
the
external
device.
DATA
MULTIPLEXING
SYSTEM
(OMS)
The
data
multiplex system consists of two basic
elements:
a.
The Data
Multiplex
Channel
(DMC) for com-
municating
with
several
data
sources/destinations,
and
for
synchronizing
I/O
operations
with
memory.
b.
One
or
more Data Subchannels (DSC) for
interfac-
ing
between
periphera
I devices or systems
and
the
DMC.
Data
Multiplex
Channel
(DMC}
The
data
multiplex
channel
is
equipped
with
an
internal
interlace
feature
that
allows
specified
input/output
tables
in memory to be processed
by
the
addressed peripheral
device
via
the
associated
subchannel.
Data
Subchannels
(OSC)
Two
standard subchannels
are
available.
Model 91711
DSC-I provides
character
oriented
operations,
and
Model
91712 DSC-lI
is
full-word
(24-bit)
oriented.
Up
to
128
DSCs
can
be
attached
to
the
DMC.
Two
or more
DSCs
can
be
active
simultaneously using
an
internal
priority
arrange-
ment
to
determine which subchannel
can
transmit
to
the
DMC
at
any
given time.
1-3

External
Interlace
(EIN)
An ExternaI I
nter
lace
ModeI 91800
can
be
attached
to
any
DSC. The EIN controls
the
transmissions of
the
DSC
at
a
maximum rate
of
one
vV'ord
per memory
cycle.
Maximum
data
transfer
rate
using
internal
interlace
is
190,000
words
per
second.
With
external
interlace
the
maximum transfer
rate
is
increased
to
570,000
words
per
second.
MEMORY
INTERFACE
CONNECTION
(MIC)
The Memory
Interface
Connection,
Model 91500, is
avail-
able
for
direct
access
to
core
memory under control or
external
equipment.
A
prerequisite
for MIC is a
Multiple
Access
to
Memory (MAM) ModeI 92990 for
each
memory
module. The 925 Computer requires
the
Mu Itiple Access
to
Memory (Model 92992). The
external
device
must provide
signals
to
the
MIC
indicating
when
an
I/O
operation
is
to
take
place,
it
must
specify
the
memory address,
and
must
indicate
whether
the
function
is
an
input
or
an
output.
The MIC
checks
parity
on inputs
and
generates
parity
on
outputs.
Data
transfer
is
in
the
form
of
24-bit
words plus
odd
parity.
The maximum
data
transfer
rate
is
570,000
words per second.
1-4
PRIORITY
INTERRUPT
The
925/930/9300
Computers
are
capab
Ie
of
program
sequence
interruption
by signals
generated
by communica-
tion channels, special features, and external equipment,
on a
priority
basis. Each
925/930/9300
includes
a
basic
interrupt
unit
that
provides two interrupts (four for 9300)
with 22 more
avai
lable
(20 more for 9300) for use
with
optional
I/O
channels
and
special
features.
Up
to
896
system
priority
interrupts for
genera
I purpose use
are
avai
1-
able
for
external
systems
by
adding
Model 93280
interrupt
control units. Each Model 93280
can
control
up
to
32
priority
interrupts. The Model 93280 does not
include
the
interrupts. However, interrupts may
be
added
to
the
Model
93280
by
connecting
a Model
93290
priority
interrupt.
Each
Model 93290
contains
two
levels
of
priority
interrupti
thus
16 ·Model
93290's
(32
levels
of
interrupt)
can
be
added
to
each
interrupt
control
un
it.
An arming
feature
may
be
added
to
the
interrupt
control
unit
by
adding
a Model 92280 arming
option
to
provide
arming for
the
first
16
levels
of
interrupt
on a Model 93280.
Arming for
the
second
16
levels of interrupts
can
be
added
by
adding
a Model 92290 arming
option
to
the
Model
92280.

SECTION
II
INPUT/OUTPUT
INSTRUCTIONS
GENERAL
Five
instructions
control
input/output
operations
of
the
925/930/9300
Computers. These
are:
a.
Energize
Output
M
(E
OM)
b.
Energize
Output
to
Direct
Access
Channels
(EOD)
c.
Parallel
Input (POT)
d.
Parallel
Input (PIN)
e.
Skip
If
Signal
Not
Set (SKS)
In
addition
to
the
five instructions
above
the
SDS
925
pro-
vides for a b lock transfer
variation
of
the
POT
and
PIN
operations,
BPO
and
BPI.
In this manual emphasis
is
placed
on
interface
information
and
the
reader
should
refer
to
the
925,
930,
or
9300
reference
manual for a
detailed
descrip-
tion
of
each
instruction.
ENERGIZE
OUTPUT
M
(EOM)
The EOM
instruction
is used primarily
to
control
input/
output
through
all
channels
except
the
DACC. This
instruc-
tion
operates
in four basic modes
that
are
program se
lect-
able
by
the
setting
of two bits
(Cl0,
Cll)
within
the EOM
instruction
format:
Cl0
Cll
Function
0 0 Buffer Control
0
Input/Output
Control
0
Interna
I Control
System ControI
One
computer
cyc
Ie
(1. 75
I-Isec)
is required to
execute
an
EOM
instruction
in
any
mode. During
the
execution
of
the
EOM
instruction
the
control
register
(C
register)
of
the
computer
is
held
stable.
At
that
time this
24-bit
register
(CO-C23)
contains
the
EOM
instruction
word. The
output
of
this
register
is
avai
lable
to
the
TMCC and
to
the
external
units.
If
an
interrupt
occurs during
the
execution
of
any
EOM in
any
mode,
it
wi II
not
be
acknow
ledged
unti I
the
execution
of
the
instruction following
the
E
OM
is
complete.
Buffer
Control
EO
M
The EOM
instruction
operating
in
the
buffer control mode
prepares
the
channel
and
device
for
data
transmissions
or
other
peripheral
activities.
The
channel
to
be
used, the
peripheral
unit
on
that
channel,
the
operation
to
be
performed, and the type
of
character
format to be used,
are
all
detailed
within
the
EOM in this mode. The use
of
BCD
or
binary
data
transmission,
the
allowance
or
not
of
a
leader
(as
in
paper
tape
functions),
and
the
direction
of
operation
(in
magnetic
tape
functions)
are
all
detailed
to
the
channel
and
its
connected
periphera
I unit. Execution of such
an
EOM
connects
the
specified
peripheral
unit to
the
channel.
Interlace
can
also
be
alerted
with
EOM in this mode.
Internal
Control
EOM
The EOM in the
internal
control
mode is used to
enable
and
disable
the
interrupt
system, to
prepare
the
system for
the
selective
arming
and
disarming of the system
interrupt
levels,
to
reset
the
overflow, and
to
record
exponent
overflow.
The EOM,
internal
control mode, does not
apply
directly
to
I/O
control,
and
therefore,
it
does
not
generate
interface
signa
Is.
Input/Output
Control
EOM
The EOM in
the
input/output
mode is used
to
direct
periph-
eral
devices
to
perform
nontransmitting
operations
such as
rewind
magnetic
tape
and
upspace
the
printer.
Selection
of
certain
channel
operations such as
interrupt
response and
the
input/output
terminal
function
desired
is
made
with
this
EOM. It
is
also
used
to
alert
peripheral
devices
that
a
Parallel
Input (PIN)
or
Parallel
Output
(POT) instruction
is
to
follow. The C
register
outputs,
C18 through
C23,
must
be
decoded
by
the
external
unit
during
this instruction
to
avoid
interference
with
standard
device
control.
System
Control
EOM
The EOM in
the
system control mode
can
control
internal
equipment
by
providing
a
single-bit
output
of
approximately
1.4
I-Isec
to
any
add~essable
connector.
The system control
mode
can
be
divided
into two
distinct
submodes
by
gating
bit
9 with bits
10
and
11
of
the
system mode EOM.
Cl
C9
Cl0
Cll
x
X
o E
OM
System ControI (Externa
I)
EOM System Control
(Internal)
The
internal
system control submode provides control for
standard
I/O
systems such as the DMS,
data
communications,
and
display. The
external
system control submode provides
a means of
controlling
special
non-standard
I/O
equipment
or
systems.
Cl
must always
be
included
in
the
decoding
circuitrY.!1nce
the
term
Cl
separates
the
Data
Mu
Itiplex
System (C1) from
other
I/O
buffer units (C1).
2-1

EO
M I
nterface
Signals
Four signals
generated
by the
EOM
instruction
are
available
at
the
TMCC
I/O
connectors. See figure
2-1.
These
sig-
nals, when
true,
indicate
that
the contents
of
the C register
(CO-C23)
are
to be transferred to external equipment. The
four signals
are:
a.
~
b.
~
(Buffer Control Mode)
c.
0;)
(I/o
Control Mode)
d.
GV
(System Control Mode)
The signals,
@,
Q,
and®,
indicate
to the
external
system which EOM mode
is
currently
being
executed.
The
Eom
signal
is
generated
by all EOM instructions,
and
is
true during periods
T7
-
Tr
(1. 4 flsec). The
Eom
pulse
is
also
generated
during
the
FILL
operation.
The
Eom
signal
is
inhibited during
the
second EOM instruction
of
the
interlace
loading
sequence
and
during
time-share
operations.
The
signals,~
and~are
derived
from
the
EOM
instruction
according
to configuration
of
bits
Cl,
Cl0,
and
Cll.
Signal
W(A)
Y(B)
Cl
Cl0
Cll
Cl
Cl0
Cll
Time
----t
..
~
TMCC
C,
D
Cl
C10
Cll
Cl
C10
Cll
r----EOM Instruction
~
I (1.75
~ec)
I
18171615141312111°IRIPI
~
L
~
L
L
@ through
E=:C
Register
Stable
-~-~
I
@ !
900561A.21 1
Figure 2-1. Signals
Generated
by EOM Instructions
2-2
The terms C17 and C17 must be used by the external system
to distinguish between TMCC-W(A)
and
TMC-Y(B),
and,
similarly, between TMCC-C
and
TMCC-D.
C
17
TMCC-W(A)
or
TMCC-C
C17 TMCC-Y(B)
or
TMCC-D
The ® signal
is
derived from
the
EOM instruction
{external system submode}
according
to bits
C9,
C
10
and
C11. ® =
C9
ClO
Cl1
If
the
contents
of
the
C
C~)er
(CO,
C',
C2,
C12-C23)
are
decoded
during the
Sys
signal,
up
to
32,768
single-
bit outputs
can
be
obtained.
ENERGIZE
OUTPUT
TO
DIRECT
ACCESS
CHANNELS
(EOO)
The
EO
D instruction
is
used to control
input/output
through
the DACC. This instruction
is
similar
to
the
EOM instruc-
tion
and
performs analogous functions for the
direct
access
channels
E,
F,
G,
and
H.
EOO
Interface
Signals
Four signais
generated
by
the
roo instruction
are
available
at
the
DACC
I/O
connectors. See figure
2-2.
These
sig-
nals, when
true,
indicate
that
the contents
of
the C register
Time
----t.~
r----
EOO Instruction
....
1
/ (1.75
~ec)
Signal
/8
171615/4/3/211101
RIP/
l®
~ L
@
~
L
cg
,
@throughE:-C
Register
Stable==--
,@
I
I 900561A.22
Figure 2-2. Signals
Generated
by
EO
D Instruction

(CO-C23)
are
to be transferred to
external
equipment.
These
signals
are:
a.
@)
b.
~
(Buffer Control Mode)
c.
Q
(I/O
Control Mode)
d.
~
(System Control Mode)
The
signals,
@,
@'
and~,
indicate
to
the
external
system
which
EOD mode
is
currently
being
executed.
Eod
is
generated
by
all
EOD instructions
and
is
true during
periods
T7
-
Tr
(1. 4 fJsec). This
Eod
pulse
is
inhibited
dur-
ing
time-share
operations
and
during
the
interlace
loading
sequence.
The @
and@
signals
are
derived
from
the
EOD
instruction
according
to
the
configuration
of
bits C 1, C 10,
C11,
and
C 17.
DACC
Signal E F
~
Cl
C17
Cl0
Cll
Cl
C17
Cl0
Cll
~
-
Cl
C17
Cl0
Cll
Cl
C17
Cl0
Cl1
Q
.!::L
@
Cl
C17
Cl0
Cll
C1
C17
Cl0
Cll
~
Cl
C17 C10
Cll
C1
C17
C10
Cll
Because C 17
and
C
17
are
included
in
the
~
and
Ci2!)
terms,
external
recognition
of
C
17
and
C
17
is
not required.
@
is
inhibited
during
the
interlace
loading
sequence.
® signal
is
derived
from
the
EOD instruction
according
to bits
C9,
C10,
and
Cll.
® =
C9
C10
Cll
PARALLEL
OUTPUT
(POT)
The POT instruction provides a means
of
direct
parallel
transfer
of
up to 24 bits from memory to
an
I/O
channel
or
external
device
via
the
C register of
the
processor. Each
word transfer
is
under
direct
program
control.
The POT
instruction must be
preceded
by
an
EOM instruction to
select
the
desired
device.
During a POT instruction,
the
computer
accesses
the
word to be transferred from a
locati~n
of
memory
determined
by
the
effective
address
of
the
instruc-
tion.
The computer then proceeds to a
wait
phase
and
holds
the
word
to
be transferred in
the
C register.
The
wait
phase consists
of
an integral number
of
computer
cycles
(1.75
fJsec
each).
During
the
wait
phase,
the
C
register
output
lines CO-C23
are
stable
and
contain
the
24-
bit
word to be transferred to
the
external
device.
Upon
receipt
of
a
ready
signal
from
the
external
device
which
is
to
receive
the
data,
the
computer exits from
the
wait
phase
and
continues computation. (The computer will remain in
the
wait
phase,
thereby
suspending
computation,
until
it
is
reieased
by
the
ready
signai from
the
external
device).
if
the
device
was
ready
before
the
computer
entered
the
wait
phase,
the
computer would spend
only
one
cycle
in
the
wait
phase
and
then resume computation. Thus all POT instruc-
tions spend
at
least
one
computer
cycle
in a
wait
phase.
The POT instruction requires 2 + n
cycles,
[(3.5
fJsec) +
n
(1.75
fJsec)] where n = number
of
wait
phases for
execution.
POT
Interface
Signals
The following signals
are
available
on POT connectors
pro-
vided
with
each
DACC
and
TMCC. See figure
2-3.
The
ready
signal suppl
ied
by
the
external
device
is
designated
CRt).
This
signal,
when low
(Ov)
indicates
that
the
unit
is
ready,
and
when high
{+8v}
that
the
unit
is
not ready. The
status
of
this
ready
signal
is
tested
once
every
machine
cycle
during
the
wait
phase. {The
actual
sampl ing time
is
T7-T3}. The
ready
signal must be
at
ground level for
at
I
east
one
computer
cyc
Ie
(1.75
fJsec)
after
the
start
of
the
POT
wait
phase to ensure
acknowledgment
by
the
central
processor. The
wait
phase terminates
at
the
completion of
that
machine
cycle
during
which
the
unit
ready
signal was
acknowledged.
The following signals
are
generated
by
a
POT
instruction:
a.
~
-This signal
is
true during
the
entire
wait
phase
of
the
0struction,
and
is
false
at
all
other
times. Pot 1
being
true
indicates
to
the
external
device
that
the
C register
output
lines.
are
stabl~contain
the
24-bit
word to be
trans-
ferred.
~
going false
indicates
to the
external
device
that
the
computer has
acknowl-
edged
the
ready
signal
and
has
exited
from
the
wait
phase.
b.
~
-This signal
is
true from T5-Tl
of
every
machine
cycle
during
the
POT
wait
phase,
and
is
false
at
all
other
times.
<f~V
may thus be used
as a strobe
by
the
external
device
to strobe the C
register
o,utput lines
(@)
-
@}.
If
a
time-
share
operation
occurs during
the
wai~sf>
the
~
signal will remain
true,
but
Pot 2 will
be
inhibited.
At
the
completion
of
the
time(stf3.
operation,
depending
upon
the
condition
of
Rt
,
at
least
one
more
cycle
of
wait
phase wi
II
occur.
The following
three
signals
are
also
generated
by both
the
TMCC's
and
the
DACe's,
and
are
derived
from
the
pulse
counters in
the
communication
channel.
These timing
sig-
nals may
be
used to
clock
Eom, Sys, Pot,
etc.,
in
an
external
device.
a.
C§9I)-
Thissignal
is
true from
T5
through
TO
of
every
computer
cyc
Ie,
and
is
fa
Ise
at
a
II
othertimes.
2-3

Time
,..
....
I
..
~---------
POT
WAIT
PHASE----irl
-------~
..
I
Signal I0I
RIP
18
I
71
61
51
41
31
2
11
I0I
RIP
I8I
716
151
413
12
11
I
01
RIP
I
H8
I
71
6
15
14 I3
12
I1I0 I
RIP
1
____
~--------------------------~l~~------------~L
---I~~I----
®
l~,---
__
_
@ through
WI///JJ//hC::
11
Wllh
@tlIIII/IIIIc=CRe
g
isterStable---------------.a...l"'"l---------,...-.IYlJJ4
~I~
-----I~~
I
L
900561A.23
Figure
2-3.
Signals
Generated
by
POT
Instruction
b.
C~-
This signal is true from
T6
through
T3
of
every
computer cycIe, and
is
false
at
aIrothertimes.
This signal
may
be used during the POT
wait
phase
to
indicate
to
the
external
device
the time period
during which
the
ready
lineC[)wi
II
be
tested.
c.
@)-
This signal
is
true from
T7
through
T4
of
every
computer
cycle,
and
is
false
at
all
othertimes.
PARALLEL
INPUT
(PIN)
The PIN instruction provides a means of
direct
parallel
transfer
of
up to 24 bits of
data
from
an
external
device
into
memory
via
the C register of the computer. Each word
transferred
is
under
direct
program control. The PIN instruc-
tion must
be
preceded
by an EOM instruction
to
select
the
desired
device.
During the
execution
of
a PIN instruction
the computer proceeds to a
wait
phase almost
identical
to
that
of a POT instruction.
The
wait
phase consists of an
integral number of
computer@).
The
C register
is
first
reset,
then
the
input lines (
CdO
-
Cf~D)
are
strobed
into the C register.
This
process
of
resetting
the
C register
and
of
then strobing the
data
repeats
once
every
machine
cyc
Ie
during
the
wait
phase of a
PI
N instruction.
When the ready signal
is
received
(C]I)going
to ground
level) from
the
externa
I
device,
the computer exits
from
the
'.'/Oit
phase and continues computation.
The
wait
phase
terminates
at
the
completion of
that
machine
cycle
during
which the
external
ready signal was
acknowledged
by
the
computer;
therefore,
a PIN instruction must go through
at
least one
wait
phase. The requirements for the ready signal
are
identical
to
those for a POT instruction. Thus, a PIN
2-4
instruction requires 3 + n
cycles
US.
25
!-,sec)
+
nO.
75!-,secil
where
n =number
of
wait
phases for
execution.
NOTE
The
C register input lines
(C~O)-
~~D)
are
inverted before
they
are
strobed into the C register; thus,
the
C register wi
II
receive
the
ones com-
r.lement of the
data
impressed on
CC~)
-
~~D.
PIN
Interface
Signals
Two
si
gna
Is
are
generated
by a
PI
N instruction. See
fi
gure
2-4.
These signals
generated
in
the
computer
are
available
at
the
PIN connectors provided with
each
DACC and TMCC.
a.
® -This signal
is
true from
T7
through
TO
of
every
computer
cycle
during a PIN
wait
phase
and
is
false
at
all
other
times. ® indicates to
the
external
device
that
the
C register input lines
are
being strobed into the C register and therefore
must
be
stab
Ie
at
th
is
time.
b.
cRTI)-
This signal
is
a
1.4
f-lsec
ground level
signal
generated
when
the
PIN instruction exits
from the
wait
phase.
C~)
going to ground
indicates to the
externa
I system
that
the CPU has
acknowledged
the
ready
signal by
exiting
from
the
wait
phase
and
has
accepted
24
bits
of
data.
(CETI)
is
positive in its
quiescent
condition).

Time •
I- PIN
WATT
PHASE
-I
Signal
101
RIPI8171615t4131211101
RIP
1817161514/312111
aiR!
P!l~8171615\
41
312111
01
RI
P!
817161514131211101
RI
PI
u
------------------------------~l~2----
@through
@
@)
l I
~~
L
l~
I 900561A.24
Figure
2-4.
Signals
Generated
by
PIN Instruction
If a
time-share
operation
occurs during
the
wait
phase, the
CEVsignal
will
be
inhibited.
At
the
completion of
the
time-share
operation,
depending
on
the
condition
ofCE[),
at
least
one
more
cyc
Ie
of
wait
phase
wi
II
occur.
If
a
time-share
operation
occurs during
the
cycle
after
the
last
wait
phase
cycle,CRti)
will
be
inhibited
until
the
completion
of
the
time-share
operation.
SDS
925
SPECIAL
I/O
OPERATIONS
The 925 Computer includes two
additional
I/O
instructions,
Block
Parallel
Output
(BPO) and Block Parallel Input
(BPI).
These instructions
are
block
transfer versions
of
POT
and
PIN instructions. The transmission of
data
is
initiated
by
performing
the
following programming steps:
a.
Load
the
number
of
words to be transferred, minus
one,
into
the
A register.
b.
Alert
the
external
unit
by
means
of
an
EOM
instruction.
c.
Start
the
transfer with a BPO or
BPI
instruction.
The computer now enters a
wait
and
transfer phase. If
the
external
unit
is
ready,
information
will
be
transferred
at
a
rate
of one word
each
computer
cycle
(1.
75
I-Isec)
untiI the
word
count
placed
into
the
A register (which
is
counted
down
by
one
each
I/O
cycle)
or unti I
the
externa
I unit
supplied
the
terminate
signalm.
Input
(BPI)
The
computer remains in
the
wait
and
data
transfer phase
unti I
ready
detector
f(E)p,
Rf,
is
set
by the
externally
supplied
ready
signal
Rt.
See figure
2-5.
sRf
rRf
(J02
05
06
Tp)
Rt
(J02
05
06
Tp)
Rt
The computer supplies a ® signal
each
time a word
is
being
transferred into
the
C register.
Pin =
(J02
06)
(T7-
TO)
Ts
02
Rf
Th
is
process continues untiI
the
word count reaches
zero
or
unti I
the
external
unit supplies a ground to the
terminate
signal
lineC]!).
Either
condition
causes the computer to
exit
from
the
wait
and
data
transfer phase
at
pulse time
Tp.
The computer now generates
the
transfer complete
si
gna I
([IT).
Rti
=
(J04
01
04
06)
Ts
(T7-
Tr)
If
the
external
unit
cannot
(Jf.~
information
each
1.75
I-Isec,
the
ready
signal line
Rt
,
can
be
used as a
clock
to
synchronize
the operations.
Output
(BPO)
The computer
enters
the
wait
and
data
transfer phase and
supplies
the
Pot1
signal. The
external
unit must supply
the
ctl!1>gna',
if!
,before
the computer can generate
the
Pot2
signal.
The
@signal
sets
the
ready
detector
2-5

Time
..
Signal
""'"I·r-----WAIT
-AND
DATA
TRANSFER
PHASE-----I
..
~I
10lRIPl817161S1413121110lRIPI817161S14131211
101R~1817161S14131211101RIP1817161S14131211101RIPI
Rf
l~~
--------------~L
®
@through
<@
®
----------------------------~H~---------
®
--------------------------~l~l---------------
r-
",,--------,'
1&--
_________________________________________
900_56_1A_"_25
........
Figure
2-S.
Signals
Generated
by 92S
BPI
Instruction
flip-flop
Rf
in
the
same manner as for
block
parallel
inputs.
See
fi
gure
2-6.
sRf
~2
OS
06
Tp)
Rt
rRf
Q~2)
~2
OS
06
Tp)
Rt
Pot1
(TS-
Tl) Tsr
Rf
OS
The
cr;:-2)
signal
can
be
used by
the
external
unit
to
strobe
the
C register outputs. This process continues unti I
the word count reaches
zero
or the
external
unit supplies a
ground on
the
terminate signal
line<]L).
C!!)is
recog-
nized
at
pulse time Tp, and therefore must
be
low
for
at
least one
cycle
to ensure acknowledgement. Either
condi-
tion causes
the
computer to
exit
from
the
wait
and
data
transfer phase
at
pulse time Tp.
As
in
block
input operations the
ready
signal line, CEi),
can
be
used as a
clock
to
synchronize
the
block
parallel
output
operation.
SliP
IF
SIGNAL
NOT
SET
(SIS)
The
SKS
instruction provides a means of program sensing both
internal and
external
conditions.
This
instruction operates
in four basic modes
that
are
program
selectable
by
the
setting
of
two bits (C10
and
Cll)
within
the
SKS
instruction format.
2-6
C10
o
o
1
1
.Q.1
o
1
o
1
Mode
Special
Internal Test
Channel/Device
Test
InternaI Test
System Test
Only
channel/device
test
and
system
test
are
available
to
the
external
equipment,
and
wi
II
be
described.
The
SKS
system
test
mode
is
divided
into two submodes
(system
test
externa
I,
and
system
test
internaI)
by
gating
bit
9 with bits 10
and
11. This
is
necessary if the two sub-
modes
of
the EOM system control
are
uti
lized.
Refer
to
paragraph on system control EOM.
C1
C9 C10
Cll
x o S
KS
System Test (Externa
I)
x
SKS
System Test (Internal)
The
SKS
instruction tests the status of signals supplied
to
the
computer by peripheraI devices or system equipment.
If
the
signal
is
low,
the
next instruction in sequence
is
skipped.
If
this signal
is
positive, the program does not skip
but
con-
tinues
in
its normal
sequence.
C1
must always
be
included
in the
decoding
circuitry:
since
the term
C1
separates the
Data Multiplex System (C1) from
other
I/O
units (C1).
The
SKS
instruction requires two computer
cycles
(3. S
I-Isec)
if
no skip occurs,
and
three
cycles
(S.2S
I-Isec)
if a skip does
occur.
SKS
I.terface
Sigaais
The following signals necessary to implement
the
SKS
tests
are
available
at
the
I/O
connectors on
each
TMCC
and
DACC. See figure
2-7.

Time
..
Signal
IOIRIPIS1716151413121110IRIPIS1716151413121
1iOlRIPISI716151413121
1iOlRIPISI7161514131211
IOIRIPI
~-----------------------~H~------------~
__________
__
--------------~H~------------------~
Rf
n------------,l
@through@
S
Reg
ister
Stabl;
~~\U
__________
JU.LLLU.LLLU.I.U.l.LI.U.l.Lu.u.r..u.u.r..W/.U.
--------------------------~n~--------
900561A.26
Figure 2-6. Signals Generated
by
925
SPO
Instruction
Time
•
1.-
..
1----------
SKS
Instruction-----------.-ja,
Signal
IlloIRlplsI71615141312\1\O\R\plsI716\514\31211IoIRlpl
Skss
(C9 true) L
or
Skss
(C9 false) I L
@through<§)
_~"I---------C
Register
Stable--------.-..t~~
Status of ® or
@Tested
-------------------------~
900561A.27
Figure 2-7. Signals Generated
by
SKS
Instruction
2-7

a.
2-8
~-
This signal
is
generated
by
each
SKS
instructioc~0dicates
that
the
C register outputs
(((T),
C9
through@D)
are
stable
and
m~
decoded
by external equipment prior to
supplying the computer with
the
test signal. The
external
eguipment should
decode
all
available
bits
(@),
UD
through
@V)
since
some
configurations have been
pre-assigned
for use with
standard equipment such as
data
multiplexing sys-
tems, message switching,
etc.
The
~
signal
is
true
from
T6
-
Tr
of
the
second
cycle
of
the
SKS
instruction if
bit
C9
is
true.
If
bit
C9
is
false,
~
is
true
from
T7
of
the
first
cycle
through
Tr
of
the
second
cycle.
~
is
inhibited
during a
time-share
operation.
If
a
time-share
operation
occurs during
either
of
the
first two
cycles
of
an
SKS
instruction, both
cycles will
be
repeated
at
the
completion
of
the
time-share
operation.
b.
cJ:;)-
This si nal
is
generated
by peripheral
devices when Skss
is
true during
the
SKS
instruc-
tion,
channel
device
mode. The C register bits
Cl,
C9,
Cl0,
and
Cll
are
decoded
internally
and
need
not be
decoded
externally
to determine
channel/device
mode. Bits C12 through C23 must
be
decoded
to
select
the
desired
device.
A
zero
volt
condition
on
this Iine causes
the
computer to
skip
the
next
instruction in
sequence.
c.
CS!5)-
This signal
®i)ated
by
external sys-
tem equipment when
Skss
is
true during
the
SKS
instruction, system mode. The C register bits C1
and C9 must be
decoded
externally
to determine
system
test
external
mode with bits C12 through
C23 providing
the
desired
single-bit
input address.

SECTION
III
INPUT/OUTPUT
CHANNEL
DESCRIPTION
GENERAL
This
section
describes the
optional
features, timing
consid-
erations,
and
interfacing
requirements of
the
several
input/
output
channels
available
to
the
SDS
925/930/9300
Computers -
the
TMCC, DACC, DMS, MIC,
and
Priority
Interrupts.
TIME
MULTIPLEXED
COMMUNICATJON
CHANNEL
(TMCC)
The TMCC
is
a time
multiplexed
input/output
channe
I for
communication
between
a
peripheral
device
and
the
SDS
925/930/9300
Computers. Its
operation
is
designated
"time
multiplexed"
because
it
gains
access
to
the
computer memory
through
the
same path uti
lized
by the computer
and
must
therefore momentari
Iy
interrupt computation to store or
obtain
a word
of
information.
Up
to four
TMCCs
may
be
connected
to one computer and
all
may be
active
simulta-
neously. Since
their
operation
is
time
multiplexed,
however,
only
one
channel
at
a time
can
communicate
with
the
com-
puter
memory.
TMCC has two registers for
data
storage which provide
the
means to assemble input
characters
into words or
to
disassem-
ble
words into output
characters.
The
TMCC communicates
with
the
computer
by
means of a
24-bit
Word Assembly
Register
0!YAR)
which transfers words
between
the
TMCC
and
the
computer's C register. The TMCC communicates with
exfernal
systems by means of
the
bidirectional
Single
Char-
acter
Register
(SCR)
using
either
a
6-,
12-,
or
24-bit
char-
acter
format plus a
parity
bit.
See figure
3-1.
The
character
size
depends on
the
optional
registers
that
may be
instalied. The number of
characters
per
word
is
under pro-
gram control
but
is
limited
to
a maximum of four
6-bit
characters,
two
12-bit
characters,
or
one
24-b
it
character.
Mode of transfer
is
serial
by
character,
parallel
by
bit.
A
TMCC
having
the
larger
character-length
options may
be
switched
from
one
size
to
another
under control
of
the
external
system. The
G2D
iS
selected
by
activating
one
of
the
control lines, Wx12 or
GY§"D.
A
particular
device
can
activate
only
one
of these lines; if none
is
activated,
the
TMCC assumes
the
6-bit
character
format.
The
rate
of information transfer
is
determined
by
the
clock
signal
CE~)
from
the
external
device.
For both input
and
output,
the TMCC
will
slave
itself to
the
frequency, of
the
device's
clock.
Information may be input or
output
by
executing
an
instruc-
tion for
each
word. The instruction may be given in
advance
of
the
time
it
is
needed,
in which case
the
com-
puter
remains
idle
until
the
channel
is
ready.
Or
the
com-
puter
interrupt
system may
be
used so
that
the
channe
I
can
call
for an instruction when
it
is
ready. This allows
the
computer
to
continue
with
other
computations when not
actually
engaged
in the
I/O
process.
Unit Address Codes
Sixty-four
unit address codes
are
available
to
the
TMCC.
Refer to
table
3-1.
Two
of these codes (00
and
40)
are
reserved for
channel
disconnect.
While
the
code
40
will
disconnect
the
channel
it
is
not generalIy used for this
pur-
pose
since
it
does not reset W9
flip-flop
as
it
disconnects.
The remaining 62 addresses
are
divided
in~}l
input
device
codes
0/'19),
and
31
output
device
codes
0!Y9).
When choos-
ing a
device
code
for equipment
other
than those listed in
tab
Ie
3-1,
care
must be
taken
that
no
code
reserved for
any
magnetic
tape
operation
or for
paper
tape
input
be
used.
If
Wl1
is
true (magnetic
tape)
the
buffer will modify the normal
terminate
condition.
If
a
paper
tape
input
code
is
used, an
all
zero
character
(Rwl
-
Rwp
=O)will
cause a gap
indica-
ti on to the buffer.
Interlace
An
optional
interlace
feature may
be
installed
in the
TMCC
for
either
the
W or Y channels to
facilitate
input/output
operations
with
fewer
instructions. The
interlace
logic
allows a program to
tell
the TMCC
how
many words
are
to
be
transferred
and
the
memory location of
the
first word.
Then, with
no
further instructions, the TMCC will assemble
or disassemble
the
number of words
specified
and
call
on the
computer
each
time it
is
ready to transfer a word to or from
memory. Thus,
the
I/O
process may
be
interlaced
with
computation
or
with simi lar
I/O
operations on
other
channels.
Two
additional
registers
are
provided with
the
interlace
feature:
a.
Word
Counter
- a
15-b
it
counter
used
to
store
the
number
of
words to
be
transferred during
the
inter-
lace
I/O
operation.
With
each
word transfer, one
is
subtracted
from
the
number in the counter.
b. Address
Counter
- a
15-bit
register used
to
store
the
address of the memory location
currently
being
accessed.
Each time a word
is
taken
from or sent
to memory, a one
is
added
to the number in this
register.
Input
A
brief
description
of
a
non-interlaced
process follows. The
TMCC
is
initialized
by an EOM instruction, buffer control
3-1

3-2
INTERFACE
I
@
@
I
I
I
I
I
I
I
I
I
I
@
I
@-
Zw61
18
Optional I
D.ota
Lines
I
I
@@I
@
14
@ I
I
I
Clock I
I
I
I
Input or Output I
.....
r
I
....
I'""
I
Unit I
Address
I
lines
(5)
I
I
1
.....
r'"
TMCC
W(A),
Y(B),
C,
or D
SCR
WAR
I
W4
I
Wf
CENTRAL
PROCESSOR
CO
}
To
Memory
Modules
~--+-
..
C23
I
..
Full
or
Empty
·1
Parity I
~
~~
t "0" C
I Register
W5
W7
~
I C15
......-
I
..
W8
....
I C16
r'
W6
......-
I
1 C17
I
W9
....
I C18
......-
1
W10
-I C19
...
I
I
UAR
Wll
....
C20
....
I
.-
I
W12
....
I
C21
W13
,
......
C22
...
I
W14
....
I C23
....
I
900561A.31
Figure 3-1.
TMCC
Simpl
ified
Block
Diagram

Table
3-1.
Unit Address Codes
Code Unit
00 Disconnect
01
Type Input No. 1
02 Type Input No. 2
03 Type Input No. 3
04 Paper Tape Input No. 1
05 Paper Tape Input No. 2
06 Card Reader Input No. 1
07
Card Reader Input No. 2
10
Magnetic
Tape Input No. 0
11
Magnetic
Tape Input
No.
1
12 Magnetic Tape Input No. 2
13
Magnetic Tape Input
No.
3
14
Magnetic
Tape Input No. 4
15
Magnetic Tape Input
No.
5
16
Magnetic
Tape Input
No.
6
17
Magnetic
Tape Input No. 7
20
--
21
--
22
--
23
--
24
--
25
--
26 Disc
Fi
Ie
or
Auxi liary
Drum
Input No.
27
Disc File
or
Auxiliary
Drum
Input No.
30 Scan
Magnetic
Tape No. 0
31
Scan Magnetic Tape No. 1
32 Scan Magnetic Tape No. 2
33 Scan
Magnetic
Tape
No.3
34
Scan
Magnetic
Tape No. 4
35 Scan
Magnetic
Tape
No.5
36 Scan Magnetic Tape No. 6
37
Scan Magnetic Tape
No.
7
mode. This operation also
places
the address
code
for
the
external
device
into
the
Unit Address Register
(UAR)
and
fi
lis the
character
counter
0N7,
W8) with
the
number of
characters
per word count. Each
external
device
decodes
the
UAR
outputs@through
@ and prepares to
1
2
send information to the TMCC when addressed. The unit
address
lines@through
@
are
false when
the
TMCC
is
inactive.
Once
addressed, the
external
device
generates a
clock
signal ®
each
time a
character
is
ready to
be
transferred into the TMCC
via
the
data
input
lines @ through ®
and@.
See figure
3-2.
These
data
lines
are
inverted
before
they
are
strobed into
the
character
register, thus the ones complement
of
the
data
placed
on ® through ® will be
received.
sRw
1 =
W9
W6
W5
Zw
1 +- - -
sRw24 =
W9
W6
W5
Zw24 +- - -
Code Unit
40
41
Type
Output
No.
1
42 Type
Output
No. 2
43 Type
Output
No.
3
44
Paper Tape Punch
Output
No. 1
45 Paper Tape Punch
Output
No. 2
46
Card Punch
Output
No. 1
47
Card Punch
Output
No. 2
50
Magnetic
Tape
Output
No. 0
51
Magnetic
Tape
Output
No.
1
52
Magnetic
Tape
Output
No.
2
53
Magnetic
Tape
Output
No. 3
54
Magnetic
Tape
Output
No. 4
55
Magnetic
Tape
Output
No. 5
56
Magnetic
Tape
Output
No.
6
57
Magnetic
Tape
Output
No. 7
60
High-Speed Printer
Output
No.
1
61
Hi
gh-
Speed
Pri
nter
Output
No. 2
62
--
63
--
64
Incremental Plotter
Output
No.
1
65 Incremental Plotter Output No. 2
66 Disc
Fi
Ie
or Auxi liary
Drum
Output
No. 1
67
Disc File or Auxiliary
Drum
Output
No. 2
70
Magnetic
Tape Erase
No.
0
71
Magnetic
Tape Erase No. 1
72
Magnetic
Tape Erase
No.
2
73
Magnetic
Tape Erase No. 3
74
Magnetic
Tape Erase No. 4
75
Magnetic
Tape Erase
No.5
76
Magnetic
Tape Erase No. 6
77
Magnetic
Tape Erase No. 7
The input
data
is
strobed into the
si
ngle
character
register
until
flip-flop
W5
is
set. It wi
II
be
shown
later
that
W5
wi
II
set
after
the input
clock
signal ® has
been
removed.
The TMCC monitors the @ input line,
checking
for
parity
errors
after
information
is
strobed into the single
character
register.
If
an
error
is
detected,
the
error
indi-
cator
flip-flop,
We,
is
set.
The
status of this
flip-flop
can
be
tested
by
the program. If the external
device
does not
generate
the
parity
bit
(odd
parity
is
used),
the
parity
chec~ature
can
be
inhibited
by
making the
interface
line
~
low during
data
transfer.
The
quiescent
state
of
the
signal
clock
@
is
positive.
To
initiate
a
data
transfer, ® must first go
low
to set
c lock
detector
flip-flop
W6.
sW6
W5
tcw
T8
3-3

""---/
Ecw
I
I~
__
_
W4 ______________
~r_l~
______________
~Il~
____
_
Wf
WIM
@o-
Schmitt
~
Ecw
Trigger
~
Ecw
u
900561A.32
Figure
3-2.
Input
Timing
Characteristics
Asynchronous
Mode
After
W6
is
set,
the
character
register
is
fi
lied
--
sRw
1 = Zw1 W9 W5
W6
+ - - -
sRw24 =
Zw24
W9 W5
W6
+- - -
and
the
precess
detector
flip-flop
W5
is
set
after
®
goes
high.
sW5 = W5 W6 Ecw
TO
The
contents
of
the
SCR
are
now
ready
to
be
shifted
into
the
word assembly
register
under
control
of
flip-flop
W4
providing
Wf
is
true.
sW4
=
W5
Wf
T8
Wg
The Wf
signal
will
be
false
if
the
WAR
is
not
able
to
accept
data
(the
computer
has
not
yet
serviced
the
previous
word
in
WAR
because
of
a
higher
priority
channel
requiring
access,
or
because
the
WIM command has not
yet
been
given).
3-4
After
the
shift,
W4, W5, W6
and
the
SCR
are
reset
in
prep-
aration
for
reception
of
the
next
character
from
the
external
device.
rW4
W4
TO
rW5
W4
TO
rW6
W5
TO
rRwl W9 W6 W5 W4
rRw6 =
W9
'1/6
Vv5
W4
Th
is
process
repeats
until
the
proper
number
of
characters
(indicated
by
the
character
count
register)
have
been
shifted
to
the
Word Assembly Register
NVAR).
The IIbuffer fuli
ll
flip-
flop,
Wf,
is
then
reset
to
indicate
to
the
computer
that
a
word has
been
assembled
and
is
ready
for
transfer
to
memory.
This manual suits for next models
2
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