Segger J-Link User manual

A product of SEGGER Microcontroller GmbH & Co. KG
www.segger.com
J-Link / J-Trace
ARM
Software Version V4.26
Manual Rev. 0
Document: UM08001
Date: May 13, 2011
User guide of the JTAG emulators
for ARM Cores

2
J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
Disclaimer
Specifications written in this document are believed to be accurate, but are not guar-
anteed to be entirely free of error. The information in this manual is subject to
change for functional or performance improvements without notice. Please make sure
your manual is the latest edition. While the information herein is assumed to be
accurate, SEGGER Microcontroller GmbH & Co. KG (the manufacturer) assumes no
responsibility for any errors or omissions. The manufacturer makes and you receive
no warranties or conditions, express, implied, statutory or in any communication with
you. The manufacturer specifically disclaims any implied warranty of merchantability
or fitness for a particular purpose.
Copyright notice
You may not extract portions of this manual or modify the PDF file in any way without
the prior written permission of the manufacturer. The software described in this doc-
ument is furnished under a license and may only be used or copied in accordance
with the terms of such a license.
©2011 SEGGER Microcontroller GmbH & Co. KG, Hilden / Germany
Trademarks
Names mentioned in this manual may be trademarks of their respective companies.
Brand and product names are trademarks or registered trademarks of their respec-
tive holders.
Contact address
SEGGER Microcontroller GmbH & Co. KG
In den Weiden 11
D-40721 Hilden
Germany
Tel.[phone]
Fax.[phone]
Email: [e-mail]
Internet: http://www.segger.com
Revisions
This manual describes the J-Link and J-Trace device.
For further information on topics or routines not yet specified, please contact us.
Revision Date By Explanation
V4.26 Rev. 1 110513 KN Chapter "Introduction"
* Section "J-Link / J-Trace models" corrected.
V4.26 Rev. 0 110427 KN Several corrections.
V4.24 Rev. 1 110228 AG
Chapter "Introduction"
* Section "J-Link / J-Trace models" corrected.
Chapter "Device specifics"
* Section "ST Microelectronics" updated.
V4.24 Rev. 0 110216 AG
Chapter "Device specifics"
* Section "Samsung" added.
Chapter "Working with J-Link"
* Section "Reset strategies" updated.
Chapter "Target interfaces and adapters"
* Section "9-pin JTAG/SWD connector" added.

J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
3
V4.23d 110202 AG
Chapter "J-Link and J-Trace related software"
* Section "J-Link software and documentation
package in detail" updated.
Chapter "Introduction"
* Section "Built-in intelligence for
supported CPU-cores" added.
V4.21g 101130 AG
Chapter "Working with J-Link"
* Section "Reset strategies" updated.
Chapter "Device specifics"
* Section "Freescale" updated.
Chapter "Flash download and flash breakpoints
* Section "Supported devices" updated
* Section "Setup for different debuggers
(CFI flash)" updated.
V4.21 101025 AG Chapter "Device specifics"
* Section "Freescale" updated.
V4.20j 101019 AG Chapter "Working with J-Link"
* Section "Reset strategies" updated.
V4.20b 100923 AG Chapter "Working with J-Link"
* Section "Reset strategies" updated.
90 100818 AG
Chapter "Working with J-Link"
* Section "J-Link script files" updated.
* Section "Command strings" upadted.
Chapter "Target interfaces and adapters"
* Section "19-pin JTAG/SWD and Trace
connector" corrected.
Chapter "Setup"
* Section "J-Link configurator added."
89 100630 AG Several corrections.
88 100622 AG Chapter "J-Link and J-Trace related software"
* Section "SWO Analyzer" added.
87 100617 AG Several corrections.
86 100504 AG
Chapter "Introduction"
* Section "J-Link / J-Trace models" updated.
Chapter "Target interfaces and adapters"
* Section "Adapters" updated.
85 100428 AG Chapter "Introduction"
* Section "J-Link / J-Trace models" updated.
84 100324 KN
Chapter "Working with J-Link and J-Trace"
* Several corrections
Chapter Flash download & flash breakpoints
* Section "Supported devices" updated
83 100223 KN Chapter "Introduction"
* Section "J-Link / J-Trace models" updated.
82 100215 AG Chapter "Working with J-Link"
* Section "J-Link script files" added.
81 100202 KN
Chapter "Device Specifics"
* Section "Luminary Micro" updated.
Chapter "Flash download and flash breakpoints"
* Section "Supported devices" updated.
80 100104 KN Chapter "Flash download and flash breakpoints
* Section "Supported devices" updated
79 091201 AG
Chapter "Working with J-Link and J-Trace"
* Section "Reset strategies" updated.
Chapter "Licensing"
* Section "J-Link OEM versions" updated.
Revision Date By Explanation

4
J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
78 091023 AG Chapter "Licensing"
* Section "J-Link OEM versions" updated.
77 090910 AG Chapter "Introduction"
* Section "J-Link / J-Trace models" updated.
76 090828 KN
Chapter "Introduction"
* Section" Specifications" updated
* Section "Hardware versions" updated
* Section "Common features of the J-Link product
family" updated
Chapter "Target interfaces and adapters"
* Section "5 Volt adapter" updated
75 090729 AG
Chapter "Introduction"
* Section "J-Link / J-Trace models" updated.
Chapter "Working with J-Link and J-Trace"
* Section "SWD interface" updated.
74 090722 KN
Chapter "Introduction"
* Section "Supported IDEs" added
* Section "Supported CPU cores" updated
* Section "Model comparison chart" renamed to
"Model comparison"
* Section "J-Link bundle comparison chart"
removed
73 090701 KN
Chapter "Introduction"
* Section "J-Link and J-Trace models" added
* Sections "Model comparison chart" &
"J-Link bundle comparison chart"added
Chapter "J-Link and J-Trace models" removed
Chapter "Hardware" renamed to
"Target interfaces & adapters"
* Section "JTAG Isolator" added
Chapter "Target interfaces and adapters"
* Section "Target board design" updated
Several corrections
72 090618 AG
Chapter "Working with J-Link"
* Section "J-Link control panel" updated.
Chapter "Flash download and flash breakpoints"
* Section "Supported devices" updated.
Chapter "Device specifics"
* Section "NXP" updated.
71 090616 AG Chapter "Device specifics"
* Section "NXP" updated.
70 090605 AG
Chapter "Introduction"
* Section "Common features of the J-Link
product family" updated.
69 090515 AG
Chapter "Working with J-Link"
* Section "Reset strategies" updated.
* Section "Indicators" updated.
Chapter "Flash download and flash breakpoints"
* Section "Supported devices" updated.
68 090428 AG
Chapter "J-Link and J-Trace related software"
* Section "J-Link STM32 Commander" added.
Chapter "Working with J-Link"
* Section "Reset strategies" updated.
67 090402 AG Chapter "Working with J-Link"
* Section "Reset strategies" updated.
Revision Date By Explanation

J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
5
66 090327 AG
Chapter "Background information"
* Section "Embedded Trace Macrocell (ETM)"
updated.
Chapter "J-Link and J-Trace related software"
* Section "Dedicated flash programming
utilities for J-Link" updated.
65 090320 AG Several changes in the manual structure.
64 090313 AG Chapter "Working with J-Link"
* Section "Indicators" added.
63 090212 AG
Chapter "Hardware"
* Several corrections.
* Section "Hardware Versions" Version 8.0 added.
62 090211 AG
Chapter "Working with J-Link and J-Trace"
* Section "Reset strategies" updated.
Chapter J-Link and J-Trace related software
* Section "J-Link STR91x Commander
(Command line tool)" updated.
Chapter "Device specifics"
* Section "ST Microelectronics" updated.
Chapter "Hardware" updated.
61 090120 TQ Chapter "Working with J-Link"
* Section "Cortex-M3 specific reset strategies"
60 090114 AG Chapter "Working with J-Link"
* Section "Cortex-M3 specific reset strategies"
59 090108 KN
Chapter Hardware
* Section "Target board design for JTAG"
updated.
* Section "Target board design for SWD" added.
58 090105 AG
Chapter "Working with J-Link Pro"
* Section "Connecting J-Link Pro the first time"
updated.
57 081222 AG
Chapter "Working with J-Link Pro"
* Section "Introduction" updated.
* Section "Configuring J-Link Pro
via web interface" updated.
Chapter "Introduction"
* Section "J-Link Pro overview" updated.
56 081219 AG
Chapter "Working with J-Link Pro"
* Section "FAQs" added.
Chapter "Support and FAQs"
* Section "Frequently Asked Questions" updated.
55 081218 AG Chapter "Hardware" updated.
54 081217 AG Chapter "Working with J-Link and J-Trace"
* Section "Command strings" updated.
53 081216 AG Chapter "Working with J-Link Pro" updated.
52 081212 AG
Chapter "Working with J-Link Pro" added.
Chapter "Licensing"
* Section "Original SEGGER products" updated.
51 081202 KN Several corrections.
50 081030 AG Chapter "Flash download and flash breakpoints"
* Section "Supported devices" corrected.
49 081029 AG Several corrections.
48 080916 AG
Chapter "Working with J-Link and J-Trace"
* Section "Connecting multiple J-Links /
J-Traces to your PC" updated.
47 080910 AG Chapter "Licensing" updated.
Revision Date By Explanation

6
J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
46 080904 AG
Chapter "Licensing" added.
Chapter "Hardware"
Section "J-Link OEM versions" moved to chapter
"Licensing"
45 080902 AG
Chapter "Hardware"
Section "JTAG+Trace connector" JTAG+Trace
connector pinout corrected.
Section "J-Link OEM versions" updated.
44 080827 AG
Chapter "J-Link control panel" moved to chapter
"Working with J-Link".
Several corrections.
43 080826 AG Chapter "Flash download and flash breakpoints"
Section "Supported devices" updated.
42 080820 AG Chapter "Flash download and flash breakpoints"
Section "Supported devices" updated.
41 080811 AG
Chapter "Flash download and flash breakpoints"
updated.
Chapter "Flash download and flash breakpoints",
section "Supported devices" updated.
40 080630 AG
Chapter "Flash download and flash breakpoints"
updated.
Chapter "J-Link status window" renamed to "J-Link
control panel"
Various corrections.
39 080627 AG
Chapter "Flash download and flash breakpoints"
Section "Licensing" updated.
Section "Using flash download and flash
breakpoints with different debuggers" updated.
Chapter "J-Link status window" added.
38 080618 AG
Chapter "Support and FAQs"
Section "Frequently Asked Questions" updated
Chapter "Reset strategies"
Section "Cortex-M3 specific reset strategies"
updated.
37 080617 AG
Chapter "Reset strategies"
Section "Cortex-M3 specific reset strategies"
updated.
36 080530 AG
Chapter "Hardware"
Section "Differences between different versions"
updated.
Chapter "Working with J-Link and J-Trace"
Section "Cortex-M3 specific reset strategies"
added.
35 080215 AG
Chapter "J-Link and J-Trace related software"
Section "J-Link software and documentation
package in detail" updated.
34 080212 AG
Chapter "J-Link and J-Trace related software"
Section "J-Link TCP/IP Server (Remote J-Link /
J-Trace use)" updated.
Chapter "Working with J-Link and J-Trace"
Section "Command strings" updated.
Chapter "Flash download and flash breakpoints"
Section "Introduction" updated.
Section "Licensing" updated.
Section "Using flash download and flash
breakpoints with different debuggers" updated.
Revision Date By Explanation

J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
7
33 080207 AG
Chapter "Flash download and flash breakpoints"
added
Chapter "Device specifics:"
Section "ATMEL - AT91SAM7 - Recommended init
sequence" added.
32 0080129 SK
Chapter "Device specifics":
Section "NXP - LPC - Fast GPIO bug" list of
device enhanced.
31 0080103 SK Chapter "Device specifics":
Section "NXP - LPC - Fast GPIO bug" updated.
30 071211 AG
Chapter "Device specifics":
Section "Analog Devices" updated.
Section "ATMEL" updated.
Section "Freescale" added.
Section "Luminary Micro" added.
Section "NXP" updated.
Section "OKI" added.
Section "ST Microelectronics" updated.
Section "Texas Instruments" updated.
Chapter "Related software":
Section "J-Link STR91x Commander" updated
29 070912 SK Chapter "Hardware", section "Target board design"
updated.
28 070912 SK
Chapter "Related software":
Section "J-LinkSTR91x Commander" added.
Chapter "Device specifics":
Section "ST Microelectronics" added.
Section "Texas Instruments" added.
Subsection "AT91SAM9" added.
28 070912 AG Chapter "Working with J-Link/J-Trace":
Section "Command strings" updated.
27 070827 TQ Chapter "Working with J-Link/J-Trace":
Section "Command strings" updated.
26 070710 SK
Chapter "Introduction":
Section "Features of J-Link" updated.
Chapter "Background Information":
Section "Embedded Trace Macrocell" added.
Section "Embedded Trace Buffer" added.
25 070516 SK
Chapter "Working with J-Link/J-Trace":
Section "Reset strategies in detail"
- "Software, for Analog Devices ADuC7xxx
MCUs" updated
- "Software, for ATMEL AT91SAM7 MCUs"
added.
Chapter "Device specifics"
Section "Analog Devices" added.
Section "ATMEL" added.
24 070323 SK
Chapter "Setup":
"Uninstalling the J-Link driver" updated.
"Supported ARM cores" updated.
23 070320 SK Chapter "Hardware":
"Using the JTAG connector with SWD" updated.
22 070316 SK Chapter "Hardware":
"Using the JTAG connector with SWD" added.
21 070312 SK
Chapter "Hardware":
"Differences between different versions"
supplemented.
Revision Date By Explanation

8
J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
20 070307 SK Chapter "J-Link / J-Trace related software":
"J-Link GDB Server" licensing updated.
19 070226 SK
Chapter "J-Link / J-Trace related software" updated
and reorganized.
Chapter "Hardware"
"List of OEM products" updated
18 070221 SK Chapter "Device specifics" added
Subchapter "Command strings" added
17 070131 SK
Chapter "Hardware":
"Version 5.3": Current limits added
"Version 5.4" added
Chapter "Setup":
"Installating the J-Link USB driver" removed.
"Installing the J-Link software and documentation
pack" added.
Subchapter "List of OEM products" updated.
"OS support" updated
16 061222 SK Chapter "Preface": "Company description" added.
J-Link picture changed.
15 060914 OO
Subchapter 1.5.1: Added target supply voltage and
target supply current to specifications.
Subchapter 5.2.1: Pictures of ways to connect J-
Trace.
14 060818 TQ Subchapter 4.7 "Using DCC for memory reads"
added.
13 060711 OO Subchapter 5.2.2: Corrected JTAG+Trace connec-
tor pinout table.
12 060628 OO Subchapter 4.1: Added ARM966E-S to List of sup-
ported ARM cores.
11 060607 SK Subchapter 5.5.2.2 changed.
Subchapter 5.5.2.3 added.
10 060526 SK
ARM9 download speed updated.
Subchapter 8.2.1: Screenshot "Start sequence"
updated.
Subchapter 8.2.2 "ID sequence" removed.
Chapter "Support" and "FAQ" merged.
Various improvements
9 060324 OO
Chapter "Literature and references" added.
Chapter "Hardware":
Added common information trace signals.
Added timing diagram for trace.
Chapter "Designing the target board for trace"
added.
8 060117 OO Chapter "Related Software": Added JLinkARM.dll.
Screenshots updated.
7 051208 OO Chapter Working with J-Link: Sketch added.
6 051118 OO
Chapter Working with J-Link: "Connecting multiple
J-Links to your PC" added.
Chapter Working with J-Link: "Multi core debug-
ging" added.
Chapter Background information: "J-Link firm-
ware" added.
5 051103 TQ Chapter Setup: "JTAG Speed" added.
4 051025 OO
Chapter Background information: "Flash program-
ming" added.
Chapter Setup: "Scan chain configuration" added.
Some smaller changes.
Revision Date By Explanation

J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
9
3 051021 TQ Performance values updated.
2 051011 TQ Chapter "Working with J-Link" added.
1 050818 TW Initial version.
Revision Date By Explanation

10
J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG

J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
11
About this document
This document describes J-Link and J-Trace. It provides an overview over the major
features of J-Link and J-Trace, gives you some background information about JTAG,
ARM and Tracing in general and describes J-Link and J-Trace related software pack-
ages available from Segger. Finally, the chapter Support and FAQs on page 207 helps
to troubleshoot common problems.
For simplicity, we will refer to J-Link ARM as J-Link in this manual.
For simplicity, we will refer to J-Link ARM Pro as J-Link Pro in this manual.
Typographic conventions
This manual uses the following typographic conventions:
Style Used for
Body Body text.
Keyword Text that you enter at the command-prompt or that appears on the
display (that is system functions, file- or pathnames).
Reference Reference to chapters, tables and figures or other documents.
GUIElement Buttons, dialog boxes, menu names, menu commands.
Table 1.1: Typographic conventions

12
J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
EMBEDDED SOFTWARE
(Middleware)
emWin
Graphics software and GUI
emWin is designed to provide an effi-
cient, processor- and display control-
ler-independent graphical user
interface (GUI) for any application that
operates with a graphical display.
Starterkits, eval- and trial-versions are
available.
embOS
Real Time Operating System
embOS is an RTOS designed to offer
the benefits of a complete multitasking
system for hard real time applications
with minimal resources. The profiling
PC tool embOSView is included.
emFile
File system
emFile is an embedded file system with
FAT12, FAT16 and FAT32 support.
emFile has been optimized for mini-
mum memory consumption in RAM and
ROM while maintaining high speed.
Various Device drivers, e.g. for NAND
and NOR flashes, SD/MMC and Com-
pactFlash cards, are available.
emUSB
USB device stack
A USB stack designed to work on any
embedded system with a USB client
controller. Bulk communication and
most standard device classes are sup-
ported.
SEGGER TOOLS
Flasher
Flash programmer
Flash Programming tool primarily for microcon-
trollers.
J-Link
JTAG emulator for ARM cores
USB driven JTAG interface for ARM cores.
J-Trace
JTAG emulator with trace
USB driven JTAG interface for ARM cores with
Trace memory. supporting the ARM ETM (Embed-
ded Trace Macrocell).
J-Link / J-Trace Related Software
Add-on software to be used with SEGGER’s indus-
try standard JTAG emulator, this includes flash
programming software and flash breakpoints.
SEGGER Microcontroller GmbH & Co. KG develops
and distributes software development tools and ANSI
C software components (middleware) for embedded
systems in several industries such as telecom, medi-
cal technology, consumer electronics, automotive
industry and industrial automation.
SEGGER’s intention is to cut software development-
time for embedded applications by offering compact flexible and easy to use middleware,
allowing developers to concentrate on their application.
Our most popular products are emWin, a universal graphic software package for embed-
ded applications, and embOS, a small yet efficient real-time kernel. emWin, written
entirely in ANSI C, can easily be used on any CPU and most any display. It is comple-
mented by the available PC tools: Bitmap Converter, Font Converter, Simulator and
Viewer. embOS supports most 8/16/32-bit CPUs. Its small memory footprint makes it
suitable for single-chip applications.
Apart from its main focus on software tools, SEGGER develops and produces programming
tools for flash microcontrollers, as well as J-Link, a JTAG emulator to assist in develop-
ment, debugging and production, which has rapidly become the industry standard for
debug access to ARM cores.
Corporate Office:
http://www.segger.com
United States Office:
http://www.segger-us.com

J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
13
1 Introduction....................................................................................................................19
1.1 Requirements..........................................................................................20
1.2 Supported OS ......................................................................................... 21
1.3 J-Link / J-Trace models ............................................................................22
1.3.1 Model comparison.................................................................................... 23
1.3.2 J-Link ARM .............................................................................................24
1.3.3 J-Link Ultra .............................................................................................27
1.3.4 J-Link ARM Pro ........................................................................................28
1.3.5 J-Link ARM Lite ....................................................................................... 29
1.3.6 J-Link Lite Cortex-M ................................................................................. 30
1.3.7 J-Trace ARM ........................................................................................... 32
1.3.8 J-Trace for Cortex-M ................................................................................ 34
1.3.9 Flasher ARM............................................................................................36
1.3.10 J-Link ColdFire ........................................................................................37
1.4 Common features of the J-Link product family .............................................38
1.5 Supported CPU cores ............................................................................... 39
1.6 Built-in intelligence for supported CPU-cores ...............................................40
1.6.1 Intelligence in the J-Link firmware ............................................................. 40
1.6.2 Intelligence on the PC-side (DLL) ...............................................................40
1.6.3 Firmware intelligence per model ................................................................43
1.7 Supported IDEs ....................................................................................... 45
2 Licensing........................................................................................................................47
2.1 Introduction............................................................................................48
2.2 Software components requiring a license ....................................................49
2.3 License types ..........................................................................................50
2.3.1 Built-in license ........................................................................................50
2.3.2 Key-based license.................................................................................... 50
2.3.3 Device-based license................................................................................ 51
2.4 Legal use of SEGGER J-Link software.......................................................... 53
2.4.1 Use of the software with 3rd party tools......................................................53
2.5 Original SEGGER products......................................................................... 54
2.5.1 J-Link ....................................................................................................54
2.5.2 J-Link Ultra .............................................................................................54
2.5.3 J-Link Pro ...............................................................................................55
2.5.4 J-Trace................................................................................................... 55
2.5.5 J-Trace for Cortex-M ................................................................................ 56
2.5.6 Flasher ARM............................................................................................56
2.6 J-Link OEM versions ................................................................................. 57
2.6.1 Analog Devices: mIDASLink ......................................................................57
2.6.2 Atmel: SAM-ICE ...................................................................................... 57
2.6.3 Digi: JTAG Link........................................................................................58
2.6.4 IAR: J-Link / J-Link KS .............................................................................58
2.6.5 IAR: J-Link Lite .......................................................................................58
2.6.6 IAR: J-Trace ...........................................................................................59
2.6.7 NXP: J-Link Lite LPC Edition ...................................................................... 59
2.6.8 SEGGER: J-Link Lite................................................................................. 59
2.7 J-Link OBs ..............................................................................................60
2.8 Illegal Clones ..........................................................................................61
3 Setup..............................................................................................................................63
Table of Contents

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J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
3.1 Installing the J-Link ARM software and documentation pack .......................... 64
3.1.1 Setup procedure ..................................................................................... 64
3.2 Setting up the USB interface..................................................................... 67
3.2.1 Verifying correct driver installation ............................................................ 67
3.3 Uninstalling the J-Link USB driver.............................................................. 69
3.4 Setting up the IP interface........................................................................ 70
3.4.1 Connecting the first time .......................................................................... 70
3.4.2 Configuring the J-Link.............................................................................. 71
3.4.3 FAQs ..................................................................................................... 73
3.5 J-Link configurator .................................................................................. 74
3.5.1 J-Link identification methods .................................................................... 74
3.5.2 Using the J-Link configurator .................................................................... 75
3.5.3 Connecting to different J-Links via USB ...................................................... 76
4 J-Link and J-Trace related software...............................................................................77
4.1 J-Link related software............................................................................. 78
4.1.1 J-Link software and documentation package ............................................... 78
4.1.2 List of additional software packages........................................................... 79
4.2 J-Link software and documentation package in detail ................................... 80
4.2.1 J-Link Commander (Command line tool)..................................................... 80
4.2.2 SWO Analyzer......................................................................................... 81
4.2.3 J-Link STR91x Commander (Command line tool) ......................................... 81
4.2.4 J-Link STM32 Commander (Command line tool) .......................................... 83
4.2.5 J-Link TCP/IP Server (Remote J-Link / J-Trace use) ..................................... 84
4.2.6 J-Mem Memory Viewer............................................................................. 85
4.2.7 J-Flash ARM (Program flash memory via JTAG) ........................................... 86
4.2.8 J-Link RDI (Remote Debug Interface)......................................................... 87
4.2.9 J-Link GDB Server ................................................................................... 88
4.3 Dedicated flash programming utilities for J-Link........................................... 89
4.3.1 Introduction ........................................................................................... 89
4.3.2 Supported Eval boards ............................................................................. 89
4.3.3 Supported flash memories........................................................................ 90
4.3.4 How to use the dedicated flash programming utilities ................................... 90
4.3.5 Using the dedicated flash programming utilities for production and commercial
purposes 90
4.3.6 F.A.Q..................................................................................................... 91
4.4 Additional software packages in detail ........................................................ 92
4.4.1 JTAGLoad (Command line tool) ................................................................. 92
4.4.2 J-Link Software Developer Kit (SDK).......................................................... 92
4.4.3 J-Link Flash Software Developer Kit (SDK).................................................. 92
4.5 Using the J-LinkARM.dll............................................................................ 93
4.5.1 What is the JLinkARM.dll?......................................................................... 93
4.5.2 Updating the DLL in third-party programs................................................... 93
4.5.3 Determining the version of JLinkARM.dll ..................................................... 94
4.5.4 Determining which DLL is used by a program.............................................. 94
5 Working with J-Link and J-Trace....................................................................................95
5.1 Connecting the target system ................................................................... 96
5.1.1 Power-on sequence ................................................................................. 96
5.1.2 Verifying target device connection ............................................................. 96
5.1.3 Problems................................................................................................ 96
5.2 Indicators .............................................................................................. 97
5.2.1 Main indicator......................................................................................... 97
5.2.2 Input indicator ........................................................................................ 99
5.2.3 Output indicator...................................................................................... 99
5.3 JTAG interface .......................................................................................100
5.3.1 Multiple devices in the scan chain.............................................................100
5.3.2 Sample configuration dialog boxes............................................................100
5.3.3 Determining values for scan chain configuration .........................................103
5.3.4 JTAG Speed...........................................................................................104

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15
5.4 SWD interface ....................................................................................... 105
5.4.1 SWD speed ........................................................................................... 105
5.4.2 SWO .................................................................................................... 105
5.5 Multi-core debugging ............................................................................. 107
5.5.1 How multi-core debugging works ............................................................. 107
5.5.2 Using multi-core debugging in detail ........................................................ 108
5.5.3 Things you should be aware of ................................................................ 109
5.6 Connecting multiple J-Links / J-Traces to your PC ...................................... 111
5.6.1 How does it work? ................................................................................. 111
5.6.2 Configuring multiple J-Links / J-Traces ..................................................... 112
5.6.3 Connecting to a J-Link / J-Trace with non default USB-Address .................... 113
5.7 J-Link control panel................................................................................ 114
5.7.1 Tabs .................................................................................................... 114
5.8 Reset strategies .................................................................................... 120
5.8.1 Strategies for ARM 7/9 devices................................................................ 120
5.8.2 Strategies for Cortex-M devices ............................................................... 122
5.9 Using DCC for memory access ................................................................. 124
5.9.1 What is required? .................................................................................. 124
5.9.2 Target DCC handler ............................................................................... 124
5.9.3 Target DCC abort handler ....................................................................... 124
5.10 J-Link script files ................................................................................... 125
5.10.1 Actions that can be customized ............................................................... 125
5.10.2 Script file API functions .......................................................................... 125
5.10.3 Global DLL variables .............................................................................. 128
5.10.4 Global DLL constants.............................................................................. 130
5.10.5 Script file language ................................................................................ 131
5.10.6 Executing J-Link script files ..................................................................... 132
5.11 Command strings .................................................................................. 133
5.11.1 List of available commands ..................................................................... 133
5.11.2 Using command strings .......................................................................... 139
5.12 Switching off CPU clock during debug ....................................................... 141
5.13 Cache handling...................................................................................... 142
5.13.1 Cache coherency ................................................................................... 142
5.13.2 Cache clean area ................................................................................... 142
5.13.3 Cache handling of ARM7 cores................................................................. 142
5.13.4 Cache handling of ARM9 cores................................................................. 142
6 Flash download and flash breakpoints.........................................................................143
6.1 Introduction.......................................................................................... 144
6.2 Licensing .............................................................................................. 145
6.3 Supported devices ................................................................................. 147
6.4 Setup for different debuggers (internal flash) ............................................ 148
6.4.1 IAR Embedded Workbench...................................................................... 148
6.4.2 Keil MDK .............................................................................................. 149
6.4.3 J-Link GDB Server ................................................................................. 151
6.4.4 J-Link RDI ............................................................................................ 151
6.5 Setup for different debuggers (CFI flash) .................................................. 152
6.5.1 IAR Embedded Workbench / Keil MDK ...................................................... 152
6.5.2 J-Link GDB Server ................................................................................. 153
6.5.3 J-Link commander ................................................................................. 153
6.5.4 J-Link RDI ............................................................................................ 153
7 Device specifics...........................................................................................................155
7.1 Analog Devices...................................................................................... 156
7.1.1 ADuC7xxx ............................................................................................ 156
7.2 ATMEL ................................................................................................. 158
7.2.1 AT91SAM7............................................................................................ 158
7.2.2 AT91SAM9............................................................................................ 160
7.3 Freescale.............................................................................................. 161
7.3.1 Unlocking Kinetis K40 and K60 devices ..................................................... 161

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7.3.2 Tracing on Kinetis K40 and K60 devices ....................................................161
7.3.3 MAC71x ................................................................................................161
7.4 Luminary Micro ......................................................................................162
7.4.1 Unlocking LM3Sxxx devices .....................................................................163
7.4.2 Stellaris LM3S100 Series .........................................................................163
7.4.3 Stellaris LM3S300 Series .........................................................................163
7.4.4 Stellaris LM3S600 Series .........................................................................163
7.4.5 Stellaris LM3S800 Series .........................................................................163
7.4.6 Stellaris LM3S2000 Series .......................................................................163
7.4.7 Stellaris LM3S6100 Series .......................................................................163
7.4.8 Stellaris LM3S6400 Series .......................................................................163
7.4.9 Stellaris LM3S6700 Series .......................................................................163
7.4.10 Stellaris LM3S6900 Series .......................................................................163
7.5 NXP......................................................................................................164
7.5.1 LPC ......................................................................................................165
7.6 OKI ......................................................................................................167
7.6.1 ML67Q40x.............................................................................................167
7.7 Samsung ..............................................................................................168
7.8 ST Microelectronics.................................................................................169
7.8.1 STR 71x................................................................................................170
7.8.2 STR 73x................................................................................................170
7.8.3 STR 75x................................................................................................170
7.8.4 STR91x.................................................................................................170
7.8.5 STM32 ..................................................................................................170
7.9 Texas Instruments .................................................................................172
7.9.1 TMS470 ................................................................................................172
8 Target interfaces and adapters....................................................................................173
8.1 20-pin JTAG/SWD connector....................................................................174
8.1.1 Pinout for JTAG ......................................................................................174
8.1.2 Pinout for SWD ......................................................................................176
8.2 38-pin Mictor JTAG and Trace connector....................................................179
8.2.1 Connecting the target board ....................................................................179
8.2.2 Pinout...................................................................................................180
8.2.3 Assignment of trace information pins between ETM architecture versions .......182
8.2.4 Trace signals .........................................................................................182
8.3 19-pin JTAG/SWD and Trace connector .....................................................184
8.3.1 Target power supply ...............................................................................185
8.4 9-pin JTAG/SWD connector......................................................................186
8.5 Adapters ...............................................................................................187
9 Background information...............................................................................................189
9.1 JTAG ....................................................................................................190
9.1.1 Test access port (TAP) ............................................................................190
9.1.2 Data registers........................................................................................190
9.1.3 Instruction register.................................................................................190
9.1.4 The TAP controller ..................................................................................191
9.2 Embedded Trace Macrocell (ETM) .............................................................193
9.2.1 Trigger condition ....................................................................................193
9.2.2 Code tracing and data tracing ..................................................................193
9.2.3 J-Trace integration example - IAR Embedded Workbench for ARM.................193
9.3 Embedded Trace Buffer (ETB) ..................................................................197
9.4 Flash programming ................................................................................198
9.4.1 How does flash programming via J-Link / J-Trace work? ..............................198
9.4.2 Data download to RAM............................................................................198
9.4.3 Data download via DCC...........................................................................198
9.4.4 Available options for flash programming....................................................198
9.5 J-Link / J-Trace firmware.........................................................................200
9.5.1 Firmware update ....................................................................................200
9.5.2 Invalidating the firmware ........................................................................200

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10 Designing the target board for trace ..........................................................................203
10.1 Overview of high-speed board design ....................................................... 204
10.1.1 Avoiding stubs ...................................................................................... 204
10.1.2 Minimizing Signal Skew (Balancing PCB Track Lengths)............................... 204
10.1.3 Minimizing Crosstalk .............................................................................. 204
10.1.4 Using impedance matching and termination .............................................. 204
10.2 Terminating the trace signal.................................................................... 205
10.2.1 Rules for series terminators .................................................................... 205
10.3 Signal requirements ............................................................................... 206
11 Support and FAQs.....................................................................................................207
11.1 Measuring download speed ..................................................................... 208
11.1.1 Test environment .................................................................................. 208
11.2 Troubleshooting .................................................................................... 209
11.2.1 General procedure ................................................................................. 209
11.2.2 Typical problem scenarios ....................................................................... 209
11.3 Signal analysis ...................................................................................... 211
11.3.1 Start sequence ...................................................................................... 211
11.3.2 Troubleshooting .................................................................................... 211
11.4 Contacting support ................................................................................ 212
11.5 Frequently Asked Questions .................................................................... 213
12 Glossary.....................................................................................................................215
13 Literature and references...........................................................................................221

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J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
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Chapter 1
Introduction
This chapter gives a short overview about J-Link and J-Trace.

20 CHAPTER 1 Introduction
J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG
1.1 Requirements
Host System
To use J-Link or J-Trace you need a host system running Windows 2000 or later. For a
list of all operating systems which are supported by J-Link, please refer to Supported
OS on page 21.
Target System
A target system with a supported CPU is required.
You should make sure that the emulator you are looking at supports your target CPU.
For more information about which J-Link features are supported by each emulator,
please refer to Model comparison on page 23.