SGS TS68483A User manual

TS68483A
HMOS2 ADVANCED GRAPHIC
AND ALPHANUMERIC CONTROLLER
September 1993
Vcc
60
59
58
57
56
55
54
51
50
49
48
47
46
45
44
53
52
Vss
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 29 28 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9 8 7 6 5 4 3 2 1
68 66 67 65 64 63 62 61
CLK
D4
D5
D6
D7
D8
D9
D10
D11
D12
NC
NC
D13
D14
D15
CS
DS
ADM15
ADM14
ADM13
ADM12
ADM11
ADM10
ADM9
ADM8
ADM7
ADM6
ADM5
ADM4
ADM3
ADM2
ADM1
ADM0
D3 D2 D1 D0 PC/HS HVS/VS
SYNC IN
BLK
CYF1 CYF0
B0 B1
CYS
Y2 Y1
NC
Y0
P0
P1 P2 P3
IRQ
A0
A1 A2 A3 A4 A5 A6 A7
NC AE
R/W
68483-01.EPS
PIN CONNECTIONS
PLCC68
(Plastic Chip Carrier)
ORDER CODE : TS68483A
.FULLY PROGRAMMABLE TIMING GENER-
ATOR
.ALPHANUMERIC AND GRAPHIC DRAWING
CAPABILITY
.EASY TO USE AND POWERFUL COMMAND
SET:
- VECTOR, ARC, CIRCLE WITH DOT OR
PEN CONCEPT AND PROGRAMMABLE
LINE STYLE,
- FLEXIBLE AREA FILL COMMAND WITH
TILING PATTERN,
- VERYFASTBLOCK MOVEOPERATION,
- CHARACTER DRAWING COMMAND, ANY
SIZE AND FONTS AVAILABLE
.LARGE FRAME BUFFER ADDRESSING
SPACE (8 megabytes)UP TO 16 PLANES OF
2048 x 2048
.UP TO 256 COLOR CAPABILITIES
.MASK BIT PLANES FOR GENERAL CLIP-
PING PURPOSE
.FRAME BUFFER CAN BE BUILT WITH
STANDARD 64 K OR256 K DRAM OR DUAL-
PORT-MEMORIES (video-RAM)
.EXTERNAL SYNCHRONIZATION CAPABIL-
ITY
.ON CHIP VIDEO SHIFT REGISTERS FOR
DOTRATE UP TO 18 MEGADOTS/S
.8 OR 16-BIT BUS INTERFACE COMPATIBLE
WITH MARKET STANDARD MICROPROC-
ESSORS
.HMOS2 TECHNOLOGY
.68 - PIN PLCC PACKAGE
.FOR DETAILED INFORMATION, REFER TO
TS68483USER’S MANUAL
DESCRIPTION
The TS68483 is an advanced color graphic proc-
essor that drastically reduces the CPU software
overhead for all graphic tasks in medium and high
range graphic applications such as business and
personal computer, industrial monitoring system
and CAD systems.
1/30

PIN DESCRIPTION
Name Type Function Description
MICROPROCESSOR INTERFACE
D (0 : 15) I/O Data Bus These sixteen bidirectional pins provide communication with either an8
or 16-bit host microprocessor data bus.
A (0 : 7) I Address Bus These eigth pins select the internal register to be accessed. The
address can be latched by AE for direct connection to address/data
multiplexed microprocessor busses.
AE I Address Enable When TS68483 is connected to a non-multiplexed microprocessor bus,
this input must be wiredto VCC.
For direct connection to a multiplexed microprocessor bus, thefalling
edge of AE latches the address on A (0 : 7)pins and the CS input. With
an Intel type microprocessor, AE is connected to the processor
Address Latch Enable (ALE)signal.
DS I Data Strobe Active Low
- In non-multiplexed bus mode, DS lowenables the bidirectionnaldata
buffersand latches theA (0 : 7) lines on its highto low transition.
Data to be written are latched on the rising edge of this signal.
- In multiplexed bus mode, this signallow enables the output data
buffersduring aread cycle. With intel microprocessors, this pin is
connected to the RD signal.
R/W I Read/Write - In non-multiplexed bus mode, this signal controls the direction of
dataflow through the bidirectional data buffers.
- In multiplexed bus mode, this signallow enables the input data
buffers. The entering data are latched on its rising edge. With Intel
microprocessors, this pin is connected to the WR signal.
CS I Chip Select This input selects the TS68483 registers for the current buscycle. A
low level corresponds to an asserted chip select.
In multiplexed mode, this input is strobed by AE.
IRQ O Interrupt Request This active-low open drain output acts to interrupt the microprocessor.
MEMORY INTERFACE
ADM
(0 : 15) I/O Address/Data Memory These multiplexed pins act as address and data bus for display memory interface.
CYS O Memory Cycle Start The fallingedge of this output indicates the beginning of a memory
cycle.
Y (0 : 2) O MemoryAddress These outputs provide the least significant bits of the Y logical address.
B (0 : 1) O Bank Number These outputs provide the number of the memory bank to be accessed
during the current memory cycle.
CYF (0 : 1) O Memory Cycle Status These outputs indicate the nature of thecurrent memory cycle (Read,
Write, Refresh, Display).
VIDEO INTERFACE
P (0 : 3) O Video ShiftRegister
Outputs These four pins correspond to the outputs of the internal video shift registers.
PC/HS O Phase Comparator/
Horizontal Sync. This output can be programmed to provide either the phase comparator output or the horizontal sync. signal.
HVS/VS O Composite or Vertical
Sync. This output can be programmed to provide either the composite sync. signal or the verticalsync. signal.
SYNC IN I External Sync Input This input receives an external composite sync. signal to synchronize
TS68483. This input must be grounded if not used.
BLK O Blanking This output provides the blanking interval information.
OTHER PINS
VCC S Power Supply + 5 V Supply
VSS S Ground Ground
CLK I Clock Clock Input
68483-01.TBL
TS68483A
2/30

232
VIDEO
TIMING
GENERATOR
VIDEO
SHIFT
REGISTERS
DRAWING
AND
ACCESS
PROCESSOR
R4
R10
R0
R1
R2
R3
R12
R23
DATA
32
21 DATA
32
16
48
38
43
3
4
2
5
DISPLAY MEMORY LOGIC
16
65
19
52
VCC
VSS
CLK
BLK
PC/HS
HVS/VS
SYNC IN
P [0:3]
VIDEO
INTERFACE
AE, DS
R/W, CS D [0:15] A [0:7] IRQ
MICROPROCESSOR INTERFACE
CYS CYF [0:1] B [0:1] Y [0:2] ADM [0:15]
DISPLAYMEMORY INTERFACE
ADDRESS
68483-02.EPS
BLOCK DIAGRAM
ABSOLUTE MAXIMUMRATINGS
Symbol Parameter Value Unit
VCC* Supply Voltage – 0.3, 7.0 V
Vin* Input Voltage – 0.3, 7.0 V
TAOperating Temperature Range 0, 70 °C
Tstg Storage Temperature Range – 55, 150 °C
PDm Max Power Dissipation 1.5 W
68483-02.TBL
* With respect to VSS.
Stresses above those hereby listedmay cause permanentdamage to thedevice. Theratings arestress onesonly and functionaloperation of
the device atthese oranyconditions beyondthose indicated intheoperational sectionsof this specifications isnotimplied.Exposure to maximum
rating conditions for extended periods mayaffect device reliability. StandardMOS circuitshandling procedure should be used toavoid possible
damage to the device.
TS68483A
3/30

ELECTRICALCHARACTERISTICS
(VCC = 5.0 V ±5%,V
SS =0, TA=T Lto TH) (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.75 5 5.25 V
VIL Input Low Voltage – 0.3 0.8 V
VIH Input HighVoltage 2 VCC V
Iin Input Leakage Current 10 µA
VOH Output High Voltage (IIoad = – 500 µA) 2.4 V
VOL Output Low Voltage
IIoad = 4 mA ; ADM (0 : 15), IIoad = 1 mA ; other Outputs 0.4 V
PDPower Dissipation 700 mW
Cin Input Capacitance 15 pF
ITSI Three State (off state) InputCurrent 10 µA
68483-03.TBL
I - GENERAL OPERATION
I.1 - Introduction
The TS68483is an advancedcolor graphics con-
trollerchip.It isdirectlycompatiblewith mostpopu-
lar 8 or 16-bit microprocessors.
Itsdisplaymemory, containingtheframebufferand
the charactergenerators, may be assembled from
standarddynamic RAM components.
On-chipvideo shift registersand fully programma-
ble Video Timing Generator allow the TS68483to
be used in a wide range of terminals or computer
design.
Additionalinformationonapplicationscanbefound
in the TS68483User’s Manual.
I.2 - Typical Application Building Blocks
In atypicalusingTS68483,a hostprocessordrives
a display unit which drives in turn a color CRT
monitor.
The display unitconsistsof four hardware building
blocks :
- an TS68483advanced graphics controller,
- a displaymemory (dynamic RAM),
- adisplaymemoryinterface,comprisingafewTTL
parts,
- a CRTinterface of CRT drivers.
For enhanced graphics, the CRT interface may
include a color look-up table circuit. For high pixel
rate (over 18 Mpixels/s), the CRT interface must
includehigh speed video shift registers.
Thedisplaymemory interface andorganizationare
discussedin full detailsin theUser’s Manual.
I.3 - TS68483 Functions
All the TS68483 functionsare under the controlof
the host microprocessor via 24 directly accessible
16-bit registers. These registers are referred to by
their decimal index (R0-R23) (see Figure 1).
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
MARGINCOLOR
MODECOMMAND
XOR
YOR
C0
C1
15 087
TEXLIN
DWX FPY
BPY
BKY
DWY
CONF
STATUS
dy dx
Sx Sy
H
FPX BKX
Yd
Xd
DYd
DXd
RAD
STOP
Ys
Xs
DYs
DXs
COMMAND,
DRAWING
ATTRIBUTES
VIDEO
TIMING
GENERATOR
SHORTRELATIVE
REGISTER
DESTINATION
POINTER
AUXILIARY
GEOMETRIC
ARGUMENTS
SOURCE
POINTER
68483-03.EPS
Figure 1 : Register Map
I.3.1 - VIDEO TIMING AND DISPLAY PROCES-
SOR (R4 to R10).
The video timing generatoris fully programmable:
any popular horizontalscanning periodfrom 20 µs
to 64 µs may be freely combinedwith any number
TS68483A
4/30

of lines per field (up to 1024). The address of the
displayviewport(thispartofthe displaymemory to
be actually displayed on the screen) is fully pro-
grammable. The display processor provides the
display dynamic RAM refresh (see video timing
generatorsection for details).
I.3.2 -DRAWING ANDACCESSCOMMANDS(R0
to R3, R12 to R23).
The 16 remaining registers are used to specify a
comprehensive set of commands. The highly or-
thogonal drawing command set allows the user to
”draw” in the displaymemory such basic patterns
as lines, arcs, polylines, polyarcs, rectangles and
characters. Efficient procedures are available for
either area filling and tiling or line drawing and
texturing. Lines may be drawn with a PEN in order
to get thick strokes. Any drawing is specified in a
213 x2
13 drawing coordinate system.
Toaccess the displaymemory, the hostmicroproc-
essor has an indirect, sequential access to any
”window”. Accesscommands can be used to load
the charactergeneratorsas well asto loador save
arbitrarywindows stored in the frame buffer.
I.4 - Data Type Definitions
PIXEL : this is the smallest color spot displayable
on theCRT.
PEL: a Picture Element is the codingof a PIXELin
the display memory. The TS68483 can handle 4
differentPEL formats :
- 4 colorbits - short
- 4 colorbits + 1 maskbit - short masked
- 8 colorbits - long
- 8 colorbits + 1 maskbit - long masked
DRAWING COORDINATES : (see Figure 2)
The drawing commands are specified and com-
putedina213 x213 cyclicalcoordinatesystem.The
drawing coordinates are clipped and mapped into
the 211 x2
11 display memory addressing space.
Further clippingto the actual frame buffersize may
be performedby the user designed memory inter-
face.
DISPLAYMEMORY :
This is the dedicatedmemory to the display unit.
This memory is addressed as four banks of 4-bit
plane each.
BITPLANE :
Each bitplanehas a maximumcapacityof211 x2
11
bits. A byte wide organization of each bit plane is
required.
MEMORYADDRESS : (seeFigure 3).
In order to addressone bit in the display memory,
the usermust specify :
- Abank number(2 bits)B = 0 to3
- Abit plane number (2 bits) Z = 0 to 3
- AY address (11 bits) Y = 0 to 2047
- An Xaddress (11bits) X =0 to 2047
MEMORY WORD : (see Figure 3)
A32-bit memory word canbe eitherread orwritten
during each memory cycle (8 CLK periods), one
byte at a time in each bit plane in the addressed
bank. The memory bandwidth is in the 6 to 8Mby-
tes/srange.
VIEWPORT :
This is anyrectangulararray of pels located in the
display memory.
FRAME BUFFER :
This is the biggest viewport which can be held in
the display memory. The frame buffer maps a
window at the origin of the drawing coordinates.A
short pel frame buffer may be located in anybank.
Alongpelframe buffermustbe locatedinthe”bank
0, bank 1” pair.
DISPLAYVIEWPORT :
This is the viewport which is displayed on screen.
MASK BIT PLANE :
Whenmaskedpelsareused,amaskbitplanemust
be associated to a frame buffer. Mask bit planes
may be locatedin anyplane of bank 3.
CELL :
ACELL is anypatternstored inthedisplay memory
asarectangulararrayofbitmappedelements.The
drawing of any CELL may be specified with a
scalingfactor.
CHARACTER :
Thisis aonebitperelementCELL.Itmaybestored
in anybit plane,then coloredand drawnin a frame
bufferby use of PRINTCHARACTER command.
OBJECT :
This is a one short pel per element CELL. It may
bedrawnorloadedinaframebuffer.Asourcemask
bit may be associated to each element. An OB-
JECT may then be printed in another location by
use of aPRINT OBJECTcommand.
PEN :
This is the patternwhichis repeatedlydrawnalong
the coordinatesdefinedby eithera LINEor anARC
command.
The PEN may be a DOT (singlepel), a CHARAC-
TERor an OBJECT.
TS68483A
5/30

01234567
Y
X
BANK 1
BANK 0
SHORT PELS
LONG PELS
MASK
BITS
M
BANK3
Z
X
Y
213
211
211 213 0
68483-04.EPS
Figure2 : Cyclical Drawing Coordinates to Display Memory Mapping
8
8
8
8
Z32
X
Y
0123
THE MEMORY WORD
BANK0 BANK 1 BANK2 BANK3
7
4 BANKSOF 4 BIT PLANES EACH
68483-05.EPS
Figure3 : TheDisplay Memory Addressing Space
II - COMMANDS
II.1 - Introduction
The command set is strongly organized in five
subsetor commandtypes.
DRAWING COMMANDS :
- LINEAR(line, arc)
- AREA(rectangle, trapezium, polygon, polyarc)
- PRINTCELL (print character, print object)
ACCESS COMMANDS
CONTROL COMMANDS (move cursor, abort)
The commandsare parametered; this means that
any command can be executed withoptions freely
selected out of a given option set. This option set
is common for any command of a given type. For
example,any drawing commandmay be parame-
tered for destinationmask bit use.
The command code also defines the command
type and its parameters.Acommand is completely
defined when a valuehas been set for each of its
arguments.
These argumentsare :
- the geometric arguments given in the drawing
coordinate system for every drawing command.
They are automaticallymapped into the destina-
tion frame buffer ;
- the parametricvaluesare the values required by
the selectedparameters ;
- the attributevalues are the other valuesrequired
by a drawing command ; colors or scaling factors
for example ;
- the display memory addresses.
The command code is specified in register R0.
Beforeinitiatinga command execution,each argu-
ment must be specifiedin its dedicatedregister : -
an Xd, Yd drawing coordinate pair for example, is
always located in registers R14, R15.
The monitoringof acommandexecutionisdoneby
reading the status register R12 or using the IRQ
signal.
TS68483A
6/30

II.2 - Pointersand GeometricArguments (see
Figure4)
Pointersare used tospecify main geometric argu-
ments and display memory addresses.
II.2.1 - DISPLAYMEMORY ADDRESS
Abit in the displaymemory is addressedby :
- a banknumber B =0 to 3
- a plane number Z =0 to 3
- an X address X =0 to 2047
- a Y addres Y = 0 to 2047
II.2.2 - DESTINATIONPOINTER :
RegistersR14 to R17
This pointer gives the coordinate (Xd, Yd) and
dimension(DXd, DYd) of eithera lineor a window
in the drawingcoordinate system. These drawing
coordinates are easily mapped into a PEL DIS-
PLAYMEMORY address.
(X, Y) coordinates are clipped to 11bits in order to
get the Xd, Yd destinationpel addresses.
A bank number Bd must be explicitly provided to
addressa destinationframebuffer.Whenlongpels
are used, Bd must be even.
Whenmasked pels are used, the destinationmask
plane numberZd (implicitly in bank3) must also be
provided.
II.2.3-SOURCEPOINTER:RegistersR20toR23.
A source cell such as a character, a pen or an
object, is addressed by the source pointer in the
display memory.
Asource pointer specifies :
- a banknumber Bs = 0 to 3
- a Ysaddress Ys= 0 to2047
- an Xs address; this addressis a byte addressso
that the 3 LSBs are not specifiedXs = 0 to 255
- a celldimension DXs, DYs
- a bit plane addressZs.
When acharacter is addressed,Zsgivesthe plane
number into the bank Bs. When an object is ad-
dressed Zs gives the source mask plane number
in the bank B3.
II.2.4 - NOTES :
1. The TRAPEZIUM command makes a special
use of R21. In this case, R21 holds an X1
drawingcoordinatewhich hasthe sameformat
as Xd.
2. The ARC and POLYARC commands require
two extra geometric parameters (RAD and
STOP). They are specified in the drawing
coordinatessystemandstoredinregistersR18,
R19.
3. Any drawingcommand may be parameteredto
use short incremental dimensions, DXY in
register R13 instead of the standard DXd, DYd
in the”R16, R17” register pair (see Figure 5).
4. The access commands use the destination
pointer location as a data buffer. The memory
addresses and dimension of the access
viewport are then specified in the source
pointer,independentlyof the data transfer.
5. DXd, DYd and DYs may specify a negative
value.In thiscase,theymust becodedbya sign
(0 = positive, 1 = negative) and an 11-bit
absolute value.
Table 1 : CommandSet Structure
Command Drawing Mode Type Group
Line
Arc Up to the Pen Linear
Drawing
Rectangle
Trapezium
Polygon
Polyarc
Monochrome Area
Print Char
Print Object Bichrome Polychrome Cell
Load Viewport
Save Viewport
Modify Viewport
Access Management
Move Cursor Abort Control
68483-04.TBL
TS68483A
7/30

II.3 - Destination Mask and Source Mask
Amask bit may be associatedto any pel stored in
the display memory.
II.3.1 - DESTINATION MASK USE (DMU)
Any drawing command may be parametered for
destinationmask use.In thiscase,any destination
pel cannot be modified when its mask bit is reset.
SS
76543210
R13
dy dx
68483-07.EPS
Figure5 : Short Dimension Register R13
R14
R15
R16
R17
R20
R21
R22
R23
1514131211109876 45 3210
13-bit positive valueBank number
Plane number 13-bit positive value
Absolute value
Absolute value
11-bit positive value
8-bit positive value
Absolute value
11-bit positive value
Bank number
Character cell plane (PCA)
or source mask plane (PVS, PVF)
Sign
Sign
Sign
Underlined (cell)
Bd
Zd
S
S
Bs
Zs
S
U DXs
DYs
Xs
Ys
DXd
DYd
Xd
Yd
Pel
address
DESTINATION
POINTER
SOURCE
POINTER
Byte
address
Reserved
Don’t care
Only used with TRAPEZIUM command
Note : Sign value S = 1 negative + absolute value S = 0 positive
68483-06.EPS
Figure4 : Pointers
TS68483A
8/30

In otherwords :
- When the destinationmask use (DMU) parame-
ter isset :
- a pel maybe modifiedwhen its mask bit is set
- a pel cannot be modified when its mask bit is
reset.
- When the destinationmask use (DMU) parame-
ter is cleared :
- a pel may be modified, independently of its
maskbit value.
This provides a very flexible clipping mechanism
not restricted to rectangular windows. (See desti-
nation pointer section for destinationmask bit ad-
dressing).
II.3.2 - SOURCE MASK USE (SMU)
APRINTOBJECTcommand may be parametered
for sourcemaskuse.In thiscase, thesourcemask
bit associated with any source pel is read first.
When its mask bit is cleared, a source pel is con-
sideredastransparent.(Seesourcepointersection
for source mask bit addressing).
In otherwords :
- When the SMU parameter is set, the color of a
destination pel, mapped by a given source pel,
may take this source color value only when this
source bit mask is set. The destinationpel keeps
its own color value when the source bit mask is
cleared.
- When the SMU parameter is cleared, a source
pel color may be mapped into destination pel
color independentlyof the sourcebitmask value.
The source bit mask acts as a TRANSPAR-
ENCY/OPACITYflag which is enabled by SMU.A
PRINT OBJECTcommand may be independently
parameteredbybothSMUandDMU.Thisprovides
a very powerfultiling, printobject or move mecha-
nism.
II.4 - DrawingAttributes
01234567
ODD
BANK EVEN BANK
68483-08.EPS
Figure6 : Color Register
The general drawing attributesare the colors, the
drawing mode, and the scaling factor.
II.4.1. COLORS : Registers R1 andR2
Two 8-bit color values, C0 and C1, may be speci-
fied in registers R1 and R2. The low order 4-bit
nibble of a color value is drawn in an even bank.
Thehighordercolornibbleisdrawninanoddbank.
When long pels are used, banks 0 and 1 are
generally addressed as the frame buffer. When
short pels are used, any bank may hold a frame
buffer.In thiscase, thebankparityselectsthe color
nibble used. (See destination pointer section for
bankaddressing).
II.4.2.DRAWING MODE : RegisterR0
The drawing mode defines the transforms to be
applied to the pels designated by the drawing
commands. Thereare threedrawing modes.
II.4.3.MONOCHROME MODE
Any AREA drawing command, RECTANGLE for
instance, definesthrough its geometricarguments
an active set ofdestinationpels, thatis to saya set
ofpels to be modified.
When DMU = 1, this active set is further reduced
by the masking mechanism to only these destina-
tion pels with a bit mask set.
The active destination pels are then modified ac-
cordingto two elementarytransforms coded in R0.
COLORTRANSFORM :
The color value C of each active pel is modified
according to one color transform selected out of
four :
- 00 - printedin C0 : C ← C0
- 01 - printedin C1 : C ← C1
- 10 - printedin ”transparent” : C← C
- 11- complemented : C← C
This yields to a reversible markermode.
MASK BIT TRANSFORM :
The destination mask bit of each active pel is
modifiedaccordingtoonemask transformselected
out of four :
- 00 - reset bit mask : M ← 0
- 01 - set bit mask : M ← 1
- 10 - no modification: M ← M
- 11- complementbit mask : M ← M
This scheme allows the color bits and the mask bit
ofanypelbelongingtotheactiveset tobemodified
independently. The color transform is performed
first.
II.4.4 - BICHROMEMODE
APRINT CHARACTER commandismore complex
because it involves two different active sets :
FOREGROUND and BACK GROUND.
TheFOREGROUNDis that set of destinationpels
printedfrom set elements in the charactercell.The
BACKGROUND is made of all theremaining pels
belongingto the destinationwindow.
When DMU = 1, the FOREGROUND and BACK
GROUND are further reduced by the destination
masking mechanism(see Figure 8).
A bichromedrawingmodeis definedby 4elemen-
tary and independent transforms (see Fig-
ure 7) :
- a color transform and a mask transform for the
FOREGROUND PELS
TS68483A
9/30

- a color transform and a mask transform for the
BACKGROUNDPELS
II4.5 - POLYCHROME MODE
A print object command defines a source window
through the source pointer :
When SMU = 0, any pel of this window is active,
mapped and clipped to the destination window
dimension.
When SMU = 1, only pels which have a source
mask bit set are active,mapped and clipped to the
destinationwindow dimension.
In both cases, when DMU = 1, the active source
pelsarefurtherreducedbythedestinationmasking
mechanism.
Bothmasktransformsmust beprogrammedat ”NO
MODIFICATION” for correct operations (see Fig-
ure 7).
II.4.6-THELINEARDRAWINGCOMMANDCASE
A LINE or ARC drawing command may be exe-
cuted in any drawing mode depending on the
PEN.
When the pen is a DOT, this pel is printed at each
activecoordinateaccordingtomonochromemode.
Whenthe penis a CELL,this cell isprinted at each
active coordinate.In the bichrome mode when the
cell is a character, and in the polychrome mode
when thecell is an object.
For eachactivecoordinates,the activedestination
01234567
00
01
10
11
:
:
:
:
C0
C1
C
C
C
C
C
C
←
←
←
←
00
01
10
11
:
:
:
:
M
M
M
M
←
←
←
←
0
1
M
M
REGISTERR0
COLOR
MASK
BACKGROUND FOREGROUND
01234567
BACKGROUND FOREGROUND
XXXX
XXXXXXXX
10 10
Monochrome
Bichrome
Polychrome
68483-09.EPS
Figure 7 : DrawingMode RegisterR0
set is defined by the cell dimensions (DXs, DYs).
Note : when the cell is an object, SMU is not
programmable and is implicitly set. A calculated
coordinate is active when the rotated LSB linear
texturebit in (R3) is set.
YY
YY
XX
XX
DMU = 0 DMU = 1
(Xd, Yd) (Xd, Yd)
(Xd, Yd) (Xs, Ys)DXd > 0 DXs > 0
DYd < 0
DYs < 0
DESTINATION WINDOW CHARACTER CELL
MAPPED CH ARA CTER WINDOW
NO MODIFICATION
FOREGROUND
BACKGROUND
MAPPED
CHARACTER
WINDOW
MASK BIT = 1
MASK BIT = 0
ELEMENT =0
SET ELEMENT = 1
68483-10.EPS
Figure8 : Print Character Command
TS68483A
10/30

II.4.7- SCALINGFACTORANDCELLMAPPING:
(see Figures 9 and 10)
15 14 13 12 11 10 9 8
SX SY
SX or SY S
1
2
15
16
0
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
R1
68483-11.EPS
Figure9 : ScalingFactor
Y
X
DYs > 0
DXs > 0Xs, Ys
Y
X
DYd > 0
DXd > 0Xd, Yd
Y
X
DYd < 0
DXd > 0Xd, Yd
Y
X
DYs < 0
DXs > 0
Xs, Ys
Y
X
DYd > 0
DXd > 0Xd, Yd
Y
X
DYd < 0
DXd > 0Xd, Yd
68483-12.EPS
Figure10 : Cell Mappingversus DYd, DYs SIGN
Any cell may be printed with a scalingfactor.
This scaling factor is an integer pair Sx, Sy = 1
to 16. This scaling factor is interpreted with the
PRINT CHARACTER, PRINT OBJECT and LIN-
EARcommands when thepen is acell. The AREA
or ACCESS or LINEAR (DOT) commands are
never scaled.
TheLINEAR(PEN)command should be usedwith
a scalingfactor of 1 becausethe pen is clipped at
DXs,DYs.
Thescalingfactor is first applied to the sourcecell
before mapping and drawing. The drawing and
mappingisprocessedwith sign bitofDYd andDYs
values (see Figure 10).
Notes:
- DXs is always positive
- The DYs signmirrors the cell
- DXd must be positive with a PRINT CELL com-
mand
- DXd and DYd may get any sign with a LINEAR
DRAWING command. If a pen is used, these
signsare then irrelevant to the pendrawing. The
pen is mapped with positiveincrementvalues.
TS68483A
11/30

II.5 - Command Set Overwiew
Dyd
DXd
PEN
68483-12.EPS
Figure11
II.5.1 - LINEARDRAWING
LINE(Xd,Yd,DXd,DYd).ARC(Xd,Yd, DXd,DYd,
RAD, STOP).
The curve maybedrawnwithanypenandwithany
linear texture (register R3). For each set of com-
puted coordinates,R3 isright rotatedand the pen
is printed when the shifted bit isset.
II.5.2 - AREADRAWING
- RECT (Xd, Yd, DXd, DYd)
- TRAPEZIUM(Xd, Yd, DXd, DYd, X1)
- POLYGON(Xd, Yd, DXd, DYd)
- POLYARC(Xd, Yd,DXd, DYd, RAD, STOP)
EitherRECTorTRAPEZIUMallowstodrawdirectly
all the pels inside the boundary.
Any other closed boundaries may be filled by a
3-step process :
1. The mask bits inside a boundary box must be
reset by a RECTcommand.
2. AsequenceofmixedPOLYGONandPOLYARC
commandsdescribingtheclosedboundarysets
the mask bits of the pels inside this boundary.
3. This area may then be painted by a
RECTANGLEcommanddefinedforabounding
box, with destination masking. It may also be
tiledby use of a PRINT CELL command.
Note : themaskbitof anypellying ontheboundary
itself is not guaranteedto be set by step 2.
II.5.3 - PRINTCELL COMMANDS
PRINT CELL (Xd, Yd, DXd, DYd ; Xs, Ys, DXs,
DYs).
The cell addressedby Xs, Ys, DXs, DYs is scaled
then printed at location Xd, Yd and clipped at the
dXd, dYd dimensions.
When dXd, dYd ismuchlarger than DXs,DYs the
commandmaybe parameteredforrepeatdrawing.
These commands may also be parametered for
destinationmask use.
Further more the PRINT OBJECTcommand may
be parameteredfor sourcemask use.
These commands have a wide range of applica-
tions : text drawing, area tiling, print or move ob-
jects, scale and move viewports.
Note : an underlinedcell is drawn when the MSB
ofR23 is set.
II.5.4 - ACCESS COMMANDS
- LOAD VIEWPORT (Xs, Ys, DXs, DYs)
- SAVE VIEWPORT(Xs, Ys, DXs, DYs)
- MODIFY VIEWPORT(Xs, Ys, DXs,DYs)
These commands provide sequential access to a
viewport in a frame buffer fromthe microprocessor
database.
Data are transferred to/from the display memory,
word sequentially.
The R14 to R17 registersare used as a two mem-
ory word FIFO (memory word is 8 shortpels, i.e. 4
bytes).
The source pointer (R20-R23) is used to address
the viewport for all access commands.
When long pels are used, the command must be
executedoncemore whenthebanknumberin R20
hasbeen updated.
II.5.5 - COMMAND EXECUTION
Each on-chip 16-bit register has four addresses.
One address is used for plain read or write. The
otheraddressesare usedto initiatecommand exe-
cution automatically on completion of the register
access.
This scheme allows the command code and its
arguments to be loaded or modified in any other.
An incremental line drawing command, for exam-
ple,maybe executedagainand againwith succes-
siveincremental dimensionsand whithout need to
reload the commandcode itself.
As soon as a command execution is started, the
FREE bitisclearedin the STATUSregister. Thisbit
is automatically set when the execution is com-
pleted.
Thecommandsaregenerallyexecutedonlyduring
retrace intervals. However full time execution is
possible when either the display is disabled or
videoRAM componentsare used.
II.5.6 - STATUS REGISTER(see Figure12)
This register holds four read-onlystatus bits :
- FREE : this status bit is set when no executionis
pending
- VS : vertical synchronizationstate
- SEM: thisstatusbit isset whentheFIFOmemory
wordis inacessibleto the microprocessorduring
a viewport transfer
- NSEM : this status bit is set when the FIFO
memorywordisaccessible tothemicroprocessor
during a viewport transfer.
Eachof thesestatusbitsis maskable.The masked
status bits are NORed to the IRQ output pin.
TS68483A
12/30

15 14 13 12 11 10 9 8
STATUSREGISTER R12
MASKNSEM
NSEM
MASKSEM
SEM
MASKVS
VS
MASKFREE
FREE
READONLY
15 14 13 12 11 10 9 8 R12
IRQ
68483-14.EPS
Figure12 : StatusRegister
III - MICROPROCESSOR INTERFACE
III.1 - Introduction
The TS68483is directlycompatible with any popu-
lar8 or 16-bithost microprocessor; eitherMotorola
type (6809, 68008, 68000) or Intel type (8088,
8086).
The host microprocessorhas direct access to any
of the twenty four 16-bit on-chip registers through
the microprocessor interface pins :
- D(0:15) : 16 bidirectionaldatapins.
- A(0:7) : 8 address inputs
- AE, DS, R/ W, CS : 4 controlinputs.
The twenty four registers are mapped in the host
addressing space as 256 byte addresses (see
Figure 13)
- A(1:5) select oneout of 24registers.
- A0 selects thelow orderbyte (A0 =1) or the high
order byte (A0 = 0) of the selected register.
- A(6:7) providethecommand executioncondition.
The host microprocessor bus may be either 8 or
16-bits wide and maybe address/datamultiplexed
or not.
ThetwoflagsMBandBWintheCONFIGURATION
register R10 allow the data bus size and multi-
plexed/non-mutiplexed organization to be speci-
fied (see Table 2).
Table 2 : MPU Selection
Type of MPU Bus Conf. Reg. TS68483 Pins
BW MB AE DS R/WAO A (1 : 7) D (8 : 15)
NonMux 16-bit (68000) 0 0 1 UDS or LDS R/W O A (1 : 7) D (8 : 15)
8-bit (68008) 1 0 1 DS R/W AO A (1 : 7) D (0: 7)
Mux 16-bit (8086) 0 1 ALE RD WR O AD (1 :7) AD (8 : 15)
8-bit (8088) 1 1 ALE RD WR ADO AD (1 :7) AD (0 : 7)
68483-05.TBL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A0 = 0 A0 = 1
Byte Addressing
A7 A6 A5 A4 A3 A2 A1 A0
High/Low Byte Address
16-bit Register ADDRESS
Execution Condition
68483-15.EPS
Figure13 : On-chip Address and Byte Packing
TS68483A
13/30

37 26
28
25
29D [8:15]
D [0:7]
A [1:7] A [1:7]
D [0:7]
D [8:15]
TS68483TS68000
V
CS
R/W
UDSor LDS
CC
26
28
25
29
D [0:7]
A [1:7] A [1:7]
D [0:7]
D [8:15]
TS68483TS68008
V
CS
R/W
DS
CC
68483-16.EPS
Figure14 : Interfacewith TS68000/68008MPU
37
26
28
25
29AD[8:15]
AD [0:7]
A [1:7]
D [0:7]
D [8:15]
TS684838086
ALE
CS
WR
26
28
25
29
AD [0:7]
A [1:7]
D [0:7]
D [8:15]
TS684838088
ALE
CS
WR
RD
RD
37
8
88
7
A [1:7]
8
7
88
AD0
68483-17.EPS
Figure15 : Interfacewith 8086/8008MPU
TS68483A
14/30

III.2 - HardwareRecommendations
(see Figures 21, 22, 23 and24)
A0-PIN :
1. Whenusing a 16-bit data bus, the A0input pin
must be grounded.No single byte access can
be performed.
2. In order to conformwith the high byte/lowbyte
on-chip packing, the A0 input pin must be
inverted when using an 8-bit bus Intel type
microprocessor (8088 for example).
A(1:7),D(0:7), D(8:15) pins :
1. With any8-bit data bus,the D(0:7)and D(8:15)
pinsmust be paired in orderto demultiplexthe
low order data bytes and the high order data
bytes.
2. When using address/datamultiplexed bus, the
D(0:7) pins are paired with A(0:7) in order to
demultiplexdata from address.
AE, DS, R/ W, CS : See pin description.
III.3 - SOFTWARE RECOMMENDATIONS
1. The CONFIGURATION register R10 must be
first initialized.
The BW 15 flag is interpreted by the bus
interface to recognizean 8-bit/16-bitdata bus.
The MB and BW 15 flags are used to decide
when toinitiate a commandexecution.
2. Each register byte has 4 addresses in the
microprocessor memory map. These 4
addresses differ only by A(6:7). This scheme
allowsa 68008programmer toreadorwrite any
data type (byte, word, long word) and
automatically initiate or not a command
executionattheendof thistransfer.Thetransfer
lasts one, twoor four bus cycles.
A68000programmer isrestricted to onlyword and
long word data types (see Table 3).
IV - THEVIDEO TIMING GENERATOR RAM REFRESH AND DISPLAYPROCESS
Table 3 : CommandExecutionCondition
Address Execution Condition Data Type Transfer
A7 A6 8-bit Data Bus 16-bit Data Bus
0 0 no Exec Any Type Any Type
0 1 Exec after aBus Cycle 1 Byte 1 Word
1 0 Exec After 2 Bus Cycles 1 Word 1 Long Word
1 1 Exec after 4 Bus Cycles 1 Long Word* ILLEGAL
Notes : Word transfer must respect word boundary.
Long word transfer must respect long word boundary.
* Not available with 8088 MPU type.
68483-06.TBL
IV.1 - Introduction
TheVideoTimingGeneratoriscompletelysynchro-
nouswiththeCLKinput,whichprovidesa pixelshift
frequency(up to 18MHz). The Video Timing Gen-
erator :
- delivers the blankingsignal (BLK), the horizontal
(HS)andvertical (VS)synchronizationsignalson
respectiveoutput pins,
- schedulesthe memory time allocated to the dis-
play process, dynamic RAM refresh and com-
mandexecution,
- is fully programmable
- can be synchronizedwith an external composite
video sync signal connected to the SYNC IN
input.
IV.2 - ScanParameters(see Table 4 and Fig-
ure26)
IV.2.1 - TIMING UNITS
The timeunit of any vertical parameteris the scan
line.
The time unit of any horizontal parameter is the
memory cycle,which is 8 periodsof the CLK input
signal.
Thesetwo parametersareinternallyprogrammed:
- Horizontal sync pulse duration= 7 cycles
- Vertical sync pulse duration = 2.5 lines.
IV.2.2 - BLANKINGINTERVAL
The blankinginterval starts :
- at the leading edge of the vertical sync pulse.
Vertical blanking interval actual duration is 2.5
lines more than the programmed value.
- twocyclesbeforetheleadingedgeofthehorizon-
tal sync pulse. The actual horizontal blanking
interval duration is 3 cycles more than the pro-
grammedvalue.
Note : During the programmed blanking interval,
the videooutput pins P(0:3) are forced low.
IV.2.3 - PORCH AND MARGIN COLOR
During the porch interval, the programmablemar-
gin coloris displayedon the P(0:3) outputs.
The display process may be disabled by setting
DPD flag.This willbe interpretedas aporchexten-
sion.
Note : By process, the value of the block porch
must be strictlyabove 0.
TS68483A
15/30

IV.2.4.MEMORY TIME SHARING (see Figure16)
7TTL
BLKX
HORIZONTAL
Horizontal Minimum
Number of Cycles
BKX
FFX
DWX
H
4
3
3
19
3T BKX
FPX
FRONT
PORCH DWXDISPLAY BACK PORCH
1T2T
Vertical Minimum
Numberof Lines
FPY
DWY
BPY
BKY
1
1
3
1
MARGIN
DISPLAY
BLANKING
BLANKING
FRONT
PORCH
FPY
DISPLAY
DWY
BACK
PORCH
= BPY - 25
BKY
25 Lines
2H
BLKY
68483-18.EPS
Figure16 : VideoProgramming
The Video Timing Generator allocates memory
cycles to either the display process, RAM refresh
or command execution. In this respect, the scan
lines perfieldare split between: the DWY display-
able lines.
When VRE = 0, Video RAMs are not used.
The DWY x DWX cycles in the display intervalare
allocatedto the display processwhen it is enabled
(DPD = 0). When the display process is disabled,
these cycles are allocated as for non displayable
lines.
When VRE = 1, one cycle per displayline is allo-
cated to the display process. Other cycles are
allocated as for non displayable lines. The last
periodof theBLKX signal may be used to load the
internal video RAM shift register.
- the non displayable lines. In one out of nine non
displayablelines, DWX cyclesare allocatedtothe
refresh processwhen it is enabled (RFD = 0).
- In Float cycle, an external X address must be
provided. The Y address is still provided on
ADM(0:7)andY(0:2),whileADM(8:15)areinhigh
impedancestate.
IV.2.5.COMMAND ACCESS RATIO
This allocation scheme leaves about 50% of the
memory bandwidth for command access when
programminga standardTV scan. Thisratio drops
to the 30% range when a better monitor is in use
(32µsoutof43µs displayableperline,360lines out
of 390 fora 60Hz field rate). The higherresolution
means more memory accesses in order to edit a
given percentage of the screen area. In this case
Video RAMs are very helpful to keep 90% of the
memorybandwidthavailableforcommandaccess.
IV.3 - Display Process
The Video Timing Generator allocates memory
cyclestothe DisplayProcessor inorder toreadthe
Display Viewport from memory. The Display View-
port upper left corner address is programmable
through DIB, YOR and XOR. The display viewport
dimensions are related to the display interval of
DWY lines by DWX cycles per field.
TS68483A
16/30

IV.3.1 - Y ADDRESSES
WhenINE = 0, the fieldsare not interlaced.The Y
Display Viewportaddress is initialized with YOR at
the first displayable line then decremented by 1 at
each scan line. The Display Viewportis thusDWY
pel high.
When INE = 1, the fields are interlaced. The Y
Display Viewportaddressis initialized as shown in
the table below. It is then decremented by two at
each scan line. The viewport is thus 2 x DWY pel
high.
Even Field Odd Field
YorEven Yor Yor + 1
Yor Odd Yor –1 Yor
Y display Viewport address initializationwhen INE = 1
IV.3.2- X ADDRESSES AND MODX FLAGS
The X Display Viewport address is initialized with
XOR at the firstdisplayable cycle of eachdisplay-
ableline.Itisthenincrementedateachsubsequent
cycle accordingto MODX flags.
MODX1 MODX0 X INCR Video Shift
Register Memory Cycle Type
0 0 + 1 Internal Read
0 1 + 1 External Dummy
Read
1 0 + 2 External Dummy
Read
1 1 External Float
In internal mode, the Display Viewport is 8. DWX
pel wide.The on-chipvideo shift register areused.
InDummyread,thememoryisreadbuttheon-chip
video shift registers are not loaded, instead they
retain their margin color. Externalvideo shift regis-
tersare presumed to be loadedby either 8 pels or
16 pels per cycle according to the programmed
incrementvalue.
In Float cycle, an external X address must be
provided. The Y address is still provided on
ADM(0:7) and Y(0:2), whileADM(8:15) are in high
impedancestate.
Note : See Memory Organization and Memory
Timing for further details on the memory cycles.
IV.3.3 - THE VIDEO RAM CASE (VRE = 1)
In thiscase,thelastcycleof thehorizontalblanking
interval is systematically allocated to the display
process for DWY scan lines per field.
This cycle bears the scan line address, the bank
number and the X addresswhich is always XOR.
MODX must be programmed to use external shift
register (Dummy read).
IV.3.4 - PAN ANDTILT
The host can tilt or pan the Display Viewport
throughtheframe bufferbymodifyingYORorXOR
arguments.Panningisperformedon8 pelbounda-
ries.
IV.4. DynamicRam Refresh
No memory cycles are explicity allocated to the
RAMrefresh when RFD = 1.
WhenVRE = 0 and DPD = 0, the Display Process
is supposed to be able to over-refresh dynamic
components.This can be donebycarefullogical to
component address mapping. During the remain-
ing non displayable lines, the Display Viewport
address continues to be incremented : Y address
on eachline accordingto INE, Xaddressinitialized
by XOR then incremented according to MODX.
This Display viewport address is allowed to ad-
dressthe memory for DWX cyclesin onlyone line
out of nine for refreshpurposes.
When VRE = 1 or DPD = 1, any line is processed
as anondisplayableline withrespect totherefresh
process.
IV.5. Configuration and External Synchroniza-
tion
The R10 register holds eight configuration flags.
Sixoftheseflagsarededicatedto theVideo Timing
Generator.
- SSP : this flag selects thesynchronizationoutput
pin configuration:
- NPC, NHVS, NBLK : these threeflags invert the
PC/HS, HVS/VS and BLK outputs respectively.
(Ex. : WhenNBLK = 1 blankingis activehigh).
The SYNC IN input pin provides an external com-
posite synchronization signal input from which a
Vertical Sync In (VSI) signal is extracted. The
SYNC IN signal is sampled on-chip at CLK fre-
quency.Its rising sampled edgeis comparedto the
leading edge of HS. A PC comparison signal is
externally available (see SSPand NPC flags).
VSIE: thisflag enablesVSIto reset theinternalline
count.
HSIE:thisflag enablesthe risingedgeofSYNCIN
to actdirectlyontheVideoTimingGenerator.When
the leadingedge of HS does not match at 1 clock
period a rising edge of SYNC IN, one extended
cycle is performed (nine clock periods instead of
eight).
Flag Output Pins
PC/HS HVS/VS
SSP = 1 HS VS
SSP = 0 PC HVS
TS68483A
17/30

Table 4
Name Number
of Bits Mininmum Values Register Description Function
DWY 10 1 R9 Number of Display lines per Field
Vertical
Scan
INE 1 R8 Interlace Enable when INE = 1
BKY 5 1 R8 Number of Lines in Vertical Blanking – 2.5
FPY 5 1 R7 Number of Lines in Vertical Front Porch
BPY 8 3 R6 Number of Lines in VerticalBack Porch + 2.5
H 6 19 R6 Number of Double Cycles per Line Horizontal
Scan
FPX 4 3 R8 Number of Cycles in Horizontal Front Porch
BKX 4 4 R8 Number of Cycles in Horizontal Blanking – 3
DWX 7 3 R7 Number of Cycles of the Display Window
XOR 8 R4 X, Y, and bank logical address in the display
memory of the display viewport upper left corner Display Process
YOR 11 R5
DIB 2 R4
MODX 2 R9 Selection of the X Addressing Mode
MC 4 R4 Margin Color
RFD 1 R7 RAM Refresh Disable when RFD = 1 Memory
Time
Sharing
DPD 1 R7 Display Process Disable when DPD = 1
VRE 1 R8 Video RAM Enable When VRE = 1
Note : one cycle = 8 periods ofCLK Clock
68483-07.TBL
V. MEMORY ORGANIZATION
V.1 - Introduction
The display memory is logically organized as four
banks of 4-bit planes. Thus a bit address in the
display memory is given by the quadruplet :
- B = bank number,from 0 to 3
- Z = planenumber, from 0 to 3
- X = bit addressinto the plane,from 0 to 2047
- Y = bit address into the plane, from 0 to 2047.
Inonememorycycle(8CLKperiods),thecontroller
can access a memory word. This 32-bit memory
word holds one byte from each plane in a given
bank. In order to address this memory word, the
controllersupplies :
- B(0:1) : binary value of the bank number
- X(3:10): binaryvalue of the wordaddress
- Y(0:10): binaryvalue of the wordaddress.
Z and X(0:2) arenot supplied.They give only a bit
addressin a memory word.
V.2 - Memory Cycles
24 pins are dedicated to the memory interface.
- ADM(0:15) : these16 bidirectional pins are mul-
tiplexed three times during a memory cycle (see
Figure 25) :
TA : address period. Output of the X(3:11)
and Y(3:11)address
TO : evendataperiod.The evenZbytesare
eitherinput or output.
T1 : odd data period. The odd Z bytes are
eitherinput or output.
Y(0:2) : three LSB Y address output pins (non-
multiplexed)
B(0:1) : two bank address output pins (non-
multiplexed)
- CYS:Cyclestartstrobeoutput(non-multiplexed).
CYS is at CLK/8frequency. ACYS pulse isdeliv-
ered only when a command, display or refresh
cycle is performed.
- CYF(0:1) : Two cycle status outputs (non-multi-
plexed).Four cycletypesare defined:Command
Read, Command Write, RAM Refresh, Display
Access.
Because severaloptionsmay be selectedfor RAM
refresh anddisplay access bythe MODX and VRE
flags (see Video Timing Section), there are more
than four memory cycle types (see Figure 25 and
Table 5).
V.3 - DisplayMemory Desing Overview
The displaymemory implementationis application
dependant.The basic parametersare :
- the number of pixels to be displayedNx.Ny
- the number of bits per pel
- the vertical scanning frequency, which must be
picked inthe 40Hzto 80Hzrange(noninterlaced)
or in the60Hz to 80Hz range (interlaced).
This yields a rough estimate of thepixelfrequency.
When the pixel frequency is in the 15 to 18MHz
range and 4 bits per pixelor least are required,the
on-chipvideoregistersandstandarddynamicRAM
componentsmay beused.When higher pixelrates
TS68483A
18/30

or up to 8 bits per pixel are required,the designer
must provide external shift registers. Video RAM
componentsmay also be considered.
In either case, the user must design :
- A memory block. This is the hardware memory
building block. It includes the video shiftregisters
if on-chip VSR cannotbe used.It implies a RAM
componentchoice.
- An Address Mapper,which maps the logical ad-
dress into hardware address : block selection,
RowAddress(RAD), Column Address(CAD).
- Amemory cycle controller. This controller moni-
tors the CYF and CYS output pinsfrom TS68483
and block addressfrom the Mapper. It provides :
- TheCLKsignaltothe TS68483andashift clock
SCLK when external video shift registers are
used
- RAS, CAS, OE, R/ W signals to the memory
blocks
- RADand CAD Enable signalsto the Mapper.
V.3.1- FRAME BUFFER (seeTable 6)
A byte wide organization of each bit plane is re-
quired. Obviously a bit plane must contain the
Display Viewport size. A straight organization im-
plementsonly one bit plane perblock.
It may be cost effective to implement several bit
planes per block. Two basic schemes may be
used :
- One block,one Z : severalbit planes, belonging
to different banks, butaddressedby the same Z,
share agiven block. There is little time constraint
if any.
- Oneblock,twoZ :twobitplanes,belongingtothe
same bank share a given block. In thiscase, this
block must be accessedtwice during a memory
cycle.Thiscanbe solvedbytwosuccessivepage
mode accesses.
Table 5 : MemoryCycle Types
Output Pins Function Modx Flags Multiplexed ADM Cycle Type
CYF1 CYF0 1 0 TA TO T1
1 0 Command Read Y,X Z0,Z2 Z1,Z3 Read
1 1 Command Write Y,X Z0,Z2 Z1,Z3 Write
01 Display 0
00 1Y,X Y,X Z0,Z2 Z1,Z3 Read
Dummy Read + 1
00 Refresh 1
10 1Y,X Y,Hi-Z Dummy Read + 2 Float X
Refresh : dummy read cycle isperformed.
68483-08.TBL
Table 6 : FrameBuffer Organization
Typical Block Size 16 k x 8 32 k x 8 64 k x 8 256 k x 8
One Block-one Bit Planes 512 x 256 512 x 512 1024 x 512 2048 x 1024
One Block-two Bit Planes 256 x 256 512 x 256 512 x 512
COMPONENTS : 64K BITS : 16K x 4 or 64K x 1
256KBITS : 32K x 8, 64K x 4, 256K x 1
VIDEORAM :64K x 1, 64K x 4
68483-09.TBL
Table 7 : The MultiplexingScheme
HIGHER BYTES
ADMS Multiplexed Pins 15 14 13 12 11 10 9 8
TA : Address Period 10 X 3
T0 : Even Z Byte Period 7 Z = 2 0
T1 : Odd Z Byte Period 7 Z = 3 0
LOWER BYTES
ADMS Multiplexed Pins 7 6543210
TA : Address Period 10 Y 3
T0 : Even Z Byte Period 7 Z = 0 0
T1 : OddZ Byte Period 7 Z = 1 0
68483-10.TBL
TS68483A
19/30

8
8 (T1) 8 (T0)
B0
B1
B2
B3
Z3 Z2
ADM [8:15]
8
8 (T1) 8 (T0)
Z1 Z0
ADM [0:7]
68483-19.EPS
Figure17 : One Block - One Z
Z3 Z2
ADM [8:15]
Z1 Z0
ADM [0:7]
88
(T0. T1) = Page mode
68483-20.EPS
Figure18 : One Block - Two Z
A MEMORYWORD
0
1
2
3
Z
76543210
X [0:2]
68483-21.EPS
Figure19
V.3.2- MASKINGPLANES
Maskingplanesareveryusefulforgeneralpurpose
areafilling orclipping.Itmay bepracticaltouseone
ortwo planessmallerthan thecolor bitplaneif they
cyclically cover a frame buffer.
The maskingplanes must be in bank3.
V.3.3- OBJECTS AND CHARACTERS
Objects may be located in unused parts of the
framebuffer.
Character generators can be implemented in any
planeof anybank. They can also be implemented
in ROM.In thiscase, plane Z = 1 or 3 offer relaxed
access time requirements.
V.4 - Examples
Figure 20. gives the schematic for a 512x 384 non
interlacedapplication.A CLK signalin the15 to 18
MHz range should produce a 50 to 60Hz refresh
rate. Theon-chipvideoshift registers maybe used
if nomorethanfour bits perpixel arerequired.One
64 Kx 8memory block may beimplementedusing
either eight 64 K x 1 or two64 K x 4 components.
One memory block holds two 512 x 384 color bit
planes.
TS68483A
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