Sharp Pc-2500 User manual

Table of contents

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SHARP

CORPOR

A

TI

O

N

1.

S

PECIFICA

TI

ON

B

US

Y

C

APS

7:1-t

DEF

R

UN

P

RO

TEXT

:

24

x

4 lines

(5

x

7

do

t matri

x

)

Graph

i

c

s

:

150

x

32

fu

l

l

d

o

ts

4

-col

or p

l

ot

t

er pri

n

ter

(

DPG

-

29

)

PR

I

N

T

RE MO

TE

P

O

WER

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r:n:::::::J

cra::::::J

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:

I

ON

/

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I

i

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i

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E=i

I

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OD

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t..:

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o Keyboard

layout

Scientific

functions

:

Trigonomet

ri

c

functions

,

inverse

t

r

igonometr

i

c

func-

t

i

ons

,

logar

i

thmic

functions

,

exponential

functions

,

angle

conv

er

sions

,

power

ri

sing,

roots

,

i

nteger

,

ab-

s

o

l

ut

e

valu

e,

s

ign

functions,

and

p

i

.

Ed

i

t

ing

f

u

nct

i

ons

:

Ve

r

tica

l

cu

r

so

r

cont

r

o

l

(~.

+--

)

Inse

r

tion

Dele

t

ion

Backspace

Line scroll

(

t

, .).

)

Softwa

r

e

:

o Sharp businesssoftware

o Table calculation

o Graph creation: Bar graph, broken

l

ine graph,

band graph, circular graph

o Telephone book

Memory

protection

:

Battery backup

(The contents

of

program, data, and reserveareasare

r

eta

i

ned during power

off

. )

o

Model

:

PC

-

2500

o Calculat

i

on

r

a

n

ge

:

10

d

i

git

s

(mantessa part)

+

2

di

gits

(exponent

i

al

part)

o

C

a

lcu

la

ting

method

:

Formula

ori

e

nt

e

d

(w

i

th

p

ri

orit

y

fu

n

ct

i

on)

o

Programm

i

ng

language

:

BASIC

o

CPU

:

Cmo

s

8

-

b

i

t microproc

e

ssor

o

Sy

s

t

e

m ROM:

72KB

o

M

e

mory

capac

i

ty:

System

area

:

About

1740

byt

e

s

Data

only

a

r

ea: 208

byt

e

s

Program

/

data

area

:

3102

byt

e

s

R

e

serve area: 79 bytes

o

Stacks

:

Subrout

i

ne

stack

:

10 stages

FOR

-

NEXT

stack

:

5

stages

Functional

stack

:

16 stages

Data

stack

:

8

s

tages

o

Fu

n

damental

ca

l

cu

l

ator

f

u

nctions

:

Calculat

i

ons

:

Four math rules

PC-250

0

MO

D

E

L

CODE:OOZPC2500S

I

ME

SERVICE

MANUAL

SHARP PC-2500

Th

e

ALL

RESET switch

has

to

be

depress

e

d

a

f

te

r

the

execut

i

on of the

te

s

t

program

be

c

aus

e

the

dat

a

a

nd

pro-

g

r

am in each ROM are not assured

of

its contents

a

fter

the

test.

ROM

t

o be

te

s

ted

K

ey

op

e

rati

o

n

O

K status

(RUM mode)

CPU

int

e

rnal

RO

M

CALL&802

A

I

ENTER

I

11147

(

8

KB

)

CPU enternal ROM1

CA

LL

&

80

2

7

I

E

NT

ER

I

1

01

27

(32K

B

)

CPU external

R

O

M2

CA

LL&

84

F

91

E

NTER

I

3

85

24

(32K

B

)

Internally

i

mplemented memory

te

s

t

program

The

check

s

um test

p

rogram ROM

i

s

conta

i

ned

inte

rnally to

te

s

t

t

h

e

BKB CPU

in

t

ern

a

l

ROM and 32KB x

2

external

RO

M

s.

2.

TEST

PRO

G

R

AM

FFFF

H

8

000H

7000H

6

00

0H

40

00

H

8

K

B

RO

M

(CPU

in

t

erna

l

)

I

7000

H

I

I

DI

S

P

1

I

8

K

B RAM

-

-

-

-

---

----

-

I

7

2

00H

ACK

1

l

Card

image

DI

SP

2

I

----

--

-

---

--

16 KB

I

740

0H ACK2

R

AM

card

1

D!

S

P 3

I

-

-

---

----

--

76

00H

A

CK

3

I

8

KB

R

A

M

I

DI

SP

4

I

Ca

r

d

-

---

--------

780

0

H

ACK

4

I

DI

SP

5

I

-

-

--

----

--

--

7

A

OOH

AC

K

5

4KB

RAM

K

E

Y

P

ORT

1

-

--

-

--

-

---

-

-

7C

OOH KEY

P

ORT

2

~--

-

_

__

-~~K_

6

_

7EOOH

8

000H

32

KB ROM

32

KB ROM

RO

M

1

ROM

2

B

A

SI

C

I

N

T

E

R

PRE

T

ER

Bu

n

d

led

s

oftware

2000

H

RAM map

OOOO

H

o

G

raph

p

rint

ing

:

A

bo

ut

11

tim

es

,

whe

n

t

he

g

ra

p

d

e

scribed in

P

ag

e

3

0

4

i

s

p

rint

ed

c

on

t

i

nuous

ly.

o

O

p

eratin

g

t

e

mperat

u

r

e:

5

to

40

°

C

o

Physical dimensions:

29

7(W) x 210(D) x 18

(dept

h

in

front)

and 45.5 (depth

i

n

rear) mm

o

Weight

.

About

1.3kg

o

Accessories

:

Tape recorder interfacing cable, AC

a

daptor

(EA

-

150).

write

pen (one each

of

black, blue,

g

reen

,

a

n

d

red

).

paper

rol

l

(one

roll)

,

i

nstruction manual.

-2-

S

e

rial 1/0

functions

Transmiss

i

on

method

:

Asynchronous

,

half

-

dup

l

e

x

mod

e

only

Baud

rate

:

300,

600

,

1200 bps

Parity

check

:

Odd,

even

,

n

one

Word

s

i

ze:

7

or 8

b

its

S

t

op

bit

:

1

o

r

2 b

i

t

s

Connector

:

15

-

p

i

n

conn

e

c

tor

fo

r c

o

nnection

w

it

h

external

dev

i

c

e

Output

si

g

nal level: CMOS level (4

~

6 volts)

Inte

r

fac

i

ng signals:

I

n

put

RD

,

CS,

CD

Output

SD,

R

S

,

RR, ER

Others

SG

,

FG, VC

• Auto

power

of

f

:

About

14

.

5

m

inu

t

es

•

Power

consumption

:

6V

.. ..

.

(DC

), 6W

•

Power

supp

l

y

:

In

t

e

rn

a

l

r

e

cha

r

ge

able

ba

t

te

r

y

(char

g

e

source

:

1

OOVAC

,

50

.

60Hz

,

with

the AC

adapto

r

EA

-1

50

i

n

use)

•

Re

c

hargeable battery operating

t

i

me

:

About

100

ho

u

r

s

o

Co

ntinu

o

us

d

i

splay

i

ng:

D

i

splaying

"5"

on 48 di

s

p

la

y

po

s

i

tions (2 rows) under the

te

mp

erature

of

20

°

C

.

o

I

ntermitte

nt

o

per

a

tion

:

Th

e

r

efreshed

batt

e

ry

w

i

ll last

for

about

1

.5

mont

hs,

when

op

er

at

e

d

o

n

e

hou

r

per

da

y

,

provided

that

c

al

cul

a

t

o

r operat

i

on

o

r

p

rog

rammed

operat

i

on

is

done

1

0

min

utes

out of

o

n

e

hour

w

i

t

h

t

h

e

rest of th

e

t

i

me (50

m

in

utes)

ope

r

ated to display,

without

operat

i

ng the

pr

i

nter

.

o Printer in operation:

About

450 digits

,

prov

i

ded

t

hat 20

di

g

its

of "5"

are

pr

i

nted continuously under the tem-

perature

of

20

°

C

with

the character size

"b".

Print

e

r

:

Pr

i

nt

e

r

typ

e

:

X

and

Y

axis

plott

in

g

P

rin

t

colors: 4 colo

r

s

of

blac

k,

bl

u

e

,

green

,

r

ed

(Op

tion

:

EA

-

850C

)

Cha

ra

c

ter

s

ize:

1

5

k

inds

of

0

.

8

mm x

1.

2m

m

~

1

2

mm

x

1

8mm

M

i

n

i

mum pen

mov

i

ng

d

i

stanc

e: 0.2mm

P

ri

n

t

speed

:

7

c

har

acte

rs/se

co

nd,

m

ax

imum (for

printing with

standard

cha

r

acter

si z

e

"

b

")

Record

i

ng paper. Paper

ro

ll

of

l

ess

t

h

a

n

25mm

diameter and 114mm

width.

(Opt

i

on:

EA-515P

)

Pen

mov

i

ng speed: 73mm

/

second

for

X

and

Y

dir

e

c

-

tions,

103mm

/

second

for

45

°

dir

e

ction

Do

t

si z

e

:

Display

:

Li

qu

id crystal display

1.

Text

display

5 x

7

dot

matri

x display (24

pos

i

tions x 4 rows)

Character size:

3.35(W

)

x 4.71

(H)

mm

Character

p

i

tch

:

4

.

08(W

)

x 5.44(H) mm

(s

i

ngle

dot

space)

2.

G

r

aphic display

150 x 32

f

ul

l

dots

d

i

splay

Dot

size

:

0

.

63 square

m

e

t

er

s

Do

t

p

i

tc

h

:

0

.

68mm

(

for both

d

irect

i

ons

)

-

PC

-

2500

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BLOCK DIAGRAM

-

PC

-

250

0

P

i

n

S

i

gn

a

l

I

n/

Ou

t

D

e

s

c

ript

ion

(

st

a

n

dby

=p

ow

e

r off)

N

o.

n

am

e

4

8 VB

In

LCD

pow

e

r

s

upply.

H

ig

h

d

u

r

ing

s

tand

b

y and VB

wh

e

n

clo

ck

st

op

s.

49 VDIS

In

LCD

pow

er

s

upp

ly

.

H

igh

du

ri

ng

sta

ndb

y and low

wh

e

n

c

l

o

c

k

s

top

s

.

50 VCC

In

L

CD

p

ow

er

su

ppl

y

.

Nor

mall

y

,

lo

w

.

51

voe

O

u

t

LCD

po

w

er

su

p

pl

y

.

Hi

g

h

duri

ng

s

t

and

b

y

a

nd low

whe

n

clock

sto

p

s.

52 VGG

In

P

ow

e

r

s

up

pl

y

.

N

or

m

ally,

l

o

w

lev

el.

53

0

7

In/

Ou

t

D

a

ta bus

lin

e.

N

ormally, high

i

mp

ed

a

nce

.

.j.

.j.

-

60

DO

In

/

Ou

t

Data bus

l

i

ne

.

N

o

rm

a

l l

y

,

h

igh

impe

d

a

nc

e

.

61

F05

Ou

t

32KB ROM1

chi

p

s

elec

t

ena

bl

e

sign

a

l.

A low on

t

h

i

s

lin

e

s

elects

the

R

OM1

.

62 F04

O

ut

SD

thro

u

gh

t

h

e

S

IO

wh

ich

is

a

tra

n

s

m

it

d

ata

.

Low

d

urin

g

standby

(

b

u

ff

ere

d

w

it

h

t

he 50H001

).

6

3

F

0

3 Out

D

at

a.

Tr

a

n

s

miss

i

on of serial

da

ta to

t

he

PC

U

.

6

4

F0

2

O

u

t

WAKE UP which

is

a PCU

st

art

r

eq

u

est

si

g

n

a

l

.

The PCU

w

ak

es up

which a

h

ig

h

s

t

a

t

e of

t

h

is

s

ignal

.

65 F01 Out

A

p

pl

i

cat

i

on ROM2

c

hip

se

lect

en

a

bl

e

signal. A low on this line selects

th

e

ROM2.

66 B08

but

RAM,

DIS

-

LSI enable signal

.

67 A14 Out

Addre

ss

bus

.

H

i

gh

du

r

ing

standby.

.j. .j.

-

80

A1

Out Address bus. High during

standby

.

-4-

P

i

n

S

igna

l

I

n/

Ou

t

D

escription

(standby

=

power off)

No. name

1

A

O

O

ut

A

d

d

ress bus, low during

standby

2

R

/

W

Ou

t

W

rite

clock

,

normally high

3

CP

A

L

Ou

t

L

ow

order

bi

t

add

re

ss

l

a

tch

si

gnal.

A

s

t

he

add

r

ess signal

i

s

carried

out

t

h

e

data

bus

wh

en a lar

g

e capacity ROM

is

used,

that

address

signa

l

(low

order

8

b

its

of

1

6 bits)

i

s

latched with

thi

s

signal.

4

TE

S

T

In

T

e

s

t

p

in

,

norm

a

lly

low

.

5

(/)

1

In

O

sc

il

lato

r

circuit input

6

(/J

O

Out

Osci

ll

a

t

or

c

i

rcuit

ou

tp

ut

7

R

E

SET

In

Rese

t

input

.

A

high on this line causes

to

r

e

s

et

.

T

h

e signal

is

normally pulled

dow

n

to

low level.

8

XLN In

I

npu

t

from

the data

re

c

order

option

(

EAR

jac

k)

9 KON

In

O

N/

B

RK key

i

n

put

.

Normally

,

pulled

down

to

low level.

1

0

X

OU

T

O

ut

Ou

tp

ut to

th

e data

recorde

r

option

(MIC jack)

a

nd

the

buz

ze

r

.

11

DIS

O

ut

LCD

dri

ver Control

sign

a

l

1

2 HA

O

ut LCD

d

r

i

v

e

r

cl

o

ck

.

L

o

w

d

u

r

i

ng

stand

by.

2KHz

pul

se

g

en

era

t

ed

w

he

n

th

e

d

i

s-

pla

y

is

op

er

ating

.

1

3

I

A

8

I

n

/

Ou

t

K

e

y and RAM

car

d

s

lot lo

c

k

sw

it

ch

i

n

put

.

Low

du

r

i

ng

sta

n

dby.

Pul

se

generat

e

d when a key

is

d

e

pressed

.

1

4 IA7

In/Out

Key

input/

key

strob

e

output

.

Low

during

standby.

Puls

e

g

en

erat

e

d

wh

e

n

a key

i

s

d

e

pressed

.

.j. .j.

-

20

IA1

In/Out Key

input/k

e

y

strob

e

output.

Low

during

standby

.

Pulse generated when

a key

i

s

de

pr

e

ss

e

d

.

21

I

B8

In

Busy signal. Seri

a

l

busy signal from

th

e

printer

c

ontro

l

IC

(PCU).

22 IB7

In

Low

b

attery

signal

([B)

which

is

an

i

nput

from the low

ba

tt

e

ry

det

e

ct

c

i

rcu

i

t

.

Normally, hi

gh

.

23 IB6

In

CD

t

hrough

the

SIO

whi

c

h

is

a

s

e

nd

request

from

t

he

othe

r

e

n

d.

Da

ta

are

r

e

ceiv

e

d

wh

e

n

th

e signal

i

s

in a

hi

g

h

s

tat

e

an

d

stopp

e

d when low.

24 IB5

In

CS

through

t

h

e SIO which

i

s

a

trans

-

missi

o

n

e

n

a

ble from

t

h

e

o

t

her

e

n

d

.

Transmi

s

sion

is

d

on

e

wh

e

n

th

e

si

g

nal

is

in a hi

gh

state

a

nd

sto

p

ped

w

heri

low

.

25 IB4

In

RD

th

rough

t

h

e SIO

wh

ic

h

i

s

r

e

c

ei

ve

data.

26 IB3

Ou

t

RR

th

rough

th

e SIO

w

h

ic

h

i

s

a

rece

i

ve

read

y

sig

n

a

l

fr

om

t

hi

s

sid

e.

H

igh

wh

en

r

eady

to

r

ece

i\1¬

and

lo

w

wh

en

n

ot

ready

t

o

r

e

c

ei

v

e.

2

7 IB2 Out RS

t

h

ro

u

gh

t

h

e SIO

wh

i

ch

is

a sent

re

qu

e

st from

t

h

is

sid

e.

Hi

g

h

dur

i

n

g

d

at

a

tr

an

smi

s

sion and low

whe

n

compl

ete

.

28

IB1

Out ER

throu

g

h

t

h

e

SIO

.

Go

es

hig

h

u

po

n

exe

cuti

o

n

o

f

t

he OPEN

c

om

mand

.

29 VM

In

LCD

p

ow

er

sup

p

ly

30 VA

I

n

LCD

p

ow

e

r

s

upply

31 GND

I

n

Pow

e

r

sup

p

ly

32

H1

Out LCD

bac

k

p

lat

e signal.

Hig

h

impedance

during

standby.

4

-

l

e

v

e

l

puls

e

du

r

i

n

g

displaying

.

.j.

.j.

-

47 H16 Out LCD back plate

s

i

gnal

.

High impedance

during

standby.

4

-l

evel

p

uls

e

dur

i

ng

displaying

.

4. SIGNAL DESCRIPTIONS

4-1. CPU

(SC61860A14

)

p

in

sig

n

al

descr

i

ption

-

PC

-2

500

-5-

NOTE

:

Voltage when

VDIS

is

7

.

OV

.

- -7.0V

..._

-5

.

6V

-

-

4.2V

-

-2

.

8V

-

-

l.

4

V

-

ov

.......

,.....;

:

r-«

V

A

~

VM

.__

VB

-

GND

·

VA

H-

f

VMH

-

I

*

Vsu..:I""

v"

f

/

5

VAL

-

t

I

VDI

s

%

Vn1

s

5

V

M

L

-

T

l

VDIS

V

D

I

S

-

5-

·V

BL- I.

Retain the

condit

i

ons

at

powe

r

off

.

LC

RE

SE

T

ON

h5

l~

'

--~

(

S

H2

6

:T

R5

)

ES

R.

H:T

R22

Power

off

(CPUat standby)

Disp

l

ay on

Display

off

DIS

Th

e

LCD

opera

te

s

i

n

1

/

16 duty.

• Timing

chart

80-p

i

n

R

ead

/

Writ

e

S63

(

S63

)

S62

(

S62

)

(

D

ispla

y

RAM)

D

I

SP

DR

I

VER

64

byt

e

(

00-3

F

)

64

by

t

e

(

40

-?F

)

64

byte

(

80-B

F

)

M M

SC

43537

gN

~

~~~~~~~~~~~~~~~~~~

;~

~

mmmmmmmmmmmm

m

w

m

mw

mmm

~

mmm

co

'

:

.

::'

B

V

B

S

1

S2

Q:;

)I

>

~

0

c

Q)

E

CJ)

Q)

Cf)

O

ss1

Q

S

s2

.

h

o

;

h

1:h

2:

h

J:h ,:

h

I

' '

'

V

ors

V

A

s:

u

(/)

:J

C/)

-

Q)

~

"O

"O

<(

'

C

E

R/W

,

:CON

TROL

0

1-8

~~---.

(La

t

ch clock)

¢AL

G

ND

V

GG

DIS HA

-

- -

-

--

-)}

- ·

<j>

-

~

-

4-2. Displaychip (SC43537) description

-

PC-2500

-6-

h

5

=

1

h5

=

0

A

ll digits

off

(

DIS=

L)

VAL VBH

O

n

VBL VAH

O

ff VAL

VBH

ON ON ON

ONOFFOFFOF!FdFFOFFOFFON

.

ON ON ON ON ON

O

N

O

N

O

F

F

All digits

o

f

f

V

DJ

S=VBL --

S

e

g

ment waveform

VB

H

-- ------~

B

ack

p

l

at

e

(

H1)

wa

veform

VMH

--

-

-

----

---

-

------

--

------

-

S

e

gment output waveform

Hl

H2 H3 H4 H5 H6 H7 HS H9

H1

0

Hl1H12H13Hl4

H1 H2 H3

H

4

H

5

GND=VAH

-

hl

(

TRl

)

h2

(

TR2

)

h3(T

R3

)

h4

(

TR4

)

h5(TR5)

HA

DI

S

RES

•

Co

u

nte

r

un

i

t

and

segme

n

t

wav

e

fo

r

ms

-

PC-2500

R

OMl

ROM2

DISPl

DISP2

DISP

3

DISP4

DI

SP5

RAME,

R

OME

M

,ROMEB

RAMl-6

K

OS

K07

K06

K05

K0

4

K03

K

02

K

Ol

OUT2

(

7J

7

LE

D

)

:

for

Japan

O

UTl

(

C

A

P

S

LED

)

R

E

O

F

F

REON

P

ACL

-

PC-2500

-7-

HL

~

I

VGG

~

G

ND

H

L-

----

-

--

-

----

-

-~

CL

F05

D3,

D2

R/W

D

l

I

I

...

I

r-

I I

i

I

I

...

I

--{)

...

....

I

,

I

I I

I

I

~

I

...

....

I

I

I

,

I

r

I

I I

I

...

I

-

I

!

I

I

I

I

...

I

...

I

I

...

....

I

I

...

I

I

...

r

I

....

I

...

..

I

.... ....

I

I

...

I

Data

l

atch

I

...

...

I

.

I

...

r

I

I

...

.

...

I

I

.

I

I

I

I

I

I

---

I

...

...

...

,

...

I

I

...

r

I

I

.

...

..

....

I

I

...

...

Address

d

e

code

r

...

....

....

~

..

....

I

I

....

...

...

r

I

I

...

...

...

-

I

I

I

,___

I

... ...

....

I

I

I

I

I

-

...

I

...

r

I

I

...

I

I

...

....

D

O

------1

BOS

AS

A9

AlO

All

A12

A13

A14

}

.

FOl

•

I

4-3

.

G

a

t

e

array (SC61J216F)

Th

i

s

LSI

contains the

RAM,

ROM

,

and

D

I

SP

chip

se

l

ec

t

s

i

gnal

decoder circuits

and key

s

trobe generating

circuit

.

P

in

S

ig

n

a

l

In/

Out

De

sc

ri

p

t

i

o

n

N

o

.

na

m

e

50

D

O

-

NU

51

Dl

I

n

Low

bat

t

ery

(

LB)

in

put

from

t

he low

ba

tte

r

y

detec

t

ci

r

c

u

i

t

.

N

or

m

ally

,

hig

h

le

v

e

l.

52

D

2

-

N U

53

D

3

I

n

S

e

ri

a

l

/pa

r

alle

l

in

t

e

rf

ace

se

l

ect

sig

n

al.

H

ig

h

:

ser

i

a

l

i

n

te

r

face

(lo

w

:

paral

l

el

i

nterface

).

54

NC

-

N

U

-8-

P

in

S

ig

n

al

I

n

/

Ou

t

D

escription

N

o

.

n

ame

1

D

4 In

B

it size

se

l

ect

signal.

H

ig

h

;

8-

bi

t

(l

o

w

:

7

-bit)

2 D5

In

CR code

f

unc

tio

n

al

assign

m

e

n

t

.

Lo

w

:

CR w

i

th LF

(

h

ig

h

:

C

R

onl

y)

3 D6

I

n

Char

ac

te

r

ki

n

d select

s

i

g

nal

:

Hi

gh: JIS

(J

5

to

be

sh

or

te

d

),

low

:

AS

C

II

(J6

to

b

e

sho

r

ted)

4 D7

I

n

P

ape

r

fe

e

d

(

PF

)

s

ig

n

al.

Lo

w

:

pa

p

e

r

feed,

h

ig

h:

pape

r feed

st

o

p

5

DB

-

NU

6 D9

-

NU

7

D

lO

-

N

U

8 Dl

1

Ou

t

Hal

t

ena

bl

e

sign

al

(

HAL

T

ENABL

E

)

9

D

1

2

-

NU

10

D

13

-

NU

11

D14

I

n

Da

ta

sig

n

al.

S

e

r

ial

data input

fr

om

the

CPU.

1

2

D

1

5

Ou

t

Bu

s

y

si

gn

a

l.

Se

ri

al

b

us

y

s

ig

nal

t

o

t

he

CPU.

13 R40

-

NU

(

-

-

(

R43

-

R50

-

R51

-

20 R52

-

NU

2

1

RST

-

Re

se

t

p

i

n

.

Reset

w

i

th a

hi

g

h

state

of

signa

l.

Normally,

pull

e

d down

t

o a low

state

.

22 GND

-

GND

2

3 OSCl In

O

s

cillator

circu

i

t input

24 OSC2

Ou

t

O

s

cillator circuit

ou

t

put

25 HLT In

2

6 TEST

-

GND

27

vcc

-

GND

28

ROO

Out GND

29 ROl

Out

GND

30 R02 In X/Y

motor

drive

fr

e

quency

s

e

lect

pin

.

High

:

365

pps

(low

:

325

pps)

31

R0

3 In

Charact

e

r kind

sel

e

ct signal.

High

:

CE515P

compatible

(DLG3301

E

char

ac

t

e

r

s

e

t)

32 RlO Out

Output during pow

e

r

on

SIGNAL OUT

3

3

R11 In

Input

duri

ng

p

o

w

e

r

o

n

SIGNAL

IN

34 R12 Out GND

3

5 R13 In

C

a

rriage

positio

n

dete

ct

swi

tc

h

s

i

g

nal

.

Low

:

ho

m

e

po

s

it

i

o

n

(lef

t

m

argin)

36

I

NTO In

Str

o

b

e

inp

ut

37 INTl In GND

38 R20 Out

}

-

-

-

X

mo

to

r

s

ign

a

l

41 R23 Ou

t

42 R30 Out

}

- -

-

Y

motor

sign

a

l

45 R33

Out

4

6 R60

Out

}

-

-

-

Z

motor

signal

49

R

6

3

Out

4

-

4. PCU (DLG3001

E)

pin signaldescription

-

PC-

2

500

-9-

a

.

F

/

F

reset pulse

width:

1msec

NOTE: At power

o

n

,

the flipflop

will be

rese

t

with

a

pulse from

the

C

-

R

network

.

A low

state of the

flipflop output

performs all clear

ope

r

ation

.

A

pow

e

r

on reset

output

is

sent out at the

begin

-

n

i

ng of

the

all

clea

r

operation to

reset

the

flipflop

.

Pulse added

to the

RST

p

i

n

the

r

eafter

w

i

ll

not

be assumed as

the

a

ll

clear

s

i

gna

l.

(5) Al

I

clear

operat

i

on

(

F

ig

.

1)

1

.

Pulse

i

s

added

to

Q)

in

order to

perfo

r

m the same

action

as

at

powe

r

on

.

2. Pulse

i

s

added

to

(8)

fo

r

a

wake up by releasing

the

halt condition.

3

.

Hardware

is

reset by adding a pulse

t

o

the

RST

termin

a

l

(G).

With

the

abo

ve

operation

,

it

i

n

sured

a

ll

clear

op

e

ra

-

ti

o

n

even

if

there

was an error in

the

program

due to

nois

e

.

1!9

P

O

WER ON TEST

IQ

POWER ON RESET

~

J

f------

-----

--

L_

Power on

_jt

_

®

---

Q)

R

e

s

e

t

Power on

reset

t

i

ming

(F

i

g

.

1)

(4)

-

PC-2500

NOTE-1

:

Once it goes

into the halt

state

,

arrival of

a

wake up pulse will be disregard in

this

period.

NOTE

-

2

:

"

IOm

s

.

TYP"

is

dependent

on

the factor

of

the

C

-

R

network

.

Condition

required

for the

LSI

to

operate

normally

i

s

4mse

c

,

minim

u

m.

NOTE

-

3

:

A

wa

i

t time

until it

g

oes

into the halt state after

completion

of

data

processing,

w

ith no more

data to

receive

.

@ Wake up

disre

g

ard

p

e

riod

(NOTE

-

1)

20ms

e

c

@ Halt

r

e

set

-»

start

of

ope

r

ation (NOTE-2)

10ms

e

c

©

Ha

l

t

wait period

(NOTE

-

3)

120ms

e

c

Th

is

wake up

is

disregarded

.

NOTE: The

on/off state of

th

e PF switch

is

checked once

in

a

bus

y period

(3msec)

.

(3) Halt

control

si

gn

al

timing

(Fi

g.

1)

Busy period

3msec

3msec

R

e

ady period

®

Read timing

----i__s-

'-----1----

1

~

Paper feed

perio

d

©

PA

P

ER FEED

@BU

S

Y

(2) PF switch sense

tim

i

ng (Fig.1)

®

On

e

da

t

a

l

e

ngth

8.33ms

e

c

@ One

b

i

t

length 833

µs

e

c

©

S

t

art

bit

ri

s

in

g

e

d

qe

-»

11

Oµ

se

c

busy

s

ign

al ri

s

ing

e

dge

®

O

J

''°':''''td

@

B

US

Y

~ I__

© "O" level

®

•m.c ""' ~

1

°

1

•

l

•

l

•

l

•

[

•

[

•i

I

@

"

1

" level

S

t

a

rt bi t

8-b

i

t

s

e

r

i

al

print data

ar

e

received

fr

o

m

the

CPU

to

be

pr

i

nted.

(1)

Se

r

ial

i

nterface

timing (Fig.1.)

-

5.

D

E

SCRIPTION OF THE PRINTER

CONTROL CIRCUIT

-

10

-

Mo

tor

Moving

di

r

ection

St

e

p A

B

c

D

shaft

No

.

r o

tat

i

ng X-axis Y-axis

Z

-a

xi

s

d

i

rection

1

ON OFF

O

FF

O

N

C

ount

e

r

-

+ + +

2

OFF ON OFF

O

N

clock

-

3

OF

F

ON

O

N

O

FF

wise

C

lock

-

Reverse Pen

ON

OF

F

ON

OF

F wise

direction

up

4

(

2) Drive pulse

tra

i

n

I

t

e

m

P

hase

C

olor

W

iring

di

ag

r

am

Turns

a

ct

i

v

e

at

the

l

e

ft

margin

(h

om

e

positi

o

n)

B

G

ray

1

c

s

0 o~

I

C

a

rr

ia

ge

p

o

s

itio

n

d

etector

A

Y e

ll

ow

2

VGG o

D Red

3

XD

-

uu

-

c White

4

xc

-

uu

X-

a

x

is

d

r

ive

motor

-

(

ca

rriage

mo

v

ing

directio

n

)

B

Blue

5

XB

-

00

-

A Yellow

6

XA

-

vu

-

COM

Bla

c

k

7

GND o

D

Red

8

YD

-

vu

Y

-

axis

d

ri

ve

motor

c While

9

YC

-

(pap

er feeding

dir

e

ct

i

on)

-

B

Blue

10

YB

o

o

A

Ye

llow

11

YA

-

D

Red

12

ZD

00

Z

-a

x

i

s

d

r

i

v

e

moto

r

Wh

i

t

e

13

zc

uv

(

p

e

n

u

p

/

do

wn and

c

olor

c

cha

n

ge)

B

B

l

ue

14

ZB

-

00

A Yellow

15

ZA

uv

-

PC

-

250

0

®

VGG

(

-

5

)

(

l-IH

)

I

F0

3

'

DAT

A

36 35

I

N

TO

R

l 3

®

26

I

BB

'

T

E

ST

B

U

SY

27

(

1-IH

)

VCC

38

N U

D2

R20

32 39

Rl

0

R

21

33

4

0

NU

R

l

1

R22

Ci)

23

41

TC

R23

2

4

4

2

®

R

3

0

R3

1

CD

P

C U R

32

1

OOP

1

OO

P

R

33

PA

C

L

--1

(1-

1

H

J

D

B

I

__

DLG300

1

E

DAP202

GND

(

O

)

D9

N U

D10

G

ND

1

9

R52

R6

0

CD

L

'

:

R53

R6

1

D

12

R

62

1

OOK

10

4

9

Dl

3

R63

5

4

2 9

NC

R

O

1

30

2 8

R02

ROO

3

7

53

D3

D4

R

0

3

D

6

®

R

l 2 D5

2

1

51

RS

T

Dl

5

0

D

l

1

DO

N

U

©

22

0.

1

G

ND

D7

GND

(

0

)

G

N D

I - I

I

I

1

O

OK

L

_J

1

H

DA

P

20

2

1

OOK

X

2

©

V

GG

(

-

5

)

VGG

(

!

-3

G)

PF

F

ig-1

6.

DESCRIPTION OF PRINTER OPERATION

(

1) Printer connector wiring