Shugart SA100 User manual

TABLE OF CONTENTS
1.0 Introduction ....................................................................... 1
1.1 General Description .............................................................. 1
1.2 Winchester Technology
............................................................ 1
1.3 Specification Summary
............................................................ 2
1
.3.1 Physical Specifications .......................................................... 2
1.3.2 Reliability Specifications
......................................................... 2
1.3.3 Performance Specifications
....................................................... 2
2.0 Theory ofOperation
................................................................. 3
2.1 Introduction ..................................................................... 3
2.2 Power
On Reset Circuit ............................................................ 3
2.3 Drive Ready (Control PCB/Stepper
PCB) ............................................... 4
2.4 Auto Recal (Stepper Logic
PCB) ..................................................... 4
2.5 Stepping
....................................................................... 4
2.5.1 Buffered Mode Stepping .......................................................... 4
2.5.2 Normal Stepping
................................................................ 7
2.6 Stepper Driver(Control
PCB) ........................................................ 7
2.7 Read (Control
PCB, Refer to Figure 3) ................................................. 7
2.8 Write
.......................................................................... 8
2.9 Error Detection (Control
PCB) ....................................................... 8
LIST OF ILLUSTRATIONS
Figure 1. Typical Step Rate Ramp Curve ................................................... 5
2. Step Timing .................................................................. 6
3. Read Channel Block Diagram .................................................... 7

1.0 INTRODUCTION
1.1 GENERAL DESCRIPTION
The Shugart Model 1000 series disk drive is a random access storage device with one or two non-remoyable
8" disks as storage media. Each disk surface employs one movable head to service 256 data tracks. The
two models of the
SA 1000 series are the SA 1002 and the SA 1004 with single and double platters respective-
ly. The SA 1002 provides 5 megabytes accessed by 2 movable heads and the SA 1004 provides 10 megabytes
accessed by 4 movable heads.
Low cost and unit reliability are achieved through the use of a unique band actuator design. The inherent
simplicity of mechanical construction and electronic controls allows maintenance free operation throughout
the life of the drive. .
Mechanical and contamination protection for the head, actuator and disks are provided by
an impact resis-
tant plastic and die cast aluminum enclosure. A self contained recirculating system supplies clean air
through a 0.3 micron absolute filter. Another 0.3 micron absolute filter allows pressure equalization with am-
bient air without chance of contamination.
The
SA1 000 fixed disk drive's interface is similar to the Shugart 8" family of floppy disk drives. The SA1000
is designed to fit into the same physical space as the 8" floppies. However, existing floppy controllers are
not compatible with the
SA 1000 due to differences in the data transfer rates.
Key Features:
Storage Capacity of 5.33 or 10.67 megabytes.
Winchester design reliability.
Same physical size and identical mounting configuration as the SA800/850 floppies.
Uses the same
D.C. voltages as the SA800/850 floppies.
Proprietary Fas Flex III band actuator.
4.34 Mbits/second transfer rate.
Simple floppy-like interface.
1.2 WINCHESTER TECHNOLOGY
The SA 1000 disk drive employs Winchester technology. The term Winchester refers to several unique
features about the drive. They are:
* Environmentally sealed chamber for heads and disks.
* Disk surface lubricated to facilitate magnetic head take off and landing without damage to the media
(The heads can land randomly anywhere
on the surface of the media).
* A head that flies 19 micro inches above the surface of the media.
* Reduced head load force of 9.5 grams which allows the heads to rest on the surface of media prior to
take off
(The spindle speed for head take off is approximately 500 rpm). .
The close proximity of the heads to the recording media permits recording densities of 6270 bits-per-inch.
This recording density allows 10 megabytes of data to
be stored on an 8-inch drive. Sealing the chamber that
houses the disk and head assemblies prevents contaminants from reaching the disk surface. The 0.3 micron
absolute breather and recirculating filters keep the environment inside the chamber free from undesirable
particulate contaminants.
UNDER
NO CONDITION MUST THE DRIVE BE UNSEALED IN THE FIELD. A CLASS 100 CLEAN ROOM EN-
VIRONMENT IS NEEDED FOR UNDER-THE-BUBBLE REPAIR.
1

1.3 SPECIFICATION SUMMARY
1.3.1 PHYSICAL SPECIFICATIONS
Environmental Limits
Ambient Temperature =
Relative Humidity =
Maximum Wet Bulb =
50° to 115°F (10° to 46°C)
BO/o to BO%
7BoF non-condensing
AC Power Requirements
50/60 Hz ± 0.5Hz
100/115 VAC Installations =
200/230 VAC Installations = 90-127V at 0.75A typical
1 BO-253V at 0.3BA typical
DC Voltage Requirements
+24VDC ± 10% 2.BA typical during stepping
(0.2A typical steady state, non stepping)
+5VDC ± 2.0A typical during stepping
(3.6A typical non-stepping)
-5VDC ± 5% (-7 to -16VDC optional) .2A typical
Mechanical Dimensions
Rack Mount Standard Mount
Height = 4.62
in. (117.3mm) 4.62 in. (117.3mm)
Width =
B.55 in (217.2mm) 9.50 in. (241.3mm)
Depth = 14.25 in. (362.0mm) 14.25 in. (362.0mm)
Heat Dissipation =
511 BTU/Hr. typical (150 Watts)
1.3.2 RELIABILITY SPECIFICATIONS
MTBF: B,OOO POH typical usage
PM: None required
MTTR: 30 minutes
Component Life: 5 years
Error Rates: Soft Read Errors:
Hard Read Errors:
Seek Errors:
1 per 10
10
bits read
1 per
1012 bits read
1 per 106 seeks
1.3.3 PERFORMANCE SPECIFICATIONS
Capacity SA1002 SA1004
Unformatted
Per Drive 5.33 Mbytes 10.67 Mbytes
Per Surface 2.67 Mbytes 2.67 Mbytes
Per Track 10.4 Kbytes 10.4 Kbytes
Formatted
Per Drive 4.2 Mbytes
B.4 Mbytes
Per Surface
2.1 Mbytes
2.1 Mbytes
Per Track
B.2 Kbytes
B.2 Kbytes
Per Sector 256 bytes 256 bytes
Sectors/Track
32
32
Transfer Rate 4.34 Mbits/sec 4.34 Mbits/sec
2

Access Time
Track to Track
Average
Maximum
Average Latency
19 msec
70 msec
150 msec
9.6 msec
1.3.4 FUNCTIONAL SPECIFICATIONS
Rotational Speed
Recording Density
Flux Density
Track Density
Cylinders
Tracks
R/W Heads
Disks
3125
rpm
6270 bpi
6270 fci
172 tpi
256
512
2
1
2.0 THEORY OF OPERATION
2.1 INTRODUCTION
19 msec
70 msec
150 msec
9.6 msec
3125 rpm
6270 bpi
6270 fci
172 tpi
256
1024
4
2
This section will functionally describe the major circuits of the SA1 000. For interface timing, refer to SA1 000
OEM manual PIN 39010.
2.2 POWER ON RESET CIRCUIT (POR)
In order to generate a -paR (Power on Reset) signal, a simple switching circuit on the control PCB is used.
This circuit utilizes capacitor
C4, transistor 05 and two biasing resistors R67 and R68. When initial D.C.
voltages are applied to the drive, C4 charges up from 0 volts preventing 05 from turning on. This establishes
a low
at the .output of IC 5C. It takes approximately 50ms for C4 to charge up enough to turn on 05. Once 05
is turned on, IC 5C8 will remain high until power is removed.
The following latches are cleared during the power-on phase:
Resets the fault latch,
6D on the Control PCB.
At the stepper PCB - paR loads counter chip 3F with a hex count of 3, which is translated at the de-
coder chip
2F to OA
2,
OB
1 (phase
A).
Resets the seek complete latch 2A, allows seek complete to be active at the interface if the
read/write heads are located at Track 000.
Sets the Auto-Recal latch 3C on the stepper PCB.
-Clears the step enable latch, 1C on the stepper PCB.
-Loads track count buffer IC's 5E and 4B to a hex count of FF on the stepper PCB.
After the reset initialization is completed the drive waits for the ready condition to occur.
3

2.3 DRIVE READY (CONTROL PCB/STEPPER PCB)
The drive ready condition occurs when the disk spindle speed is above 9S
o
/0 of its nominal velocity (@ 2968
RPM's). The ready circuit is derived by comparing the time between two successive index pulses to a fixed
time reference. The index detection circuit consists of
an op amp differentiator and a one shot schmitt trig-
ger. A zero detection at the output of the differentiator circuit would generate a
10p,s pulse at the output of IC
7B7. The frequency of the index pulse is depended upon the rated rotational velocity of the disk. The fre-
quency period
is equal to 19.2ms when the disk is rotating at the rated speed (312S rpm).
At the Stepper
PCB an active low index signal presets the parallel inputs to counters 1E and 2E. These
counters are clocked by a
271 Khz signal. It takes approximately 20 ms for 1Eand 2E to overflow. A low, out
of counter 1
E14, resets speed latches 1D and SF. The speed latches will remain cleared if the time between
two index pulses
is greater than 20.04 ms, indicating a not ready condition. When the disk is rotating above
9S
o
/0 of its nominal rotational speed, incoming indexes will preset 1E and 2E before they time out. The next
index signal will set latch
SF and SF6 will go low indicating an active ready condition.
2.4 AUTO RECAL (STEPPER LOGIC P.C.B.)
An Auto Recal is performed if two basic conditions are satisfied: One is that drive ready has to be in the ac-
tive state, and the other
is that the heads must not be positioned over track zero. Assuming that these condi-
tions are met, the following logic functions are performed. The Index signal
is gated through IC's 3C and 4F.
The Step Enable signal is in the inactive state, which allows the index signal to be used as a pseudo step
signal.
The Auto Recal latch (3C) is currently in the set position, indicating the direction of motion of the
read/write heads will begin to recalibrate
in the normal mode of operation until the track zero phase (phase
A) is detected. The seek settle timer 1 Band 2B will time out in approximately 18ms, activating Seek Com-
plete at the interface. The drive is now ready for normal operation.
2.5 STEPPING
The STEP interface line is a control signal, which causes the read/write heads to move in the direction defin-
ed by the DIRECTION IN line. The Direction In line must be stable at least 1 OOns before the leading edge of
the Step pulse.
There are two basic modes of operation of stepping the read/write heads, the normal mode and the buffered
mode.
In order to implement either of these two modes of operation, there are several conditions that must
be initiated before stepping can be accomplished.
1. Write Gate must be inactive.
2. Drive Select must be active.
3. Ready must be active, and Seek Complete true.
2.5.1 BUFFERED MODE STEPPING
In this mode, the step pulses are received at a high rate (pulse period separation between 3.0p,s and 200p,s),
and buffered into step counters 4B and SE. Once all step pulses have been received, s"'tep rate timer SA 14
will output a low, which
is gated through IC's 3D1 0, 3ES and 4FS. This logic function is used to prevent any
more step pulses from being received.
The actual stepping operation will now begin, depending upon the step count loaded into the step count buf-
fers, 4B and
SE. For discussion, assume a 20
10 track seek operation.
4

Counters 48 and 5E will hold a count of 316 and 116 respectively. The count of IC 48 will be compared to the
count of
IC 3A (this count currently equals zero). Since IC 48's count is greater than the count of IC 3A, IC
4A, Pin 5 will output a logical one. A high signal out of 4A will select the outputs from counters 3A through 38.
This particular count will
be used as an address to prom 58. The firmware control for each address is design-
ed to select the appropriate step rate time (see figure 1). The approximate time for the fi rst step rate is 200l!s
(Prom address 1610) .and the second step rate time is approximately 560l!s (Prom address 17
10), The output
from
IC 5A, Pin 14, will clock the divide-by-2 flip flop at 1 D. The output (low to high transition) from the flip flop
(IC 1 D, Pin 9), has several important functions:
Enables the 141!s window generator circuit (step enable signal).
Enables sequencing from the phase counter.
The phase counter will either count up or down depending upon the direction line. (For phase
counter timing see figure
2).
Enables the down count from counter 48.
The step count from counter 48 is continuously compared to the count of 3A, until 3A becomes greater than
the count of 48. At this time data selector
38 will select the lower value step count of IC 48. Slower and
slower step times are selected (ramping down) until the step time is at the rate of the initial step.
For longer seeks, the step speed will increase (ramp up) during the first 15 steps, until the maximum step
speed
is reached. The speed will be maintained until only 15 steps remain. Now the step speed is decreased
(ramp down) gradually down to the initial 1120 usec rate. The purpose of ramping up is to decrease the total
seek time, and the purpose of ramping down is to slow the stepper mass down in order that a settle time of
18 msec, can be maintained.
18
16
14
12
10
STEP
COUNT 8
6
4
2
o~ __ ~ __ ~ ____ ~ __ ~ __ ~ ____ ~ __ ~ __ ~ ____ ~ __ ~ ____ ~ __ ~
o 100 200 300 400 500 600 700 800 900 1000 1100 1200
TIME IN MICRO SECONDS
FIGURE 1. TYPICAL STEP RATE RAMP CURVE
5

GENERAL STEP PHASE TIMING
OA
I
l-
I I I I I I
081
I I I I I I I I L,/I
I I I I I I I
ocl
I I I I I I I I
I
Sf-
I I I I I I I I
1Yo U I I U I I U I I
I I I I I I I I
1YI I U I I U I U I
I I I I I I I I
I U I I U
LIT
1 Y2
I I
I I I I I I I I I
1 Yl
I I I U I I I U I U
I I I I I I I I I
I I I I I I I I I
-081 I I
I I I I I I
-082
I I I I I I I
·1
I I I I I
-OA2
I I I I I
I I I I
-OAI I I
I
(AI) (AI81)(81)(A281)(A2)(A282)(82) (AI82)
TRUTH TABLE FOR PHASE SEQUENCES
ij
OC 08
OA -OAI -081 -OM -082
a 0 a a 1 1
a 0 1 a a
a a a 1 1
r 1 a a
11~PHASEA
~ 1 0 a a 1
a: 1 0 1 a a
~
w 1 a 1 a
w
(/), 1 0 a
FIGURE 2. STEP TIMING
6

READ/WRITE
HEAD
HEAD
SELECT
LINES
B
U
F
F
E
R
fr SA1002}
2 SA1004
3
FILTER
NETWORK
FILTER
AND
AJD
~--t CO~~ERT-
FIGURE 3. READ CHANNEL BLOCK DIAGRAM
2.5.2 NORMAL STEPPING
,...----. TP5
DROOP
IGNORE
CIRCUIT READ
_____ DATA
Normal seeking entails exactly the same sequence of events as the Buffered Step Mode with the only dif-
ference being that only one step pulse is loaded into the Step Buffer, and the rate of stepping is considerably
slower. In this mode of operation the read/write heads will move at the rate of the incoming step pulses. The
pulse width is 3p.s minimum and the minimum time between successive steps is 1.Sms.
2.6 STEPPER DRIVER (CONTROL P.C.B.)
The stepper driver- circuit
is enabled by a low active enable step signal. The phase signals are entered via
cable J9, and are gated through open collector type drivers. For discussion purposes, assume that phase A2
is active, this signal would turn on 018 and 022 respectively, allowing the 24v Darlington switch to pass cur-
rent through
022 (low impedance), and to the A2 coil phase of the stepper motor. The activated A2 phase will
also cause
010 and 027 to turn on. The amount of current flowing through the Phase A winding is regulated
by a switching regulating circuit consisting of SA2, 4B1, 014 and 016. The current is monitored at a summ-
ing node and at the voltage comparator SA2. If the current becomes too high, comparator SA2 will switch,
turning off 014 and 016. This prevents any current from flowing through the phase A2 motor coil. In this
mode the SA2 comparator will switch on and off as required. Transistors 021 and 028 are in the off mode
providing a high impedance path for current to flow from 021 into the
A1 phase winding. This prevents any
other phases from becoming activated. Once the desired cylinder has been reached + REF seek complete
will go true turning on 029 and enabling +Svolts to hold the stepper motor in position. The limiter 6A2 is ac-
tivated and it regulates current flow to the motor coil.
2.7 READ (CONTROL PCB, REFER TO FIGURE 3)
In order to initiate a read operation the following conditions must be satisfied:
- A selected drive.
Drive Ready Active. \
A selected head.
Write gate inactive.
All Fault conditions cleared.
-Seek complete.
7

The read operation begins with raw read data flowing through the selected head. Resistor R1 (4300) pro-
vides read damping necessary for the detection of flux transitions, and also provides the necessary im-
pedance matching between the read/write head and the first amplification stage. The first stage of the read
channel consists of isolation transistors 02 and 09, and protection diodes( CR9 and CR10). Differential
amplifier 2F functions as a high pass filter allowing any frequency above 15 Khz to pass through, and the 4
pole Bessel filter acts as a low pass filter allowing only frequencies below 5.3 Mhz to pass through. Tran-
sistors
03 and 04 act as an active impedance matching network to the final stage of signal amplification.
The final stage of amplification consists of a differential op amp, which allows only frequencies below
22
Mhz to pass. Typical amplification for the total read channel is 104 for 1F and 97 for 2F frequency. A 2 pole
Bessel filter with a corner frequency at 3.3 Mhz
is inserted between 3F and 5F for additional droop reduc-
tion.
The amplified raw data is digitized by a zero crossover detect one shot (8T20). The delay created by the
one shot at location
7B is used to delay erratic data long enough to be out of the window created by the com-
bination of
IC 7F and IC 6F11. The output of 6E3 (or TP 5) is the digitized droop ignore circuit (noise ignored).
The digitized read data
is then gated to the interface.
2.8 WRITE
In order to initiate a write operation the following conditions must be satisfied:
-Write gate
on.
Ready.
Drive selected.
Head selected.
No fault conditions.
Seek complete.
Assuming that the above conditions are satisfied a Write operation will be initiated. The write operation
begins with
an active Write gate signal at 409. Write Gate active will turn off the read detector, and turn on
transistors 06 and 2C8, 9, 10, allowing current to flow through the write current sense line. Current flow is
limited by three 1% resistors R22, R23 and R24. If the cylinder is less than 128, Reduce IW signal should be
in the inactive state, which allows an extra 10 ma to flow. When the cylinder count becomes greater than
128, Reduce
IW should be activated, turning off transistor 2C12, 13, 14 preventing current from flowing
through R22, thus reducing the amount of current by approximately 10 mao Current flow is monitored by
+ IW Sense Signal. This Signal alerts the control circuitry that an Write operation is being performed. Write
data
is gated to F/F 50, which divides the write data. In this mode write current will be switched by alternate-
ly turning 2C on and off. Write data will be written to the head whose center tap has been selected by the
decoder
IC (1 C).
2.9 ERROR DETECTION (CONTROL P.C.B.)
The fault Signal is used to inhibit improper writing on the disk. There are two basic fault conditions that are
detected. They are:
1. Write Current in the heads wihtout Write Gate active.
2. Multiple heads selected.
Fault condition 1 will set latch
60, preventing any data from being written on the disk. Fault condition 2 will
also set latch
60, indicating more than one head has been selected. In order to reset any fault condition the
drive select line must
be inactive for at least 500 ns or until a power-on-reset is applied.
8

TABLE OF CONTENTS
1.0 Troubleshooting Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9
1.1 Philosophy.. . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Equipment Required . . . . . . . . 9
1.3
PCB Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9
1.3.1 Control PCB Test Points. . . . . . . . . . . . . . . . ..................... " 9
1.3.2 Stepper
PCB Test Points. . . . . . . . . . . . . . . . . ................................ " 9
1.4 Troubleshooting Flowcharts . . . . . . . . . . . . . . . . . .
.................................. 10
2.0 Drive Motor/Pulley/Belt Removal Instructions
............................................ 20
2.1 Drive Motor/Pulley/Belt Installation Instructions ..... " ................................ 20
2.2 Special Equipment ...... ..................... ................................ 23
2.3 Index Transducer Adjustment Procedure . . . . . . .................................... 23
2.4 Damper Removal/Installation Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ...... 24
2.4.1 Damper Removal Procedure ..................................................... 24
2.4.2 Damper Installation Procedure .... . . . . . . . . . . . . . . . . . . . ........... 24
2.5 Track 000 Flag Assembly Installation and Removal . . . .......................... 25
2.5.1 Track 000 Flag Assembly Removal . . . . . . . . ........................ 25
2.5.2 Track 000 Flag Assembly Installation. . . . . .
.......................... 25
2.6 Track 000 Adjustment Procedure . . . . . . . . . . . . . . .. . .......................... 25
2.6.1 Track 000 Alignment Procedure. . . . . ................................... 25
3.0 SA 1000 Jumper Options. . . . . . . .......................................... 27
LIST OF ILLUSTRATIONS
Figure 4. Index Signal. . . . . . . . . . . . . . . . . . . . . . ................................ " 9
5. Enable Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9
6. System Clock. . . . . . . . . . . ................................. " 9
7. SA1 000 Cover. . . . . . . . . . . . . . . . . . . . ................................. 21
8. SA1000 . . . . . . . . . ................................... 22
8a. Drive Motor Pulley Adjustment . . . . . . . . . . . . . . . . . . . . . . .
.. . ............... 23
9. Index Pulse . . . . . . . . . . . . . .. . . . . . . . . . . . . . ............ 23
10. Damper Removal. . . . . . . . . . . . . . . . . . . . . . . . . . .......................... 24
11. Damper Installation. . . . ................................................... 24
12. Track 000 Flag Collar
........................ . ........................... 26
13. Track 000 Flag Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 26
14. Track 000 Flag Alignment . . . . . . . . . . . . . .
.. . ............................... 26
15.
SA 1000 Control PCB . . . . . . . . . . ................................ 27

1.0 TROUBLESHOOTING TECHNIQUES
1.1 PHILOSOPHY
The following troubleshooting techniques are designed to aid field service personnel in locating a drive fault
down to the circuit level or to determine that the drive is not field repairable, in which case the drive must be
repaired at a depot facility. '
1.2 EQUIPMENT REQUIRED
1. A power supply capable of generating the following voltages:
+5 volts @ 3.6 Amps
-5 volts @ .2 Amp or (-7 to -16 VDC optional)
+24 volts @ 2.B Amps
2. Oscilloscope -Tektronix 465 or equivalent
a. Probes: X 10 2 each
X 1 1 each
b. clip-on current probe
3. Digital Multimeter -HIP 3476B or equivalent.
1.3 PCB TEST POINTS
1.3.1 Control PCB Test Points
2 INDEX SIGNAL 19.2 ms (Fig. 4)
3 DIFFERENTIATED READ DATA
4 DIFFERENTIATED READ DATA
5 DIGITIZED READ DATA
6 TRACK 000 FLAG
1, LOGICAL 1 = TRK 000
7 WRITE GATE
B ENABLE STEP (Fig. 5)
9 WRITE DATA MFM
1.0 SEEK COM PLETE
11 GROUND
(BF-9) SYSTEM CLOCK 3.69p.sec (Fig. 6)
12 READ DATA
14 GROUND
15 GROUND
FIGURE 4. 2V/div 5 ms
1.3.2 Stepper PCB Test Points FIGURE
5. 21'S SEQUENCIAL SEEK 2V/DIV 2p.S/DIV
1 STEP COMPLETE (LAST STEP)
2 GROUND
3 GROUND
5 STEP RATE SIGNAL
FIGURE 6. 2V/DIV 1p.s
9

1.4 TROUBLESHOOTING FLOWCHARTS
The interface signals utilized by various flowcharts may be generated by the host system/controller through
its own diagnostic routines.
FLOW CHARTS
¥Test entry point
o Perform test indicated
o Test is completed successfully go to next test.
HAC POWER TEST"
"TEST A"
PRELIMINARY NOTES:
1. CHECK DRIVE VOLTAGE AND FREQUENCY SPECIFICATIONS
BEFORE SUPPLYING AC POWER TO THE DRIVE.
CHECK FOR
PROPER AC
VOLTAGE (rl J4
CONNECTOR
REPLACE AC
MOTOR
IF DISK DOES NOT
ROTATE PROPER-
LY AFTER REPLAC-
ING DRIVE MOTOR,
THE DRIVE
SHOULD BE
RETURNED TO
DRIVE DEPOT
10
REPLACE AC
POWER CABLE
CHECK AC
SOURCE
REPLACE DRIVE
BELT
A

PRELIMINARY NOTES:
1. CHECK REGULATOR JUMPER
OPTIONS ON CONTROL PCB
FOR CORRECT POSITION.
(·5V OR ·15V)
NOTE: IF LSI
CHIP IS
INSTALLED THEN TEST
#1 NEED NOT BE
PERFORMED.
"DC VOLTAGE TEST
"TEST
B"
CHECK FOR + 5
VOLTS (it
STEPPER PCB
FLAT RIBBON CABLE J9
TEST #1
YES
TEST
#2
PINS
19
21
24
1·17 (ODD)
RECHECK .19 AT
CONTROL PCB IF RIBBON
CABLE OKAY
CHECK FOR+ 5
VOLTS@ J5
REPLACE FLAT
RIBBON CABLE B
.,19
CONNECTOR ALSO TEST #3
CHECK OTHER DC
VOLTAGES
REPLACE
STEPPER
PCB
J5 PIN
REMOVE P5 FROM
CONTROL PCB &
RECHECK DC TEST #4
VOLTAGES
CHECK SYSTEM
REPLACE CON·
TROL PCB
POWER SOURCE TEST #5
REPLACE SYSTEM
POWER SOURCE
1
2
3
4
5
6
REPLACE .,15
CABLE
VOLTAGE
+ 5V
+ 5V
+ 5V
GROUND
1-----' B
VOLTAGE
+ 24 VOLTS
+ 24 RETURN
·5 RETURN
·5 VOLTS
+5 VOLTS
+5 RETURN
t----~ B
NOT A DRIVE FAULT: CHECK FOR OTHER SOURCES.
11

"DRIVE NOT READY"
"TEST e"
PRELIMINARY NOTES:
1. TEST A AND B MUST BE COMPLETED SUCCESSFULLY
BEFORE STARTING TEST C.
ACTIVATE AP-
PROPRIATE DS
LINE
CHECK FOR A
3.69JLs TIMING
CLOCK SIGNAL AT TEST
#1
INTERFACE
J29 & 10
CHECK FOR TIM-
ING CLOCK AT
CONTROLLER IN-
TERFACE
CHECK CABLE J9
PIN 16 AT CON- TEST #3
TROL PCB
CHECK J9 16 AT
STEPPER PCB FOR TEST #4
TIMING CLOCK
VERIFY J4 TIMING
CLOCK AT THE
FOLLOWING CHIP TEST #5
LOCATIONS AT
STEPPER PCB
REPLACE CON-
TROL BD
REPLACE J9
CABLE
REPLACE
STEPPER
PCB
TEST C CONTINUED NEXT PAGE
12
TEST #2
VERIFY CON-
TROLLER OPERA-
TION.
STEPPER PCB IC'S
PIN LOCATIONS
2E-1
1E-1
3D-9
1A:13
5A-1
1C-9
1B-1
2B-1
1A-1
REPLACE J2
CABLE
20 PIN CONNEC-
TOR
NOTE; CABLE J9
WILL BE
OMITTED WHEN THE STEPPER
LSI CHIP IS INSTALLED IN LOCATION #3C
OF CONTROL PCB.