Shugart SA850 User manual

SA850/851 ~
Bi-CompliantTM g
Double Sided ~D
Diskette Storage Drive @
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~®Shugart
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TABLE OF CONTENTS
.1.0 Theory of Operations . . . . . .. . ........ .
1.1 General Operations.
1.1.1 Head Positioning
1.1.2 Diskette Drive Spindle
....... .
1.1.3 Read/Write Heads
............. .
1.2 Recording
Format. . . ..... .
1.2.1 Bit Cell
.......... . ............ .
1.2.2 Byte
............. .
1.2.3 Recording Format (Double Density) .
1.2.3.1 Rules of Encoding .
1.2.4 Tracks. . . .
..... .
1.2.5 Track Format
............. .
1.2.5.1 Sector Recording Format
1.2.5.2 Soft Sector Recording Format.
1.2.6 Typical Track Index Format
1.2.6.2. . . . . . . . .
..... .
1.3.0 Track Accessing
........ .
1.3.1
................ .
1.3.2 . . . . . . . . . . .
...... .
1.3.2.1. .
............... .
1.3.3 Actuator Control Logic (Figure 21) . . .
........ .
1.3.3.1 Power
On Reset. . ....................... .
1.3.3.2 Forward Seek
.................... . ..... .
1.3.3.3 Reverse Seek
......... . ............... .
1.3.4 Track Zero Indicator. .......... . ............................ .
1.4.0 Read/Write Operations
.......... , ............ . ......... .
1.4.1 . . . . . . . . . . . .. ............... . .......................... .
1.4.2 . . . . . . . . . . . . . .
.. . .................. .
1.4.3 . . . . . . . . . . . ................... .
1
1
1
1
2
3
3
3
4
5
6
6
.......... 6
6
6
. 12
. ........ 13
13
. ........ 13
13
13
. ..... 13
. . 13
14
. ...... 14
.. ........ 17
· .. 17
17
17
1.4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..... 17
1.4.5 . . . . . . . . . . . . . . . . . .
..................................... 17
1.5.0 Read/Write Head . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.1 .. ....................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 19
1.5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ......... 19
1.5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.......... 19
1.5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
........ 19
1.6.0 Write Current Operation (Figure 32) .............................. . · .. 20
1.6.1 .................. .
1.6.2 . .
............. .
1.6.3
....... .
1.6.4
........... .
1.7.0 Read Circuit Operation (Figure 33)
..
1.7.1 ................. .
1.7.2
............. , ............. .
1.7.3
.......... .
1.8.0
Interface. . .......... .
1.8.1
J1/P1 Connector. . ...... .
1.8.2
AC Power . . . . . . ...... .
1.8.3
DC Power. . ...... .
1.8.4 Output Lines
...
. ......... 20
. ....... 20
. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
.20
. ... 21
. ... 21
. . 21
. .... 21
.22
.22
22
· .. 22
22

2.0 Maintenance Section ............................................................... 25
2.1.0 Maintenance Features .......................................................... 25
2.1.1 Alignment Diskette ............................................................. 25
2.1.2 SA809 Exerciser
........................................... ' .................... 25
2.1.3 Special Tools
................................................................. 25
2.2.0 Diagnostic Techniques .......................................... '.' .............. 25
2.2.1 Introduction .......................................... '.' ...................... 25
2.2.2
"Solt Error" Detection and Correction .............................................. 26
2.2.3 Write Error
................................................................... 26
2.2.4 Read Error
................................................................... 26
2.2.5 Seek Error
.................................................................... 26
2.2.6 Test Points SA850/851
.......................................................... 27
2.2.7 Connectors ................................................................... 27
2.2.7.1 ......... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 27
2.2.7.2. . . . . . . . . . . . . . . . . .
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 28
2.2.7.3 J3/P3
...................................................................... 28
2.2.7.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 29
2.2.7.5 J5/P5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 29
2
.. 2.7.6 J6/P6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
2
.. 3.0 Preventative Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
2
.. 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
2
.. 3.2 Preventive Maintenance Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
2
.. 3.3 Cleanliness .... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30
2 .. 3.4 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30
2 .. 4.0 Removals, Adjustments ........................................ ; ................ 30
2..4.1 Motor Drive ................................................................... 30
2..4.1.1 Drive Motor Assembly: Removal and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30
2..4.1.2 Motor Drive Pulley ............................................................ 30
2..4.2 Head Cover Shield Removal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30
2.4.3 Cartridge Guide Access ......................................................... 31
2.4.4 Sectorllndex LED Assembly: Removal and Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31
2.4.5 Write Protect Detector .......................................................... 31
2.4.5.1 Write Protect Detector: Removal and Installation .................................... 31
2.4.5.2 Write Protect DetectorAdjustment ............................................... 31
2.4.6 Head Load Mechanism Assembly .. '.' ............................................. 32
2.4.6.1 Head Load Mechanism: Removal and Installation ................................... 32
2.4.6.2 Head Load Mechanism Adjustment .............................................. 32
2.4.7 Index/Sector Photo Transistor Assembly ............................................ 34
2.4.7.1 Index/Sector Photo Transistor Assembly: Removal and Installation ...................... 34
2.4.7.2 Index/Sector Adjustment .. ' ..................................................... 34
2.4.8 Spindle Assembly .............................................................. 34
2.4.8.1 Clamp Hub Removal .......................................................... 35
2.4.9 Cartridge Guide ............................................................... 35
2.4.9.'1 Cartridge Guide Removal ...................................................... 35
2.4.9.2 Cartridge Guide Adjustment . . . . . . . . . . . . . . . .............................. 35
2.4.10 Head Amplitude Check ......................................................... 36
2.4.10.1 Head Actuator Assembly: Removal and Installation ................................. 36
'2.4.10.2 Head Penetration Adjustment ....... , .......... , ......... , .......... , . , . . 37
2.4.10.3 Head Radial Alignment ........ , , ........... , ....... , ......... , , . . . . . . . . . 43
2.4.10.4 Read/Write Heads Azimuth Check .............. , .......... , .......... ".. 43
2.4.11 Door Lock Solenoid and
In Use LED Assembly Removal .......... , .. , ........ , ........ 44
2.4.12 Track 00 Detector: Removal and Installation .......... , .............. , . . . . .. 46
2.4.12.1 Track 00/76 Stop Adjustment .......... , ........... , ... , ................... , ... 46
2.4.12.2 Track 00 Detector Assembly Adjustment . , .. , .................................... 46
2.4.13 Door Lock Solenoid and
In Use LED Assembly Removal. . . ........... , ........... 46
II

Figure
LIST OF ILLUSTRATIONS
1. SA850/851 Functional Diagram ....... .
2. Bi-Compliant Read/Write Head ........... .
3. Data Pattern .... . ................... .
4. Bit Cell. . . . . . . . . . . .......... .
5. Byte... . . . . . . . .. . ...................... .
6. Data Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..... .
7.
8.
9.
FM, MFM and M2FM Encoding ....... .
SA801
Sector Recording Format ..
Track Format ....................... .
MFM Track Format Comparison ...... .
Index Address Mark FM ....................... .
10 Address Mark FM . . . . . . ......... .
Data Address Mark FM . . . . . . ............ .
Deleted
Data Address Mark FM .
MFM Index Address Mark ..................... .
MFM 10 Address Mark ........................ .
MFM Data Address Mark. . . . . . . . . . .................. .
MFM Deleted Data Address Mark. . . ...... .
MFM Index Pre Address Mark ............... .
MFM Pre ID/Data Address Mark . . . . . . . .. . ........ .
Activator Control Logic ......... .
Count 0 . . . . . . . . . . . ................... .
Count 1 ................ .
Count 2 . . . . . . . . . . . .. . ...... .
Count 3 ...... .
Byte .................................. .
Basic R/W Head
Recorded Bit
...... .
Reading a
Bit. . . . ........................ .
1F and 2F Recording Flux and Pulse Relationship
Read/Write
Heads. . . . . . . . . . ...... .
Write Circuit Functional Diagram ........ .
Read
Circuit Functional Diagram
Data Separation Timing Diagram ...... .
Interface Connections.
Interface Signal Driver/Receiver.
Head Load Mechanism Adjustment .......... .
Head Load Timing .
Head Penetration Tools
......... .
Dial Indicator . . . . .................. .
Penetration Plate Installation
Dial
Indicator Installation ...... .
Installation Check .......... .
2
2
3
.. .. 3
4
4
5
6
7
8
8
9
9
9
· .. 10
·
....... 10
·
.. 10
· . 11
.. ..... 11
. ....... 11
· .. 15
· .. 16
.
............. 16
. . . . . . . .
.. 16
· . 16
. ............... 17
. ...... 18
.
.......... 18
· . 18
· . 19
· ....... 19
. .... 20
·
.. 21
. ... 22
· .23
· .. 24
· ....... 33
.33
· ....... 37
· .38
. ......... 39
· . 40
. ... 41
· ....... 41
. ............. 42
10.
11 .
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
2·3.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
Correct Penetration.
Penetration Adjustment.
Head Radial Alignment
Motor Plate . . . . . . . . . . . . . 44
. . . . . . . . . . . . . . 44
III

48. Azimuth Burst Patterns ....................................................... 45
FlowCharts ........................ . ......................................... 47
logic Diagrams : .................... " ..... " ..................................... 53
Physical Locations ........... : . . . . . .. . ........................ ' ................. 57
49.
(1 of 2) .................................................................... 61
49. (2 of 2) ........... " .............. " .......................................... 62
Illustrated Parts Catalog ........... " ... " .......................................... 63
50.. " .......................... " ... " .......................................... 64
51 ...................... " .......... "" .............................. " " ......... 67
Schematic Diagrams
................. " .......................................... 68
IV

1.0 THEORY OF OPERATIONS
1.1 GENERAL OPERATIONS
The SA850/851 Diskette Drive consists of read/write and control electronics, drive mechanism, read/write
heads, track positioning mechanism, and removable Diskette. These components perform the following
functions:
• Interpret and generate control signals.
• Move read/write heads to the desired track.
• Read and write data.
The relationship and interface signals for the internal functions of the SA850/851 are shown
in Figure 1.
The Head Positioning Actuator positions the read/write heads to the desired track on the Diskette. The Head
Load Actuator loads the read/write heads against the Diskette and data may then be recorded or read from
the Diskette.
The electronics are packaged
on the PCB. The PCB contains:
1. Index Detector Circuits (Sector/lndex for SA851).
2. Head Position Actuator Driver
3. Head Load Solenoid Driver
4. Read/Write Amplifier and Transition Detector.
5. Data/Clock Separation Circuits (SA851).
6. Write Protect
7. Drive Ready Detector Circuit.
8. Drive Select Circuits.
9. Side Select Circuit.
10. In Use and Door Lock Circuits
11. Write Current Switching/Read Compensation
1.1.1 HEAD POSITIONING
The read/write heads are accurately positioned by a Fasflex™ metal band/stepping motor actuator system.
A precision stepping motor
is used to precisely position the head/carriage assembly through the use of a uni-
que metal band/capstan concept. Each 3.60 rotation of the stepping motor moves the read/write head one
track in discrete increments.
1.1.2 DISKETTE DRIVE SPINDLE
The Diskette drive motor rotates the spindle at 360 rpm through a belt-drive system. 50 or 60 Hz power is ac-
commodated by changing the drive pulley and belt. A registration hub, centered
on the face of the spindle,
pOSitions the Diskette. A clamp that moves in conjunction with the latch handles fixes the Diskette to the
registration hub.

1.1 .. 3 READ/WRITE HEADS
READ
LOGIC
WRITE
LOGIC
SIDE
READ DATA
SEP DATA (FMI
SEP CLOCK (FMI
WRITE CURRENT
WRITE DATA
WRITE GATE
WRITE PROTECT
SELECT POWER ON RESET
INDEX DETECTOR
INDEX LED
STEPPER ... A
STEPPER -A
,·B
STEPPER -8
CONTROL
LOGIC
t
FIGURE 1. SA850/851 FUNCTIONAL DIAGRAM
SIDE SELECT
IN USE LED
HEAD LOAD (OPTIONAL!
STEP
DIRECTION/SIDE SELECT (OPTIONAL!
DRIVE SELECT
TRACK 00
INDEX
READY
SECTOR (851)
ALTERNATE I/O (3 LINES)
TWO SIDED
(OPTIONAl)
DISK CHANGE
The proprietary heads are a single element ceramic read/write head with straddle erase elements to provide
erased areas between data tracks. Thus normal interchange tolerances between media and drives will not
degrade the signal to noise ratio and insures diskette interchangeability.
The read/write heads are mounted on a carriage which is pOSitioned by the Fasflex™ actuator. The head
carriage assembly utilizes a combination flexured/rigid head mounting system. This allows the flexured head
to load the media against its rigidly mounted counterpart (see Figure
2).
The diskette is held in a plane perpendicular to the read/write head by a platen located on the base casting.
This precise registration assures
perfect compliance with the read/write heads. The read/write heads are in
direct contact with the diskette. The head surface has been deSigned to obtain maximum signal trans·fer to
and from the magnetic surface of the diskette.
FIGURE 2. BI-COMPLIANT READ/WRITE HEAD
2

1.2 RECORDING FORMAT
The format of the data recorded on the Diskette is totally a function of the host system. Data is recorded on
the diskette using frequency modulation as the recording mode, i.e., each data bit recorded on the diskette
has an associated
clock bit recorded with it, this is referred to as FM encoding. Data written on and read
back from the diskettes takes the form as shown
in Figure 3. The binary data pattern shown represents a
101.
1.2.1 BIT CELL
As shown in Figure 4, the clock bits and data bits (if present) are interleaved. By definition, a Bit Cell is the
period between the leading edge
of one clock bit and the leading edge of the next clock bit.
1.2.2 BYTE
CLOCK BITS
~BIT CELL----1
FIGURE 3. DATA PATIERN
~ ... B_IT_S __ .... ~
i
DATA BITS
FIGURE 4. BIT CELL
A Byte, when referring to serial data (being written onto or read from the disk drive), is defined as eight
(8)
consecutive bit cells. The most Significant bit cell is defined as bit celiO and the least significant bit cell is
defined as bit cell
7. When reference is made to a specific data bit (i.e., data bit 3), it is with repsect to the
corresponding bit cell (bit cell
3).
During a write operation, bit celiO of each byte is transferred to the disk drive first with bit cell 7 being
transferred last. Correspondingly, the most significant byte
of. data is transferred to the disk first and the
least significant byte is transferred last.
When data is being read back from the drive, bit celiO of each byte will be transferred first with bit cell 7 last.
As with reading, the most significant byte will be transferred last from the drive to the user.
Figure 4 illustrates the relationship of the bits within a byte and Figure 6 illustrates the relationship of the
bytes for read and
write data.
3

C C o
BITCELL 0
USB
-----------------------B~-----------------------
BINARY REPRESENTATION OF:
DATA BITS
CLOCK BITS
HEXADECIMAL
REPRESENTATION
OF
DATA BITS
CLOCK BITS
t
BIT CELL 0 OF BYTE 0 IS
FIIRST DATA TO BE SENT
TO THE DRIVE WHEN
WIfIITING AND FROM THE
Df~IVE WHEN READING
o o
FIGURE 5. BYTE
FIGURE 6. DATA BYTES
1.2.3 RECORDING FORMAT (DOUBLE DENSITy)
.0
CDC
t
BIT CELL 7 OF BYTE 17 IS
LAST DATA TO
BE SEIH TO
THE DRIVE WHEN WAITING
AND FROM THE DRIVIE
WHEN READING
Double capacity can be obtained by use of MFM (modified frequency modulation) and M2FM (modified,
modified frequency modulation) rather than
FM (frequency modulation) which is the standard method of en-
coding data on the diskette.
The differences between FM, MFM and M2FM encoding are shown in Figure 7. Note that MFM and M2FM
result in a 1 to 1 relationship between the "flux changes per inch" and the bits per inch recorded Oln the
diskette. This also results
in a doubling of the data transfer rate, from 250 to 500 KBS, when compared to
FM ..
Data error rate performance equal to standard capacity diskettes using FM encoding can be achieved by us-
ing:
• The SA850/851 diskette drive with its proprietary ceramic/ferrite read/write head.
• Phase locked loop (VFO) data separator
• Write precompensation.
Provision
of the phase locked loop data separator and write precompensation circuitry is the responslibility
of the user of the SA850/851 diskette drive.
Shugart Associates will provide design information, as required, to SA850/851 users who desire to incor-
porate double capacity diskette drives in their products.
The bit cell for MFM and M2FM encoded data is one half the duration of the bit cell for FM encoded data.
Also, unlike FM, and MFM and M2FM bit cell does not always contain a clock bit at its leading edge. This lack
of clock bit makes data separation more complex Also, the window size is half the FM window size, which
results in less tolerance to bit shift. The only reliable method to separate MFM and M2FM encoded data is
through use of a phase locked loop (VFO) type
of data separator. The VFO, once synchronized, tracks the
data and generates clock and data windows, improving the bit shift tolerance over the conventional
"hard"
data separators commonly used in FM recording, which use windows of fixed timing.
4

1.2.3.1 RULES OF ENCODING
FM Encoding:
• Write data bits at the center of the bit cell.
• Write clock bits at the leading edge of the bit cell.
MFM Encoding:
• Write data bits at the center of the bit cell.
• Write clock bits at the leading edge of the bit cell if:
1) There is no data bit written in the previous bit cell, and
2) There will be no data bit written in the present bit cell.
M2FM Encoding:
• Write data bits at the center of the bit cell.
• Write clock bits at the leading edge of the bit cell
if:
1) There is no data bit or clock bit written in the previous bit cell, and
2) There will be not data bit written in the present bit cell.
NOTE: In M2FM/MFM, the write oscillator frequency is doubled, while maintaining the same flux changes per
inch
as FM. Thus, the bit cell in M2FM/MFM is V2 that in FM. Data transfer rate is also doubled, since a
1 to 1 relationship exists between flux changes per inch and bits per inch
(2 to 1 in FM).
BIT I
CELLS~ ______ ~ ____ ~ ______ ~ __ O __ ~~ ____ ~ __ O ____ ~ __ O __ ~ ___ O __ -L ____ ~
FM
I
1
121
1
I
ID D D
11
D
~~LLS ____ 1 .... 1_1 .... 1_1 ......... 1 _0 .L..I _1 .... 1_° ..... 1_° .......... 1 _0 .... 1---,
D D D D
MFM
D D D D D
~I 4/31 ~
11 H 4/51
,
,
,
,
,
, ,
~
, ,
~
FIGURE 7. FM. MFM AND M2FM ENCODING
5
,
,
,
,
,
,
,
,
,
~
, , ,
,
~
,

1.2.4 TRACKS
The! SA850/851 drive is capable of recording up to 154 tracks of data. The tracks are numbered 0-76 for each
side. Each track
is made available to the read/write heads by accessing the head with a stepper motor and
carriage assembly and selecting the desired side of the diskette. Track accessing will be covered
in Section
3.
Basic Track Characteristics:
No. Data bits/track Single Density
No. Data bits/track Double Density
Index Pulse Width
Index/Sector Pulse Width
(SA851 only)
1.2.5 TRACK FORMAT
41,300 bits
82,600 bits
1.8 ±
.6 ms
.4 ± .2 ms
Tracks may
be formatted in numerous ways and is dependent on the using system. The SA850/851 use index
and sector recording formats respectively.
1.2.5.1 SECTOR RECORDING FORMAT
In this Format, the using system may record up to 32 sectors (records) per track. Each track is started by a
physical index pulse and each sector is started by a physical sector pulse. This type of recording is called
hard sectoring. Figure 8 shows a typical Sector Recording Format for 1 of 32 sectors.
'---- ____ -----I
ri
IS
DATA I CLOCK
SYN-
72 BITS-+---~
MIN
40 BITS MAX
DATA IDENTIFIER- ~
WRITE
TURN ON
112 BITS 72 BITS
MAX ~""'---1040 BITS MAX -..MIN
~--------5.2 ± .30MS--------- ... -1
FIGURE 8. SA801 SECTOR RECORDING FORMAT
1.2.5.2 SOFT SECTOR RECORDING FORMAT
In this Format, the using system may record one long record or several smaller records. Each track is
started
by a physical index pulse and then each record is preceded by a unique recorded identifier. This type
of recording
is called soft sectoring.
1.2.6 TYPICAL TRACK INDEX FORMAT
Figure 9 shows a track Format, which is IBM compatible, using index Recording Format with soft sectoring.
6

-.....I
-.J. 11.....- __
PrlYSICAL INDEX INDEX ADDRESS MARK
,
DATA
GAP4
PRE PRE
FIELD
PRE
INDEX
10
26
INDEX
C2 A1
MFM MFM
10
TRACK -
ADDRESS
SIDE
SECTOR
SECTOR
CRC
MARK -
ADDRESS
NUMBER NUMBER
LENGTH
1
I
[ HEX 00 FOR SIDE 0
HEX 01 FOR SIDE 1
HEX 00 FOR 126 BYTE SECTORS
_ H~X 01 ~OR 256 BYTE SECTORS
I I A1 I
FM
MFM
11
22
6
12 o
3
10
FIELD
1
X
CRC
2
BYTES
BYTES
J
GAP
2
)
'-
;
j
GAP
10
3
'-
FIELD
2
~
DATA
ADDRESS
MARK
FM
MFM
FIGURE 9. TRACK FORMAT
DATA
GAP
+ DATA
FIELD
<II FIELD
GAP
2 2
26
4
USER DATA
CRC CRC
1 2
1 I "I 1 A1 I
26
53 6
12
o
3
BYTES
BYTES
Note byte count is tor 26 records
Gap 3 change byte count with
record length.

r-I INDEX
_J IL--=~~ __________________________ __
.-------------------------------
MFM1M16BYTES----------------------------------~
I INDEX IPRE I I. I
G4A SYNC I.AM AM Gl
------. REPEAT FOR EACH RECORD _I
~~NC I :~ I AM liD I CAC I G2 I ~~ I ::~AAM I AM I DATA I CRC I ~i=~·1 G3 G4B
4E
00
m
FC 4E
00 m FE @] ffi 4E 00 0 ~ 40 0 4E 4E 4E DATA
80
12 3 1
80
12
3 1
80
12 3 1
50
50
50
12
12
12
2
2
2
4 2
22
4 2 22
4 2 22
-----------------------~
UPDATE WRITE
III 3 bvtes C2 with unique clock patt~n 14
m 3 bytes Al with unique clock patt~n OA
[!) Track 11OO'Iber.. head fItIIOOer. sectOf. record length
~ Generated by CRC ..-alor which should be equiQllent 10 celTT VHl
(!] 1 byte 01 FB or Fa
12
12
12
3
3
3
1024
512
256
2
2
2
115 654 BYTES18 REC.
B3 400 BYTES/IS REC.
53 598 BYTESI26 REC.
L_
FIGURE 10. MFM TRACK FORMAT COMPARISON
C o C o o C o o C o C C
BIT CEll 1 BIT CEll 2 BIT CEll 3 BIT CEll 4 BIT CEll 5 BIT CEll 6
.... I----------INDEX ADDRESS MARK BYTE-----------t~
BINARY
REPRESENTATION OF:
DATA BITS
CLOCK BITS 1
o
o o
FIGURE 11. INDEX ADDRESS MARK FM
8
HEXADECIMAL
REPRESENTATiON OF:
o DATA BITS
FC
CLOCK BITS
07

C C o C o o o o c o c o c C c
BIT CELL 7 BIT CELL 0 BIT CELL 1
BITCEll]
BIT CELL J
BITCELLO
~------------------------IOADORESSMARKBYTE ------------------------~
BINARY
REPRESENTATION OF:
DATA BITS
CLOCK BITS
C c o c o
o o o
FIGURE 12. ID ADDRESS MARK FM.
o o o c
o
C o C
HEXADECIMAL
REPRESENTATION OF:
DATA BITS
FE
CLOCK BITS
C7
o C c
81T CELL' 81T CELL e
'" CHl , ~ :" CEll; :,TCEl"
81T CELL 5
~-----------------------DATAADDRESSMARKBYTE------------------------~
BINARY
REPRESENTATION OF:
DATA BITS
CLOCK BITS
C C o C o
o
o o o
FIGURE 13. DATA ADDRESS MARK FM
o o o c C c
HEXADECIMAL
REPRESENTATION OF:
DATA BITS
FB
CLOCK BITS
C7
C c
~---------------------DELETEDDATAADDRESSMARKBYTE------------------~~
BINARY
REPRESENTATION OF:
DATA BITS
CLOCK BITS
o o o
o o o
FIGURE 14. DELETED DATA ADDRESS MARK FM
9
HEXADECIMAL
REPRESENTATION OF:
DATA BITS
Fa
CLOCK BITS
C7

D D
BINARY
REPRESENTATION OF:
DATA BITS
CLOCK BITS
D D D
BIT ~ELL I BIT ~ELL I BIT ~ELL I
INDEX ADDRESS MARK
o o o
D D C
5 ,6 7
BIT CELL I BIT CELL I BIT eEL:1
HEXADECIMAL
REPRESENTATION OF:
o FC
01
FIGURE 15. MFM INDEX ADDRESS MARK
D D D D D D D
BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL
, ....... ___ ----------- MFM ID ADDRESS MAR K --------------il~
BINARY
REPRESENTATION OF:
D
DATA BITS
CLOCK BITS
D
~IT ~ELL I BIT ~ELL I
BINARY
REPRESENTATION OF:
DATA BITS
CLOCK BITS
o o o o o o o
FIGURE 16. MFM ID ADDRESS MARK
D D D
HEXADECIMAL
REPRESENTATION OF:
o
o
FE
00
D D
BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL
o o
DATA ADDRESS MARK -------------I~
o o o o
o o
HEXIDECIMAL
REPRESENTATION OF:
FB
o
00
FIGURE 17. MFM DATA ADDRESS MARK
10

C D
BINARY
REPRESENTATION OF:
DATA BITS
CLOCK BITS
D
o
D D
DELETED DATA ADDRESS MARK
o o o o o
o o
D C
HEXIDECIMAL
REPRESENTATION OF:
o
Fa
03
FIGURE 18. MFM DELETED DATA ADDRESS MARK
D D C C D
BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL
104------------ PRE INDEX ADDRESS MARK -------------:l~
BINARY
REPRESENTATION OF:
DATA BITS
CLOCK BITS o o o
o o o
o o o
HEXI DECIMAL
REPRESENTATION OF:
o
o
C2
14
FIGURE 19. MFM INDEX PRE ADDRESS MARK
D D C C D
JI~~n~~n~ __ ~n~_nL
BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT ~ELL I BIT <;;ELL I BIT ~ELL
~-------------PREADDRESSMARK
BINARY
REPRESENTATION OF:
DATA BITS
CLOCK BITS o o
o o o o o o
o o
HEXIDECIMAL
REPRESENTATION OF:
A1
o
OA
FIGURE 20. MFM PRE ID/DATA ADDRESS MARK
l'

1.2.6.1 Index is the physical detector indicating one revolution of the media and is used to initiate format
operations, generate the Ready signal in the storage device, insure one complete revolution
of the media
has been searched. and for a deselect storage device signal after a certajn number of revolutions.
Gap
1-
G4A is from the physical index address mark sync and allows for physical index variation,
speed variation and interchange between Storage Devices.
Sync is a fixed number of bytes for Separator synchronization prior to the address mark. It
includes a minimum of two bytes plus worst case Separator sync up requirements.
Index Pre Address Mark (MFM) . Three bytes of C2 with unique clock bits not written per
the encode rules. Refer to Figure 19.
Index Address Mark (FM) . is a unique byte to identify the index field and is not written per
the encode rules. Refer to Figure 11.
Index Address Mark (MFM) . is one byte of FC and it is written per the encode rules.
Refer to Figure 15.
G1 is from index address mark to 10 field address mark sync.
ID Field -Sync is a fixed number of bytes for Separator synchronization prior to AM. Includes a
minimum
of two bytes plus worst case Separator sync up requirements.
Gap
2-
10 Pre Address Mark (MFM) . Three bytes of A1 with unique clock bits not written per the
encode rules. Refer to Figure 19.
10 Address Mark (FM) . is a unique byte to identify the 10 field and not written per the en-
code rules. Refer to Figure 12.
10 Address Mark (MFM) . is OnE! byte of FE and it is written per the encode rules. Refer to
Figure 16.
10 . is a four byte address containing track number, hearj number, record number, and
record length.
CRe . is two bytes for cyclic redundancy check.
Gap from 10CRC to data AM sync and allows for speed variation, oscillator variation and
erase core clearance of 10CRC bytes prior to write gate turn on for an update write.
Data
F'ield -Sync is a fixed number of bytes for Separator synchronization prior to the AM. Includes a
minimum of
two bytes plus worst case separator sync up requirements.
Pre Data Address Mark
(MFM) . Three bytes of A1 with unique clock bits not written per
the encode rules. Refer to Figure 20.
Data Address Mark (FM) . is a unique byte to identify the Data Field and it is not written
per the encode rules. Refer to Figure 13.
Data Address Mark
(MFM) . is one byte of FB or F8 and it is written per the encode rules.
Refer to Figure 18.
Data· is the area for user data.
CRe . is two bytes for cyclic redundancy check.
WG
OFF (Write Gate Off) . is one byte to allow for the Write Gate turn off after an update
write.
12

Gap 3-
Gap 4-
Gap from WG OFF to next ID AM sync and allows for the erase core to clear the Data
Field CRC bytes, speed and write oscillator variation, read preamplifier recovery time and
system turn around time to read the following
10 Field.
G4B is the last gap prior to physical index and allows for speed and write oscillator varia-
tion during a format write and physical index variation.
1.3.0 TRACK ACCESSING
• Carriage Actuator Motor
• Actuator Control Logic
• Reverse Seek
• Forward Seek
• Track 00 Flag
1.3.1 Seeking the read/write heads from one track to another is accomplished by selecting the desired
direction utilizing the Direction Select interface line, loading the read/write heads, and then pulsing the Step
line. Multiple track accessing is accomplished by repeated pulsing of the Step line until the desired track has
been reached. Each pulse
on the Step line will cause the read/write heads to move one track either in or out
depending
on the Direction Select line.
1.3.2 The Carriage Actuator Motor used on the SA850/851 is a four phase, 3.6 degree, permanent
magnet stepper motor.
1.3.2.1 There are four stator poles with four teeth per pole extending axially the length of the rotor. The
rotor contains
25 teeth per half, spaced 14.4 degrees apart, with each being displaced one tooth pitch
relative to each other. The rotor is permanently magnetized with one gear (half) being the north pole and the
other the south pole. The four winding per phase are those which when energized will magnetize the poles
causing the rotor to move
1;4 of a gear tooth pitch or 1 step.
1.3.3 ACTUATOR CONTROL LOGIC (FIGURE 21)
1.3.3.1 POWER ON RESET
The Step Counter (FF A and FF 8) is a modified Gray Code counter that counts 0, 1, 3 and 2. At power on, the
Step Counter
is reset causing the not outputs to be active. When the door is closed and the heads loaded the
not outputs actuate the 1 and 4 drivers. With these drivers active the position zero windings are excited
causing the rotor to align
as shown in Figure 22. (Note, depending on the previous state of the stator win-
dings, the heads may move up to two tracks).
1.3.3.2 FORWARD SEEK
• Seek forward five tracks.
• Assuming:
Present position of the read/write heads to be track 00.
Direct Select at a minus level (from the host system).
Write Gate inactive.
Five Step pulses to
be received (from the host system).
Step Counter reset (drivers 1 and 4 active).
13

Minus Direction Select is inverted and becomes +Direction Select. Since the Step Counter is reset (low), a
higtl is at one input of ExClusive
OR A and a low at Exclusive OR B. +Direction Select is high and inverts
both signals present at ExclusiveOR's A and
B, causing the input to FFB to be high.
When the first Step pulse is sent to the control logic, it
is anded with -Read Gate and then clocks FF A off and
FF Bon. this enables drivers 1 and 3 causing the Actuator Motor to move 3.60 in a clockwise direction, which
in turn moves the carriage assembly one track towards the center of the diskette. Figure 21 (Track 01 ,Count
1 ).
With FF A off and FF B on, a low is presented to Exclusive OR A A and B allowing +Direction Select to pass
to both
FFS. Upon receipt of the next Step pulse both FFS are clocked on, enabling drivers 2 and 3. Figure 22
(Tra.ck 02, Count 3).
With both FFS on, a low is at Exclusive OR A and a high at Exclusive OR Bwhich presents + Direction Select
to FF A. The next Step pulse clocks FF A on and FF B off enabling drivers 2 and 4. Figure 25 (Track 03, Count
2).
This process is continued until the host system stops sending step pulses at Track 05. At that time FF A is off
and
FF B on enabling drivers 1 and 3. Figure 23 (Count 1).
1.3.3.3 REVERSE SEEK
• Seek in a reverse direction five tracks.
• Assuming:
Present position of the read/write heads to be track 05. Direction Select at a positive level (from
the host system).
Write Gate inactive.
Five step pulses to be received.
FF A is off and FF B is on, drivers 1 and 3 active.
Plus Direction Select is inverted and becomes -Direction Select. With FF A off and FF B on lows, are
presented to Exclusive
ORs A and B. With the first step pulse the FFS are clocked off enabling the 1 and 4
driv.ers causing the actuator motor to move 3.6 degrees in a counter-clockwise direction, moving the car-
riage one track towards the outside of the diskette. Figure
22 (Track 04, Count 0).
Witt) both FFS off a high is presented to Exclusive OR A and a low to Exclusive OR B. the next Step pulse
clocks
FF A on and FF B off enabling drivers 2 and 4. Figure 25 (Track 03, Count 2).
This process continues until the fifth Step pulse. With lows at the Exclusive ORs, and FF's are clocked off
enabling drivers 1 and 4. Figure 21 (Track 00, Count 0).
1.3.4 TRACK ZERO INDICATOR
Track 00 Pin 42 is provided to the host system to indicate the read/write heads are at track zero. The Track
Zero Flag
on the carriage assembly is adjusted so that the flag covers the photo transistor at track one.
When
FF A and B are clocked off the actuator moves to track zero, the Q outputs and Drive Select Internal
are anded together and then ANDed with the Track Zero detect to send the Track Zero indication to the host
system. (Figure
21)
14

+ 5V
·DIRECTION
SELECT
·STEP
·READ
GATE'
TP27
PHASE A
PHASE B
TRACK
STEP COUNT
00
o
STEP
COUNTER
D 0
FFA
(5
FFB 0
(5
-POWER ON
RESET
-TRACK 00
01
02
3
03 04
2 0 05
+STEPPER ENABLE
06
3 07
2
08 09
o 10
11
3 2
FIGURE 21. ACTIVATOR CONTROL LOGIC
15
+ 24V
+ 24V