
5.2 Memory LCD-TFT Display
A 1.28-inch SHARP Memory LCD-TFT is available on the kit to enable interactive applications to be developed. The display has a high
resolution of 128 by 128 pixels, and consumes very little power. It is a reflective monochrome display, so each pixel can only be light or
dark, and no backlight is needed in normal daylight conditions. Data sent to the display is stored in the pixels on the glass, which means
no continous refreshing is required to maintain a static image.
The display interface consists of an SPI-compatible serial interface and some extra control signals. Pixels are not individually addressa-
ble, instead data is sent to the display one line (128 bits) at a time.
The Memory LCD-TFT display is shared with the kit Board Controller, allowing the Board Controller application to display useful infor-
mation when the user application is not using the display. The user application always controls ownership of the display with the
DISP_ENABLE signal:
• DISP_ENABLE = LOW: The Board Controller has control of the display
• DISP_ENABLE = HIGH: The user application (EFR32) has control of the display
Power to the display is sourced from the target application power domain when the EFR32 controls the display, and from the Board
Controller's power domain when the DISP_ENABLE line is low. Data is clocked in on DISP_SI when DISP_CS is high, and the clock is
sent on DISP_SCLK. The maximum supported clock speed is 1.1 MHz.
DISP_EXTCOMIN is the "COM Inversion" line. It must be pulsed periodically to prevent static build-up in the display itself. Please refer
to the display application information for details on driving the display:
http://www.sharpmemorylcd.com/1-28-inch-memory-lcd.html
0: Board Controller controls display
1: TARGET controls display
DISP_ENABLE
I2C_SCL
I2C_SDA
WAKE
EFM8SB1
DISP_EXTCOMIN
PB11 (US0_CLK#4)
PA0 (US0_TX#0)
EFR32BG1
PC6 (US0_CS#8)
Figure 5.2. 128x128 Pixel Memory LCD
On the BRD4101B Radio Board, both the DISP_ENABLE and the DISP_EXTCOMIN signals are driven by the I2C I/O expander device.
The DISP_ENABLE signal is set by writing to bit 0 (ENABLE) of the DISP_CTRL (0x00) register. The DISP_EXTCOMIN signal is set or
cleared by writing to bit 1 (EXTCOMIN) of the DISP_CTRL (0x00) register.
There is also an option to have the I/O expander device automatically handle the periodic toggeling of the DISP_EXTCOMIN signal. If
AUTO_EXTCOMIN (bit 2) in DISP_CTRL (0x00) is set, the DISP_EXTCOMIN signal will toggle at a fixed rate of 60 Hz (30 Hz clock
output).
Note: The display peripheral shares GPIO pins with the Serial Flash and the Virtual COM port peripherals, as well as the EXP header.
UG268: EFR32BG1 2.4 GHz 8 dBm WLCSP Wireless Starter Kit User's Guide
Peripherals
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