Silicon Laboratories Si3210 Guide

Rev. 0.61 8/09 Copyright © 2009 by Silicon Laboratories AN45
AN45
DESIGN GUIDE FOR THE Si3210/15/16 DC-DC CONVERTER
1. Introduction
The ProSLIC® from Silicon Laboratories integrates a
complete analog telephone interface into one
low-voltage CMOS device and offers extensive software
programmability to meet many global telephony
requirements and customer specifications. In addition to
performing all BORSCHT functions, the Si321x also
dynamically generates and controls its own battery
voltage, eliminating the need for external battery
supplies. Two different battery generation architectures
are supported: a BJT/inductor design offering a low-cost
battery supply solution, and a MOSFET/transformer
design offering increased power efficiency and a wider
range of input voltages. This application note gives
specific guidance in determining dc-dc converter power
requirements and selecting component values for each
of the dc-dc converter architectures.
1.1. Si321x DC-DC Converter Description
The dc-dc converter dynamically generates the large
negative voltages required to operate the linefeed
interface. The Si321x acts as the controller for a
buck-boost dc-dc converter that converts a positive dc
voltage into the desired negative battery voltage. In
addition to eliminating external power supplies, this
allows the Si321x to minimize power dissipation by
dynamically controlling the battery voltage to the
minimum required for any given mode of operation.
Figure 1. Linefeed Power Diagram
DC-DC
Converter VTR
VBAT
Input Output
Linefeed Circuitry
RING
TIP
Ringer RDC
Hook SW.
+
–
VDC
+
–
+
–
Twisted
Pair Line Telephone
RLINE
2
RLINE
2

AN45
2 Rev. 0.61
1.2. Power Output Requirement
Understanding the maximum power required by the
ProSLIC linefeed circuitry to operate a worst-case
specified load is the first step in determining the dc-dc
converter design solution. Figure 1 defines the linefeed
circuit and load circuit in basic blocks of circuitry.
Typically, the ringing state is the highest power
consumption state for the SLIC, but in special cases the
off-hook state can have the highest. Guidance in
calculating each of these states is offered in this
section.
The ringer impedance of one telephone is defined as an
8F cap in series with a 6930 resistor. This is
approximately the same impedance as 7000 at 20 Hz
and is defined as 1 REN (ringing equivalence number).
Since there can be N number of telephones connected
in parallel to the TIP and RING lines, the equivalent
impedance of the parallel ringers can be computed as
the following (NREN is limited to 1 to 5):
During ringing, the TIP-to-RING peak voltage, VTR_PK,
is the sum of the rms voltage drop across the ringer
circuit, VRINGrms, the line resistance, and the internal
source resistance of 160 .
Considering the resistance of 26 gauge telephone wire,
which is 0.45 per feet, this equation becomes the
following:
Equation 1
The required VBAT is equal to VTR_PK plus VCMR, which
is the voltage drop across the linefeed circuit. The
VCMR voltage is set by the indirect Register 40 and
recommended to be 1.5 V for most applications.
Equation 2
The worst-case peak current for NREN load is when the
load is connected with a short loop of negligible line
resistance.
This yields an average current equation:
Equation 3
The total output power required during ringing is equal
to the power consumed in the load plus the power
consumed in the sensing resistors and the external
transistors of the linefeed circuitry. This leakage current
has a magnitude of 2.5 mA.
Equation 4
1.2.1. In the Off-Hook State
In a few special cases, the power consumed during
off-hook is higher than the power consumed during
ringing. It is important to check for this and design the
power supply to handle the larger power requirement.
Most designers can skip this section unless their
designs support long line and/or the brief on-hook
voltage measurement (for caller ID 2 and 2.5) with
TRACK = 0 (bit 0 of the direct Register 66).
The output current equations in the off-hook active state
are as follows:
Equation 5
where ILIM is the current limit set by Register 71, and
IBJTBIAS is the bipolar biasing current set by the direct
Register 65.
There are two power equations for different track
settings. For TRACK = 1, VBAT is allowed to track the
line resistance to minimize power consumption.
RNREN
7000
NREN
------------------
=
VTR_PK
VRINGrms 2
7000 NREN
--------------------------------------- 7000
NREN
------------------RLINE Rs
++


=
VTR_PK
VRINGrms 2
7000 NREN
--------------------------------------- 7000
NREN
------------------2 Dist 0.045 160++


=
VBAT VTR_PK VCMR+=
IPK
VTR_PK
7000 NREN
----------------------------------------
=
IAVG IPK
2

---
2 NREN VTR_PK

7000
------------------------------------------------------
==
POUT VBAT IAVG 0.0025+=
IBAT ILIM IBJTBIAS
0.6 V 80 ILIM IBJTBIAS ++
5100
------------------------------------------------------------------------


++=

AN45
Rev. 0.61 3
The power equation for this mode is as follows:
Equation 6
where VCM is set by the direct Register 73, and VOV is
set by Register 66. RLOOPMAX is the maximum total loop
resistance (RLINE + Phone’s RDC + RS) where RS is the
internal series resistance.
For TRACK = 0, VBAT can ramp up quickly to support
the brief on-hook voltage measurement feature, the
power equation is as follows:
Equation 7
where VBATL is set by the direct Register 75.
If the off-hook power consumption is greater than the
power during ringing, the dc-dc converter should be
designed based on the off-hook current and off-hook
VBAT
. However, the requirement for the switching
components (Q7 and Q8 or M1) should still be based on
the VBAT value during ringing.
1.3. Power Input Requirement
The input power is equal to the output power plus the
wasted power during the power conversion process.
The efficiency of the Si321x dc-dc converter is mainly
dependent on the inductor loss (copper and magnetic
loss) and the switching loss. For worst-case estimation,
the efficiency is assumed to be 60% for the
BJT/inductor solution (the actual efficiency is between
63% and 73%) and 75% for the MOSFET/transformer
solution (the actual efficiency is between 75% and
83%.)
Solving for IIN:
Equation 8
The input voltage to the dc-dc converter could drop
quickly (depending on the source impedance) as the
input current rises. The VIN minimum is defined as the
input voltage level at the maximum input current defined
in Equation 8. It is important that the VIN minimum is
used as the VDC in the design calculation to prevent the
dc-dc converter from receding below the low-voltage
lock-out threshold, which could cause the dc-dc
converter to shut down prematurely.
POFFHOOK IBAT VCM VOV ILIM RLOOPMAX ++=
POFFHOOK IBAT VBATL =
POPIN Power EfficiencyIIN VIN Power Efficiency==
IIN
PO
VIN Power Efficiency
----------------------------------------------------------------
=

AN45
4 Rev. 0.61
1.4. Component Selection for BJT/Inductor
Solution
The typical circuit application for the BJT/inductor
version of the Si321x dc-dc converter is shown in
Figure 2. Components in this circuit are discussed, and
detailed descriptions for each functional block are
provided to guide the designer through the component
value selection process.
Figure 2. Typical Application Circuit
1.4.1. Power Inductor Design Equation
The L1 inductor is the main power component in the
Si321x dc-dc converter. Energy from the input is stored
into the L1 during Q7 switch transistor on-time and
released to the output during Q7 off-time. The amount
of this energy is directly proportional to the inductance
of the inductor and to the square of the maximum
current that flows through the inductor during on-time.
The inductor power equation is derived as the energy
over time:
where Fs is the switching frequency of the Q7 transistor.
This frequency represents the number of times that the
energy transfers from the input to the output via the
inductor per second.
The output power can be related to inductor power with
the efficiency factor, which is defined as the ratio of the
output power over the input power.
Equation 9
In the Discontinuous Switching mode, the current
flowing in the inductor always starts at 0 A at the
beginning of on-time of Q7, peaks at the end of the
on-time, and goes back to zero at the end of off-time.
During on-time, VDC is presented across the L1 inductor
and the current flow increases linearly (see Figure 3)
with respect to the on-time duration of Q7.
+VDC
VBAT
R21
RFILT
C9
CBAT
10

L1
LSW
R17
RSWE
C26
CFILT
2222
QBATD
Q8
Q7 QBATD
FZT953
C10
CFF
R20
RMONL
R19
RMONH
R16
RSW
R18
RVDC
C25
10

C14
0.1

DCMONH
DCMONL
DCFF
DCDRV D1
DSW
ES1D
Fuse
VCC
R28*
R29*
VBAT
Q9
2222
.1 mF
ELI
MAX
2

2
-------------------------
=
PIND
E
T
----LI
MAX
2

2T
-------------------------LI
MAX
2
Fs
2
--------------------------------------
== =
POUT EFF PIND EFF
LI
MAX
2
Fs
2
--------------------------------------


==

AN45
Rev. 0.61 5
The rate of the current increase depends on VDC and
the inductance of L1.
As the output demands more energy, the Si321x
lengthens Q7 on-time to increase the L1 inductor
current. This increase in the inductor current raises
storage energy in L1; Therefore, more energy is
available to the output when Q7 is off. The inductor
current reaches its peak IPK at tONMAX.
So, the maximum on-time is as follows:
The off-time equivalent circuit is shown in Figure 4. Q7
is off and the inductor current follows the diode, D1, to
the C9 output capacitor and the RLOAD.
Figure 3. L1 Current Flow during Q7 On-Time
Figure 4. L1 Current Flow during Q7 Off-Time
The voltage across the inductor during this time is equal
to VBAT less the D1 diode voltage drop or approximately
VBAT
. Since VBAT is greater than VDC, the rate of current
change is faster compared to the current slope during
on-time. The inductor current starts from IPK and
descends to 0 A at tOFFMAX.
So the maximum off-time is as follows:
Equation 10
The period of the switching frequency, Fs, is equal to
the reciprocal of the maximum on-time plus maximum
off-time:
it VDC
L
-----------t=
IPK
VDC
L
-----------tONMAX
=
tONMAX
IPK L
VDC
------------------
=
+
–
Q7 SW
VDC
i(t)
L1
IPK
tONMAX
Slope = di/dt = VDC/L
IPK
tOFFMAX
Slope = di/dt = VBAT/L
D1
C9
IL
L1
+
–
+
–
RLOAD
+
–
VBAT
IPK
tOFFMAX
-----------------------VBAT
L
--------------
=
tOFFMAX
IPK L
VBAT
------------------
=

AN45
6 Rev. 0.61
Substituting the above expression for the power
Equation 8:
Equation 11
And solving for IPK:
Equation 12
Solving for L from Equation 11, the required inductance
is expressed as:
Equation 13
The optimum switching frequency of the Si321x dc-dc
converter is between 64 kHz and 85 kHz. Faster
switching frequency is generally less efficient. This is a
common characteristic of the PNP switching element
and low-cost inductor magnetic material.
1.4.2. Power Inductor Selection
Once output power (POUT), VDC, and VBAT are clearly
defined, the inductor can be selected as follows:
1. Calculate IPK based on Equation 12 (assumed 60%
efficiency). This is the maximum current requirement
for the inductor.
2. Calculate the inductance, L, based on Equation 13
assuming worst case 60% efficiency. Since inductors
tend to have tolerances in the range of ±5% to
±30%, the minimum value of inductance must be
equal to the calculated value of the inductor. Vary Fs
from 64 kHz to 128 kHz to obtain the desired
inductance value.
3. Calculate the period, T, for Fs and the corresponding
value for direct Register 92 in hexadecimal.
Equation 14
4. Calculate the maximum off-time and the
corresponding value for direct Register 93 in
hexadecimal.
Equation 15
1.4.3. Selecting a DC-DC Converter Switching Tran-
sistor
The switching transistor (Q7) on the typical application
circuit is shown in Figure 2 on page 4. This transistor is
turned on by the base drive current through Q8 while
R16 provides the discharge current path for Q7’s
base-emitter capacitor during turn-off. The capacitor,
C10, provides additional charge pump boost current
from the DCFF pin of the Si321x to turn Q7 off faster.
C10 with a value of 22 nF is sufficient for most
applications. R16 plays an important role in turning off
the Q7 transistor, but R16 also robs the Q7 base drive
current during the on-time. With a value of 200 , R16
does an adequate job of turning Q7 off and only takes
3 mA from the base current during on-time.
Equation 16
Table 1 lists the requirements for the switching
transistor, Q7.
Another critical specification is the transistor gain at
ICMAX. The higher the transistor gain (hFE), the less
base current is required to keep it in saturation during
on-time and the more efficient the converter will be
since the base current is not delivered to the load.
Also, as more base current is required, it becomes more
difficult for the DCDRV and DCFF pins to switch the
transistor off quickly, which further decreases efficiency.
Practically, Q7 gain should be around 100 at peak
inductor current.
Fs 1
tONMAX tOFFMAX
+
--------------------------------------------------1
IPK LVDC IPK LV
BAT
+
----------------------------------------------------------------------------
==
POUT EFF PIND EFF
LI
PK
2Fs
2
----------------------------------


==
IPK
2POUT VBAT VDC +
EFF VBAT
VDC 
-------------------------------------------------------
=
L2POUT
EFF IPK 2Fs
-----------------------------------------
=
PWM Period Register 92 T
61 ns
---------------
=
Table 1. Switching Transistor Q7
VCEO > |VBAT| + VDC
VEBO > VCC
VCBO > |VBAT| + VCC + VDC
ICMAX > IPK (maximum Inductor current)
fT> 100 MHz
Direct Register 93 tOFFMAX
61 ns
-----------------------IPK LVBAT

61 ns
-----------------------------------------
==
R16 0.6
IR16
----------
=

AN45
Rev. 0.61 7
1.4.4. Si321x Bipolar Switch Driver
In Figure 2, the Q8 collector current provides the base
current drive that turns the switch transistor Q7 on. The
base current drive should be sufficient to keep Q7 in
saturation at IPK. The overdrive factor of 1.3 is sufficient.
Equation 17
The Si321x sets the DCDRV pin high to create the base
current drive through Q8. The values of R17 and VCC
control the base drive current.
Equation 18
Transistor requirements for Q8:
VCEO > VCC + VDC
VEBO > VCC
VCBO > VCC + VDC
fT> 200 MHz
1.4.5. Selecting Output Capacitor and Filter
The output capacitor, C9, is subject to large ac currents
from the inductor and should have low equivalent series
resistance (ESR) to minimize ripple voltage on VBAT
.
Equation 19
A 10 F, 100 V electrolytic capacitor provides adequate
filtering in most applications.
An RC filter between C9 and the load reduces ripple
voltage on the VBAT output. This filter should have a
time constant of less than 100 s to maintain loop
stability. See CFILT and RFILT in Figure 2.
(Recommended values for these two components are
.1 F and 15 , respectively.)
1.5. Undervoltage and Overcurrent
Protection
The Si321x dc-dc converter is designed to operate
under a specific input voltage and output loading
condition. When the input voltage goes too low, there is
not enough power from the input to deliver to the output;
so, the dc-dc converter may try to draw excessive
current in an attempt to deliver power to the output. A
similar condition exists when the output ramps up too
fast (during power up, transient loading), short loads, or
unintentionally overloads the output. To prevent
damage to the switching transistor during these
abnormal conditions, the Si321x implements an
undervoltage and overcurrent mechanism.
Figure 5. Protection Sense Circuitry
ICMAX
IBQ7
----------------hFEmin@ICmax

IBQ7 1.3 ICMAX
hFEmin@ICmax
--------------------------------------
=
IBQ7
VCC 0.6 V–
R17
------------------------------- 0.6 V
R16
--------------
–=
R17
VCC 0.7 V–
IBQ7 0.6 V R16
+
----------------------------------------------
=
VRIPPLE ERSMAX IPK =
4.5 k
VDC
R19
0.8 VDC
4.5 k
R20
0.8 VDC
R18
Q7
IC
Si3210
SDCH
SDCL
Pin 8
Pin 9

AN45
8 Rev. 0.61
1.5.1. Undervoltage Lock-Out
The undervoltage lock-out is implemented via the
SDCH pin as shown in Figure 5. When the VDC goes
under a specified value, the current flow through R19
into the SDCH pin goes under 120 A, and it triggers
the Si321x to shut off the dc-dc converter. The equation
for R19 with a specific VDC is given by the following:
Equation 20
R19 should be calculated with a 20% lower value in VDC
to prevent premature low-voltage lock-out. If the voltage
lock-out is activated too often or if the Si321x goes in
and out of low-voltage lock-out and creates an
oscillation-like condition at the input voltage, it indicates
that the input power source has high impedance and
should be replaced with a better power source.
However, the values of R18, R19, and R20 should be
checked against the intended low-voltage lock-out
before any conclusion is made about the input power
source.
1.5.2. Overcurrent Protection
Overcurrent protection is implemented via the SDCL
pin. (See Figure 5.) The circuit is designed to produce
equal current flow from VDC to both the SDCL and
SDCH pins with zero current flow through Q7. (R20 is
set to be equal to R19 and the value of R18 is small.)
When current flows through Q7, it generates a voltage
drop across R18 and reduces the current flow into the
SDCL pin. When the current flow into the SDCL pin is
10.5 A lower compared to the current flow into the
SDCH pin, it triggers the overcurrent protection, and the
Si321x ends the current PWM cycle to prevent
excessive current flow through Q7. The overload
current should be set 20% above the maximum inductor
current to prevent current shut down prematurely.
Equation 21
A fuse or other power overload circuit should be placed
between the VDC power supply and each input of the
ProSLIC dc-dc converter circuit (one per ProSLIC
solution) to protect the switching components (Q7 or
M1) from potential electrical overstress in the event of a
hardware fault condition. For more information
concerning fuse selection, please contact Silicon Labs.
1.6. Output Overvoltage Protection
It is possible for the dc-dc converter to generate
excessively high voltage beyond the voltage rating of
external components. To prevent damage to these
components, a transistor (Q9) is added to limit the VBAT
to a desired level.
Resistors R28 and R29 are connected between VCC
and VBAT as a biasing circuit for the transistor, Q9.
When VBAT approaches the predetermined voltage
level set by R28 and R29, Q9 is turned on and takes
current from R20 away from pin SDCL and,
consequentially, triggers the Si321x to end its current
PWM cycle.
Q9 can be any NPN low voltage (12 V or higher)
general-purpose transistor (2N2222 is recommended).
The equations for R28 and R29 are as follows:
where VBE = .55 V.
where VCLAMP is the clamping voltage for VBAT.
VCLAMP should be set to a voltage less than the voltage
rating of the external components and higher than the
maximum VBAT to be generated for a given application.
1.7. Design Example
Suppose that the system requires 5REN of loading on
1680 ft. of line length with a ringing signal 45 V RMS at
the phone. The fast voltage measurement feature is not
supported, and the system prefers optimization for
power saving. The system has regulated 5 V as the
main supply voltage for the Si321x and an unregulated
12 V dc with a .75 A current rating.
1.7.1. Step 1: Define the Output Requirement
Calculate VTR_PK from Equation 1:
From Equation 2:
R19
VDC
1.5
-------------0.8–
120 A
--------------------------- 4.5 k–=
R18 10.5 A4.5 kR19,20
+
1.2 IOVERLOAD

---------------------------------------------
=
R28 VCC VBE+
148 A
-------------------------------------
=
R29 VCLAMP
148 A
---------------------
=
VTR_PK
VRINGrms 2
7000 NREN
--------------------------------------- 7000
NREN
------------------2 Dist 0.045 160++


=
VTR_PK
45 2
7000 5
-------------------- 7000
5
-------------2 1680 045 160++


76.5==
VBAT VTR_PK VCMR+76.5 1.5+78 V===

AN45
Rev. 0.61 9
From Equation 3:
The output power equation becomes
1.7.2. Step 2: Selecting Output Power Requirement
Set up for power optimization in the active off-hook
mode:
From Equation 5:
From track 1 Equation 6:
Conclusion:
The 2.9 W ringing power is the worst-case power
requirement because the active off-hook power
requirement is much lower (.46 W). The ringing power is
used for the design of the dc-dc converter.
1.7.3. Step 3: Define Input Requirement for the 12 V
DC
From Equation 8:
Experiments with the unregulated 12 V source showed
that the actual VDC voltage drops down to 10 V at input
current equal to .36 A. The adjusted VDC and IIN is as
follows:
The total current drew on the 12 V unregulated supply is
.48 A, which is well within the 12 V unregulated
maximum specification of .75 A.
1.7.4. Step 4: Selecting the Power Inductor
Calculate the IPK using Equation 12:
Calculate the L1 Inductance from Equation 13:
(This frequency was selected to round up the inductor
value to 100 H.)
From Equation 14:
From Equation 15:
IAVG IPK
2

---
2 NREN VTR_PK

7000
------------------------------------------------------
==
IAVG
2576.5
7000
------------------------------ 34.79 mA==
POUT VBAT IAVG 0.0025+78 0.03479 0.0025+==
2.9 W=
ILIM 20 mA Register 65=
IBJTBIAS 4 mA Register 66=
Track 1 Register 71=
VCM 3V Register73=
VOV 9 V Register 66=
IBAT ILIM IBJTBIAS 0.6 80 ILIM IBJTBIAS ++5100++=
24.5 mA=
POFFHOOK IBAT VCM VOV ILIM RLINE ++=
24.5 mA 3 9 20 mA 2 20000.045 160+++.46 W==
IIN
POUT
VIN 60%
--------------------------- 2.9
12 0.6
---------------------0.4 A===
IIN
POUT
VIN 60%
--------------------------- 2.9
10 0.6
---------------------0.48 A===
VDC 10 V=
IPK
2POUT VBAT VDC +
EFF VBAT VDC

-------------------------------------------------------1.14 A==
L2POUT
EFF IPK2 Fs
-----------------------------------------100 H==
Fs 89.5 kHz=
T1
89500
---------------- 11.2 S==
Period Register 92 11.2 S
61 nS
--------------------- 183 b7 H===
Delay Register 93 tOFFMAX
61 nS
-----------------------0.98 100 H75
61 nS
-----------------------------------------------------
==
21 15 H==

AN45
10 Rev. 0.61
1.7.5. Step 5: Selecting the Q7 Switching Transistor
Transistor requirement:
The Zetex FZT953 bipolar transistor meets all of the
above requirements and its HFE gain at IPK = 1.14 A is
100.
Let IR16 = 3 mA for adequate Q7 base capacitor
discharge.
From Equation 16:
1.7.6. Step 6: Select the Base Drive Circuit
Q8 transistor requirement:
The general purpose 2222 transistor meets all of the
above requirements.
Calculate the value for R17:
Base current drive requirement for Q7
From Equation 17:
From Equation 18:
1.7.7. Step 7: Under Voltage Circuit Design
Set under voltage lock-out to be 20% lower than the
minimum VDC.
From Equation 20:
1.7.8. Step 8: Overcurrent Protection
From Equation 21:
1.7.9. Step 9: Output Overvoltage Protection
VBAT max = 78 V (during ringing). See Table 2 for
voltage ratings.
Therefore, VCLAMP must be greater than 78 V but less
than 88 V: VCLAMP = 85 V.
If VCC = 5 V, then
VCEO VBAT VDC +78 10+88 V==
VEBO VCC 8V=
VCBO VBAT VCC VDC
++ 78 5 10++ 93 V==
ICMAX IPK 1.14 A=
Speed:fT100 MHz
R16 0.6
0.003
---------------200 ==
VCEO VCC VDC +510+15 V===
VEBO VCC 5V==
VCBO VCC VDC
+510+15 V===
Speed:fT200 MHz
IBQ7
1.3 IMAX 
HFE
---------------------------1.3 0.98
100
--------------------------12.74 mA===
R17 VCC 0.6–
IBQ7 0.6 R16+
------------------------------------------275 ==
Table 2. Component Voltage Rating
Components Voltage
Parameter
Voltage
Rating
C9, C26, C3, C4, C5, C6 VC– 1.5 98.5
Q1–Q4 (2N5401) VCEO 150
Q5, Q6 VCEO 150
Q7 VCEO – VDC 100 – 12 = 88
VUNDER 1–20%VDC 8 V==
R19 VUNDER 0.8–
120 A
------------------------------------


4500–56K==
R19 R=20 56K=
IOVERLOAD 1.2 IMAX 1.176 A==
R18 10.5 A 4500 R19+
IOVERLOAD
--------------------------------------------------------------- 0.5 ==
R28 5.55+V
148 A
---------------------------- 37.4k==
R29 85 V
148 A
--------------------574k==

AN45
Rev. 0.61 11
1.8. MOSFET/Transformer Design
DC-DC Converter
The MOSFET/transformer dc-dc converter solution
offers higher power efficiency than the BJT/inductor
solutions and is the preferred solution for applications
using low VDC input voltages.
The transformer dc-dc converter circuit is shown in
Figure 6. R16, R17, Q7, and Q8 are eliminated. The M1
MOSFET is the main power-switching component in this
design. The Si321xM version of the ProSLIC is used to
directly drive the M1 MOSFET using the DCFF pinout.
Figure 6. Transformer DC-DC Converter
All relevant design equations for the inductor dc-dc
converter are applied in the same manner for the
transformer dc-dc converter except for the following
equations.
1.8.1. Equation 10A
During the off interval, the switch current goes to 0 and
the primary voltage is the reflection of the VBAT
:
VP=NVBAT
. The transformer mutual primary current
equation becomes
In the discontinuous mode, the current goes to 0 at the
end of the off time interval:
Solving for tOFF – MAX:
Equation 10A
Where N is the transformer turn ratio:
NPis the number of turn of the primary winding.
NSis the number of turn of the secondary winding.
1.8.2. Equation 12A:
Deriving the peak current equation based on the new
tOFF – MAX 10A equation:
Equation 12A
1.8.3. Equation 13A
Use the former Equation 13 and solve for FS.
Equation 13A
C14
0.1 uF
VBAT
R21 1534
33
9
8
DCDRV
DCFF
SDCL
SDCH
C27
470pF
R18
RVDC
Transformer
T1
2
6
10
1
4
3
Note 2
R20
RMONL
C9
10 uF
CBAT
CFILT
International Rectifier
Note 1
D1
ES1D
DSW
VDC
RFILT
R19
RMONH
R22 22
C26
0.1 uF
M1
IRLL014N
1
2
3
C25
10 uF
R21
RVDCRVDCRVDCRVDC
Fuse
VCC
R28*
R29*
VBAT
Q9
2222
R23
200k
Si3210M
it IPK
NV
BAT

LM
------------------------ t–=
0I
PK
NV
BAT

LM
------------------------ tOFF –MAX
–=
tOFF –MAX
IPK L
NV
BAT

------------------------
=
NNP
NS
-------
=
IPK
2POUT NV
BAT VDC

EFF NV
BAT VDC

-----------------------------------------------------------------------
=
FS
2POUT
EFF LI
PK2

-------------------------------------
=

AN45
12 Rev. 0.61
1.8.4. Switching MOSFET Requirements
To optimize the Si321xM dc-dc converter performance,
logic level MOSFET is recommended as the dc-dc
switching element. This allows the DCFF pin to drive
the MOSFET directly.
1.8.5. Power Transformer
A transformer was designed for the Si321x dc-dc
converter based on the TDK PC40EF12.6 E core. This
transformer has three primary windings connected in
series (see Figure 7) to handle all VDC voltage ranging
from 3 V to 35 V (consult the factory for higher VDC).
The secondary winding can generates up to 94.5 V
VBAT at any in range VDC input. Table 4 shows the
voltage and the transformer ratio N value for each of the
winding connection.
Figure 7. Winding Connections
Figure 8. Recommended PCB Layout
Core Material: E core, TDK PC40EF12.6-Z, or
equivalent
Air Gap: Center leg .088 mm
Bobbin: 10 pin (ready for pick and place)
Winding:
W1–2 = W2–3 = W3–4 = 8T, #28 wire
W6–10 = 40T, #33 wire
Inductance:
W1–2 = 11.3 H ±10% (only one winding needs to be
tested)
W1–3 = 45.2 µH ±10%
W1–4 = 107 µH ±10%
Table 3. Switch MOSFET M1
VDSS >NxV
BAT +V DC
IDMAX>3xI
PK at VGS =3V
RDS 0n < .2 at IDMAX
VGS (th) < 2 V
CISS (input cap) < 300 pF
COSS (output cap) < 60 pF
CRSS (reverse t. cap) < 30 pF
Total gate charge: 14 nC
tON (VDD =50V,I
D=4A)<10ns
tOFF (VDD =50V,I
D=4A)<20ns
Table 4. Transformer Winding Connection
VDC Voltage Winding
Connection
Ratio N Primary
Inductance
3 V to 9 V Winding 1–2 .2 11.3 H
10 V to 15 V Winding 1–3 .4 45.2 H
16 V to 35 V Winding 1–4 .6 107 H
1
2
3
4
6
10
17.7
9.4
2.54
4.17
1.2
110
56
Component Side

AN45
Rev. 0.61 13
1.8.6. MOSFET/Transformer DC-DC Converter
Design Procedure
The transformer dc-dc converter design procedure is
similar to the design of the inductor dc-dc converter.
Below are design steps based on the BJT/inductor
design example.
1. Step 1 to step 2 are identical to the BJT/inductor
dc-dc converter
2. In step 3, use 75% efficiency for input power
calculation.
3. In step 4, the peak current is calculated using
Equation 12A; the maximum delay time for
Register 93 is calculated using Equation 10A; the
switching frequency FSand the period for the
Register 92 is calculated using Equation 13A. The
inductance of inductor L in equations 10A and 13A is
selected from Table 4 based on the VDC voltage
level.
4. Step 5 now handles the selection of the M1
MOSFET based on the requirements on Table 3.
5. Step 6 is no longer needed since the drive transistor
Q8 is eliminated.
6. Steps 7 and 8 are the same.
7. In step 9, use the voltage rating for M1 instead of
Q1. The voltage parameter for M1 is as follows:
8. Other components in the circuit that are not
discussed above should use the component values
recommended in Figure 6.
VVDSS
N
-------------- VDC–=

AN45
14 Rev. 0.61
NOTES:

AN45
Rev. 0.61 15
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 0.5
Equation 6
Changed RLINE to RLOOPMAX.
“1.2.1. In the Off-Hook State”
Updated text.
“1.7.1. Step 1: Define the Output Requirement”
Added +160 to first equation.
“1.7.2. Step 2: Selecting Output Power Requirement”
Added +160 to last equation.
Changed =.3822 to .46 W.
Changed .312 to .46 in last paragraph.
Added SLIC series resistance.
VCMR adjustment.
Changed Si3210 to Si321x throughout.
Revision 0.5 to Revision 0.6
Updated "1.8.4. Switching MOSFET Requirements"
on page 12.
Updated text.
Updated "1.8.5. Power Transformer" on page 12.
Correct the number of turns for W1-2 from 20T to
4T.
Revision 0.6 to Revision 0.61
Updated all FZT955 references to FZT953.

AN45
16 Rev. 0.61
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