Silicon Laboratories Si84xxISO User manual

Rev. 0.3 8/10 Copyright © 2010 by Silicon Laboratories Si84xxISO-EVB UG
Si84xxISO-EVB UG
Si84XXISO EVALUATION BOARD USER’SGUIDE
1. Introduction
The Si84xxISO evaluation board allows designers to evaluate Silicon Lab's family of CMOS ultra-low-power
isolators. These isolators are CMOS devices employing RF coupler technology to transmit digital information
across an isolation barrier. Very high speed operation at low power levels is achieved. These products are based
on Silicon Laboratories’ proprietary RF isolation technology and offer shorter propagation delays, lower power
consumption, improved noise immunity, smaller installed size, and more stable operation with temperature and age
versus opto couplers. The Si841x/2x/3x/4x/5x/6x include up to six unidirectional isolated channels, permitting data
transmission up to 150 Mbps. The Si840x isolator series consists of single-package galvanic isolation solutions for
I2C, SMBus, and PMBus serial port applications. For more information, refer to the respective family data sheets.
A summary of the benefits provided by the Silicon Laboratories Si84xx CMOS Digital Isolator family includes:
Robust Noise Tolerance:
5.0 kV, 2.5 kV, and 1.0 kV Isolation Ratings
Up to 50 V/m Electric-field immunity
> 1000 A/m Magnetic-field immunity
25 kV/µs CMTI
FCC Class B Compliant
Class-leading ESD Performance:
4 kV HBM, 2 kV CDM, 400 V MM
Ultra Low Power Operation:
< 1.4 mA/Channel @ 1 Mbps
200 µA standby mode
High Speed Operation:
DC–150 Mbps from –40 to 125 °C
< 250 ps (peak) Jitter
Precise Timing:
1.5 ns pulse width distortion
0.5 ns channel-channel matching
2 ns pulse width skew
I2C Compatible Isolators:
Bidirectional isolated Serial Data (SDA) and Serial Clock
Data Rates up to 1.7 Mbps
35 mA open drain I/O
Flexible Packaging Options:
NB SOIC-8, WB SOIC-16, NB SOIC-16
RoHS compliant

Si84xxISO-EVB UG
2 Rev. 0.3
2. Kit Contents
The Si84xxISO Evaluation Kit contains the following items:
Si84xxISO based evaluation board (Si84xxISO-EVB or Si84xx5kVISO-EVB) shown in Figures 1 and 2.
Si8400, Si8421, Si8442, Si8463, Si8420 (5 kV), and Si8422 (5 kV) CMOS digital isolators installed on the
evaluation board
Figure 1. Si84xxISO Evaluation Board Overview

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Figure 2. Si84xx5kVISO Evaluation Board Overview

Si84xxISO-EVB UG
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3. Hardware Overview and Setup
The Si84xxISO evaluation board comes populated with an Si8400 (isolated I2C), Si8421 (2-channel digital isolator,
one forward, one reverse), Si8442 (4-channel digital isolator, two forward, two reverse), and Si8463 (6-channel
digital isolator, three forward, three reverse) installed. The Si84xx5kVISO-EVB adds the Si8420 and Si8422 5 kV
family members. The board is designed to be powered from two separate 5 V supplies (500 mA) that power all the
isolators on the board. Power is applied to the board before evaluating any isolated channel. Power is applied to
the Si84xxISO-EVB by connecting 5 V supplies to the topmost supply terminals (VDD1 and GND1, VDD2 and
GND2). Power is applied to the Si84xx5kVISO-EVB by applying 5 V supplies to the topmost and middle power
terminals (VDD1 and GND1, VDD2 and GND2). The top power terminals power the 2.5 kV isolators. The middle
power terminals power the 5 kV isolators. Supplies as low as 2.7 V can be used. If a user wants to evaluate an
isolator other than the ones populated, this can be accomplished by removing the footprint-compatible device
installed on the evaluation board and replacing it with the desired isolator device. Figures 3 and 5 provide
silkscreen overviews of the boards.
Figure 3. Si84xxISO Evaluation Board Silkscreen

Si84xxISO-EVB UG
Rev. 0.3 5
Figure 4. Si84xx5kVISO Evaluation Board Silkscreen

Si84xxISO-EVB UG
6 Rev. 0.3
3.1. Digital Isolator Considerations
The Si84xxISO evaluation board (see Figure 1 on page 2) provides a means to evaluate the Si841x,2x,3x,4x,5x,6x
digital isolator families as well as the Si8400 isolated I2C family. After power has been supplied to the board,
connect a digital input signal (5 Vpeak max, with desired clock frequency up to 150 Mbps) to the desired input
channel. To view the isolated channel’s data transmission, connect a scope probe to the output channel of interest.
There are various inputs and outputs on either side of the board depending on the device one chooses to evaluate,
as indicated by the silk screen. The board can be used to measure propagation delay, pulse-width distortion,
channel-channel matching, pulse-width skew, and various other parameters.
The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination
of the values of the on-chip series termination resistor and the channel resistance of the output driver FET. When
driving loads where transmission line effects will be a factor, output pins should be terminated with 50 controlled
impedance PCB traces.
Figure 5 illustrates the Si8421 transmitting a 500 kHz (5 Vpeak) signal through the Si8421. VDD1 and VDD2 were
powered from 5 V. Channel 1 illustrates the input, and Channel 2 illustrates the output.
Figure 5. 500 kHz (5 V Peak) Signal

Si84xxISO-EVB UG
Rev. 0.3 7
3.2. I2C Isolator Considerations
After power has been supplied to the board, connect a digital square wave input (5 Vpeak max, with desired clock
frequency up to 1.7 MHz) to the desired input channel. The Si8400 I2C isolator has 1 kpull-up resistors already
installed. If these resistors are redundant with another board that is being used to evaluate the Si8400, the user
should remove the redundant pull-up resistors to accommodate adequate drive current for the test being
performed. Moreover, note that the Si8463 can be replaced with an Si8405 (Bidirectional I2C Isolator with two
unidirectional digital channels). Pull-up resistors of 1 kare already installed to accommodate the Si8405’s
evaluation. Pull-up jumpers J1, J2, J3, and J4 need to be installed to evaluate the Si8405. They will need to be
removed or not installed (default from factory) to evaluate the Si8463.
Figure 6 illustrates Side B Pulling Up, with Side A following for the Si8400. The Si8400 was powered from 5 V on
both sides with a 100 kHz input test signal.
Figure 6. Side B Pulling Up, Side A Following
Note: The test points in front of each device have 1 mm spacing. If desired, the test points can be replaced with a 1 mm
spacing terminal block to assist in evaluation.

Si84xxISO-EVB UG
8 Rev. 0.3
4. Si84xxISO Evaluation Board Schematic
VDD1(5V) VDD2(5V)
VDD1(5V) VDD2(5V)
VDD1(5V) VDD2(5V)
VDD1(5V) VDD2(5V)
Si8400 Populated
Si8421 Populated
Si8442 Populated
Si8463 Populated
TP11TP11 TP13TP13
TP40TP40
TP22TP22
ISOLATION
U2 Si8421
ISOLATION
U2 Si8421
VDD1 1
VDD2 8
B2 6
GND1
4
A2
3
GND2
5
A1
2B1 7
J2 JUMPER J2 JUMPER
1 2
TP4TP4
C3 1uF C3 1uF R2
1K R2 1K
C1 1uF C1 1uF
TP6TP6
R7 1K R7 1K
TP1TP1
TP19TP19 TP21TP21
TP9TP9
TP27TP27
C8 1uF C8 1uF
R8 1K R8 1K
TP25TP25
TP12TP12
J4
JUMPER
J4
JUMPER
1 2
C5 1uF C5 1uF
TP29TP29
TP14TP14
TP34TP34 TP31TP31
R3 1K R3 1K
C2 1uF C2 1uF
TP42TP42
TP35TP35
C4 1uF C4 1uF
ISOLATION
U4 Si8463
ISOLATION
U4 Si8463
VDD1 1
VDD2 16
GND2
9
GND1
8
A1
2
A2
3
B3 13 B4 12
A3
4
A4
5
B1 15 B2 14
A5
6B5 11
A6
7B6 10
TP37TP37
J3
JUMPER
J3
JUMPER
1 2
TP20TP20
TP7TP7
TP26TP26
R1
1K
R1
1K
TP41TP41
TP15TP15
C6 1uF C6 1uF
ISOLATION
U3 Si8442
ISOLATION
U3 Si8442
VDD1 1
VDD2 16
GND2
9
GND1
8GND1
2
GND2
15
A1
3
A2
4
B3 12 B4 11
A3
5
A4
6
B1 14 B2 13
EN1
7EN2 10
TP30TP30
TP23TP23
R6
1K
R6
1K
R4
1K
R4
1K
TP28TP28
TP32TP32 TP24TP24
R5
1K
R5
1K
J1
JUMPER
J1
JUMPER
1 2
C7 1uF C7 1uF
TP36TP36
TP2TP2
TP38TP38
TP3TP3
TP39TP39
TP5TP5
ISOLATION
U1 Si8400
ISOLATION
U1 Si8400
AVDD 1
BVDD 8
BSCL 6
AGND
4
ASCL
3
BGND
5
ASDA
2BSDA 7
TP10TP10
TP18TP18
TP8TP8
TP33TP33
TP16TP16
TP17TP17
Figure 7. Si84xxISO Evaluation Board Schematic

Si84xxISO-EVB UG
Rev. 0.3 9
5. Si84xx5kVISO Evaluation Board Schematics
VDD1(5V) VDD2(5V)
VDD1(5V) VDD2(5V)
VDD1(5V) VDD2(5V)
VDD1(5V) VDD2(5V)
Si8400 Populated
Si8421 Populated
Si8442 Populated
Si8463 Populated
TP17 WHITE TP17 WHITE
TP36 WHITE TP36 WHITE
ISOLATION
U3 Si8442
ISOLATION
U3 Si8442
VDD1 1
VDD2 16
GND2
9
GND1
8GND1
2
GND2
15
A1
3
A2
4
B3 12 B4 11
A3
5
A4
6
B1 14 B2 13
EN1
7EN2 10
TP3 WHITE TP3 WHITE
R4
1K
R4
1K
J3
JUMPER
J3
JUMPER
1 2
TP34 WHITE TP34 WHITE
TP11 WHITE TP11 WHITE
ISOLATION
U1 Si8400
ISOLATION
U1 Si8400
AVDD 1
BVDD 8
BSCL 6
AGND
4
ASCL
3
BGND
5
ASDA
2BSDA 7
C6 1uF C6 1uF
TP25 WHITE TP25 WHITE
R8 1K R8 1K
TP1 WHITE TP1 WHITE
TP6 WHITE TP6 WHITE
TP39 WHITE TP39 WHITE
TP2 WHITE TP2 WHITE
TP15 WHITE TP15 WHITE
TP35 WHITE TP35 WHITE
TP14 WHITE TP14 WHITE
J2 JUMPER J2 JUMPER
1 2
C7 1uF C7 1uF
TP30 WHITE TP30 WHITE TP38 WHITE TP38 WHITE
R6
1K
R6
1K
TP23 WHITE TP23 WHITE
R3 1K R3 1K
C8 1uF C8 1uF
TP5 WHITE TP5 WHITE
TP41 WHITE TP41 WHITE
TP27 WHITE TP27 WHITE
C3 1uF C3 1uF
TP10 WHITE TP10 WHITE
J1
JUMPER
J1
JUMPER
1 2
C2 1uF C2 1uF
TP13 WHITE TP13 WHITE
TP42 WHITE TP42 WHITE
TP29 WHITE TP29 WHITE
C5 1uF C5 1uF
TP9 WHITE TP9 WHITE
TP21 WHITE TP21 WHITE
R1
1K
R1
1K
TP37 WHITE TP37 WHITE
ISOLATION
U2 Si8421
ISOLATION
U2 Si8421
VDD1 1
VDD2 8
B2 6
GND1
4
A2
3
GND2
5
A1
2B1 7
TP33 WHITE TP33 WHITE
TP32 WHITE TP32 WHITE
TP20 WHITE TP20 WHITE
J4
JUMPER
J4
JUMPER
1 2
TP22 WHITE TP22 WHITE
C4 1uF C4 1uF
TP19 WHITE TP19 WHITE
R7 1K R7 1K
TP8 WHITE TP8 WHITE
TP16 WHITE TP16 WHITE
R5
1K
R5
1K
TP24 WHITE TP24 WHITE
C1 1uF C1 1uF
R2 1K R2 1K
TP4 WHITE TP4 WHITE
TP28TP28
TP7 WHITE TP7 WHITE
ISOLATION
U4 Si8463
ISOLATION
U4 Si8463
VDD1 1
VDD2 16
GND2
9
GND1
8
A1
2
A2
3
B3 13 B4 12
A3
4
A4
5
B1 15 B2 14
A5
6B5 11
A6
7B6 10
TP31 WHITE TP31 WHITE
TP12 WHITE TP12 WHITE
TP40 WHITE TP40 WHITE
TP18 WHITE TP18 WHITE
TP26 WHITE TP26 WHITE
Figure 8. Si84xx5kVISO Evaluation Board Schematic (1 of 2)

Si84xxISO-EVB UG
10 Rev. 0.3
VDD1(5V)_5kV VDD2(5V)_5kV
VDD1(5V)_5kV VDD2(5V)_5kV
Si8420 Populated
Si8422 Populated
U5
Si8420
U5
Si8420
GND1
1
NC
2
A1
4
GND1
7
A2
5
NC 10
NC
8GND2 9
B2 12
NC 11
VDD1
3
NC
6
B1 13
VDD2 14
NC 15
GND2 16
TP53 WHITE TP53 WHITE
C12 1uF C12 1uF
C9 1uF C9 1uF
TP46 WHITE TP46 WHITE TP48 WHITE TP48 WHITE
TP51 WHITE TP51 WHITE
TP54 WHITE TP54 WHITE
C10 1uF C10 1uF
TP59 WHITE TP59 WHITE
TP55 WHITE TP55 WHITE
TP60 WHITE TP60 WHITE
TP57 WHITE TP57 WHITE
TP49 WHITE TP49 WHITE
TP56 WHITE TP56 WHITE TP58 WHITE TP58 WHITE
U6
Si8422
U6
Si8422
GND1
1
NC
2
A1
4
GND1
7
A2
5
NC 10
NC
8GND2 9
B2 12
NC 11
VDD1
3
NC
6
B1 13
VDD2 14
NC 15
GND2 16
TP50 WHITE TP50 WHITE
TP44 WHITE TP44 WHITE
TP52 WHITE TP52 WHITE
TP43 WHITE TP43 WHITE TP45 WHITE TP45 WHITE TP47 WHITE TP47 WHITE
C11 1uF C11 1uF
Figure 9. Si84xx5kVISO Evaluation Board Schematic (2 of 2)

Si84xxISO-EVB UG
Rev. 0.3 11
6. Bill of Materials
Table 1. Si84xxISO Evaluation Board Bill of Materials
Item Qty Reference Value Mfr Part Number Mfr
18 C1,C2,C3,C4,
C5,C6,C7,C8 1 µF C0603X5R250-105K Venkel
2 4 J1,J2,J3,J4 Jumper TSW-102-07-T-S Samtec
38 R1,R2,R3,R4,
R5,R6,R7,R8 1kCR0603-10W-1001F Venkel
442
TP1,TP2,TP3,TP4,
TP5,TP6,TP7,TP8,
TP9,TP10,TP11,
TP12,TP13,TP14,
TP15,TP16,TP17,
TP18,TP19,TP20,
TP21,TP22,TP23,
TP24,TP25,TP26,
TP27,TP28,TP29,
TP30,TP31,TP32,
TP33,TP34,TP35,
TP36,TP37,TP38,
TP39,TP40,TP41,
TP42
White 151-201-RC Kobiconn
5 1 U1 Si8400 Si8400AB-A-IS Silicon Labs
6 1 U2 Si8421 Si8421AB-C-IS1 Silicon Labs
7 1 U3 Si8442 Si8442BB-C-IS Silicon Labs
8 1 U4 Si8463 Si8463BB-A-IS1 Silicon Labs

Si84xxISO-EVB UG
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Table 2. Si84xx5kVISO Evaluation Board Bill of Materials
Item Qty Reference Value Mfr Part Number Mfr
112
C1,C2,C3,C4,C5,C6,C7,
C8,C9,C10,C11,C12 1uF C0603X5R250-105K Venkel
2 4 J1,J2,J3,J4 JUMPER TSW-102-07-T-S Samtec
3 8 R1,R2,R3,R4,R5,R6,R7,R8 1 kCR0603-10W-1001F Venkel
460
TP1,TP2,TP3,TP4,TP5,
TP6,TP7,TP8,TP9,TP10,
TP11,TP12,TP13,TP14,
TP15,TP16,TP17,TP18,
TP19,TP20,TP21,TP22,
TP23,TP24,TP25,TP26,
TP27,TP28,TP29,TP30,
TP31,TP32,TP33,TP34,
TP35,TP36,TP37,TP38,
TP39,TP40,TP41,TP42,
TP43,TP44,TP45,TP46,
TP47,TP48,TP49,TP50,
TP51,TP52,TP53,TP54,
TP55,TP56,TP57,TP58,
TP59,TP60
WHITE 151-201-RC Kobiconn
5 1 U1 Si8400 Si8400AB-A-IS Silicon Labs
6 1 U2 Si8421 Si8421AB-C-IS1 Silicon Labs
7 1 U3 Si8442 Si8442BB-C-IS Silicon Labs
8 1 U4 Si8463 Si8463BB-A-IS1 Silicon Labs
9 1 U5 Si8420 Si8420BD-A-IS Silicon Labs
10 1 U6 Si8422 Si8422BD-B-IS Silicon Labs
11 6 Standoff
12 6 Standoff
screw

Si84xxISO-EVB UG
Rev. 0.3 13
7. Ordering Guide
Table 3. Si84xxISO Evaluation Board Ordering Guide
Ordering Part Number (OPN) Description
Si84XXISO-KIT Si84xx CMOS digital isolator evaluation board kit (2.5 kV, 5 kV)

Si84xxISO-EVB UG
14 Rev. 0.3
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Added Si84xx5kVISO-EVB descriptive details
throughout.
Added Figure 2 on page 3.
Added Figure 4 on page 5.
Added Figure 8 on page 9.
Added Figure 9 on page 10.
Added Table 2.
Revision 0.2 to Revision 0.3
Replaced “ISOpro” with “CMOS” in text.
Added "7. Ordering Guide" on page 13.

Si84xxISO-EVB UG
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NOTES:

Si84xxISO-EVB UG
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CONTACT INFORMATION
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Fax: 1+[phone]
Toll Free: 1+[phone]
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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