Silicon Laboratories Si5372 User manual

UG372: Si5372 Evaluation Board User’s
Guide
The Si5372-EVB is used for evaluating the Si5372 Any-Frequency, Any-Output, Jitter
Attenuating Clock Multiplier. The Si5372 combines 4th generation DSPLL and Multi-
synth™ technologies to enable any-frequency clock generation for applications that re-
quire the highest level of jitter performance. There are two different EVBs for the
Si5372. There is an A grade which uses an external XTAL reference and there is a J
grade which has an internal XTAL reference. This user guide is intended for all ver-
sions of the Si5372 EVB. The device grade and revision is distinguished by a white 1
inch x 0.187 inch label installed in the lower left hand corner of the board. In the exam-
ple below, the label "SI5372J-A-EB" indicates the evaluation board has been assem-
bled with an Si5372 device, Grade J, Revision A, installed. (For ordering purposes on-
ly, the terms “EB” and “EVB” refer to the board and the kit respectively. For the purpose
of this document, the terms are synonymous in context.)The device The Si5372-EVB
has two independent input clocks and four independent output clocks. The Si5372-EVB
can be controlled and configured using the ClockBuilderPro™ (CBPro) software tool.
EVB FEATURES:
• Si5372A-A-EB for evaluating external
XTAL version Si5372A
•Onboard 48 MHz XTAL or Reference
SMA Inputs allow holdover mode of
operation on the Si5372.
• Si5372J-A-EB for evaluating internal XTAL
version Si5372J
• Powered from USB port or external power
supply.
•CBPro™ GUI-programmable VDD supply
allows the device to operate from 3.3, 2.5,
or 1.8 V.
• CBPro GUI-programmable VDDO supplies
allow each of the ten outputs to have its
own supply voltage, selectable from 3.3,
2.5, or 1.8 V.
• CBPro GUI-controlled voltage, current,
and power measurements of VDD and all
VDDO supplies.
• Status LEDs for power supplies and
control/status signals of Si5372.
• SMA connectors for input clocks, output
clocks, and optional external timing
reference clock.
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1. Functional Block Diagram
A functional block diagram of the Si5372-EVB is shown below. Keep in mind the J grade does not use an external XTAL or reference
and does not use the XA/XB pins. This EVB can be connected to a PC via the main USB connector for programming, control, and
monitoring. See or Section 2. Quick Start for more information.
Si5372
OUT_0
OUT_0B
Output
Termination
OUT_1
OUT_1B
Output
Termination
OUT_2
OUT_2B
Output
Termination
OUT_3
OUT_3B
Output
Termination
48 MHz
XTAL
Input
Termination
Input
Termination
XA
XB
IN_0
IN_0B
IN_1
IN_1B
Power Supply
C8051F380
MCU
+
Peripherals
I2C/SPI Bus
VDDO_0
VDD_Core
VDD_3.3
VDDO_1 VDDO_2 VDDO_3
VDDO_0 VDD_Core VDD_3.3 VDDO_1 VDDO_2 VDDO_3
Main USB
Connector
Ext +5V
Connector
I2C/SPI Bus
+5V_USB
+5V_Ext
VDDMCU
Input Clock 0 {
Input Clock 1 {
}Output Clock 0
}Output Clock 1
}Output Clock 2
}Output Clock 3
Power only
Control/
Status
INTR
Alarm_Status
Figure 1.1. Si5372-EVB Functional Block Diagram
UG372: Si5372 Evaluation Board User’s Guide
Functional Block Diagram
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2. Quick Start
1. Install ClockBuilderPro™ desktop software: http://www.silabs.com/CBPro.
• Installation instructions and the user’s guide for ClockBuilderPro can also be found at the download link shown above.
2. Connect a USB cable from the Si5372-EVB to the PC where the software is installed.
3. Leave the jumpers as installed from the factory, and launch the ClockBuilderPro™ software.
4. You can use ClockBuilderPro™ to create, download, and run a frequency plan on the Si5372-EVB.
5. Contact Silicon Labs for the Si5372 data sheet.
UG372: Si5372 Evaluation Board User’s Guide
Quick Start
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3. Jumper Defaults
Table 3.1. Si5372 EVB Jumper Defaults
Location Type I = Installed
0 = Open
Location Type I = Installed
0 = Open
JP1 2 pin I JP14 2 pin O
JP2 2 pin I JP15 2 pin O
JP3 2 pin O JP16 3 pin all open
JP4 2 pin O JP17 3 pin all open
JP5 3 pin 1 to 2 JP18 2 pin O
JP6 2 pin O JP19 2 pin O
JP7 2 pin O JP20 3 pin all open
JP8 2 pin O JP21 3 pin all open
JP9 2 pin O JP22 2 pin O
JP10 2 pin O JP23 2 pin O
JP11 2 pin O JP24 3 pin all open
JP12 2 pin O
JP13 2 pin O JP17 5x2 Hdr All 5 installed
Note:
1. Refer to the Si5372 EVB Schematics for the functionality associated with each jumper.
UG372: Si5372 Evaluation Board User’s Guide
Jumper Defaults
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4. Status LEDs
Table 4.1. Si5372 EVB Status LEDs
Location Silkscreen Color Status Function Indication
D5 INTRB Blue DUT Interrupt
D7 LOLB Blue DUT Loss of Lock
D8 LOSXAXBB Blue DUT Loss of Reference
D11 +5V MAIN Green Main USB +5 V present
D12 READY Green MCU Ready
D13 BUSY Green MCU Busy
D11 is illuminated when USB +5 V supply voltage is present. D12 and D13 are status LEDs showing on-board MCU activity.
Figure 4.1. Status LEDs
UG372: Si5372 Evaluation Board User’s Guide
Status LEDs
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5. External Reference Input (XA/XB)
An external reference (XTAL) is required for Grade A in combination with the internal oscillator to produce an ultra-low jitter reference
clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. The Si5372-EVB for these versions can
also accommodate an external reference clock instead of a crystal. To evaluate the device with a REFCLK, C93 and C94 must be
populated and the XTAL removed (see the figure below). The REFCLK can then be applied to J25 and J26. In the case of the
Si5372J-A which is the grade with the internal XTAL, there will be no external XTAL supplied on the board and no input from
Ref_XA and Ref_XB. In this case it is advised to remove any resistor connections to XTAL1 and XTAL2 on component Y1.
Figure 5.1. External Reference Input Circuit
UG372: Si5372 Evaluation Board User’s Guide
External Reference Input (XA/XB)
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6. Clock Input Circuits (INx/INxB and FB-IN/FB-INB)
The Si5372-EVB has four SMA connectors (IN0/IN0B and IN1/IN1B) for receiving external clock signals. All input clocks are terminated,
as shown in the figure below.
Input clocks are ac-coupled and 50 Ω terminated. This represents four differential input clock pairs. Single-ended clocks can be used by
appropriately driving one side of the differential pair with a single-ended clock. See the Si5372 data sheet for details on how to config-
ure inputs as single-ended.
Figure 6.1. Input Clock Termination Circuit
UG372: Si5372 Evaluation Board User’s Guide
Clock Input Circuits (INx/INxB and FB-IN/FB-INB)
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7. Clock Output Circuits (OUTx/OUTxB)
Each of the eight outputs (four differential pairs) is ac-coupled to its respective SMA connector. The output clock termination circuit is
shown in the figure below. The output signal has no dc bias. If dc coupling is required, the ac coupling capacitors can be replaced with
a resistor of appropriate value. The Si5372-EVB provides pads for optional output termination resistors and/or low frequency capacitors.
Note: Components with schematic “NI” designation are not normally populated on the Si5372-EVB and provide locations on the PCB
for optional dc/ac terminations by the end user.
Figure 7.1. Output Clock Termination Circuit
UG372: Si5372 Evaluation Board User’s Guide
Clock Output Circuits (OUTx/OUTxB)
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8. Installing ClockBuilder Pro Desktop Software
To install the CBOPro software on any Windows 7 (or above) PC, go to http://www.silabs.com/CBPro and download the ClockBuilder
Pro software.
Installation instructions and User’s Guide for ClockBuilder Pro can be found at the download link shown above.
UG372: Si5372 Evaluation Board User’s Guide
Installing ClockBuilder Pro Desktop Software
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9. Using Si5372 EVB
9.1 Connecting the EVB to Your Host PC
Once ClockBuilderPro™ software is installed, connect the software to the EVB with a USB cable, as shown in the figure below.
Figure 9.1. EVB Connection Diagram
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Using Si5372 EVB
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9.2 Main Features of ClockBuilderPro™ Applications
The ClockBuilderPro installer installs two main applications: the ClockBuilderPro Wizard and the EVB GUI.
Figure 9.2. Application #1: ClockBuilderPro Wizard
Use the CBPro Wizard to do the following:
•Create a new design.
• Review or edit an existing design.
• Export: create in-system programming.
• Convert Existing Project/NVM File
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Using Si5372 EVB
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Figure 9.3. Application #2: EVB GUI
Use the EVB GUI to do the following:
• Download configuration to EVB’s DUT (Si5372).
• Control the EVB’s regulators.
• Monitor voltage, current, power on the EVB.
9.3 Common ClockBuilderPro Workflow Scenarios
There are three common workflow scenarios when using CBPro and the Si5372 EVB. These workflow scenarios are as follows:
Workflow Scenario #1: Testing a Silicon Labs-created Default Configuration
Workflow Scenario #2: Modifying the Default Silicon Labs-created Device Configuration
Workflow Scenario #3: Testing a User-created Device Configuration
Each scenario is described in more detail in the following sections.
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Using Si5372 EVB
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9.4 Workflow Scenario #1: Testing a Silicon Labs Created Default Configuration
The flow for using the EVB GUI to initialize and control a device on the EVB is as follows.
1. Once the PC and EVB are connected, launch ClockBuilder Pro by clicking on this icon on your PC’s desktop.
Figure 9.4. ClockBuilderPro Desktop Icon
2. When the EVB is detected, select the "Open Default Plan" button on the Wizard’s main menu. CBPro automatically detects the
EVB and device type.
Figure 9.5. Open Default Plan
3. Once you open the default plan (based on your EVB model number), a popup window opens.
Figure 9.6. Write Design to EVB Dialog
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4. Select "Yes" to write the default plan to the Si5372 device mounted on your EVB. This ensures the device is completely reconfig-
ured per the Silicon Labs default plan for the DUT type mounted on the EVB.
Figure 9.7. Writing Design Status
5. After CBPro writes the default plan to the EVB, select "Open EVB GUI".
Figure 9.8. Open EVB GUI
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Using Si5372 EVB
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6. The EVB GUI opens. All power supplies are set to the values defined in the device’s default CBPro project file created by Silicon
Labs, as shown in the figure below.
Figure 9.9. EVB GUI Window
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Using Si5372 EVB
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9.4.1 Verify Free-run Mode Operation
Assuming no external clocks have been connected to the INPUT CLOCK differential SMA connectors (labeled “INx/INxB”) located
around the perimeter of the EVB, the DUT should now be operating in free-run mode, as the DUT will be locked to the crystal in this
case.
You can run a quick check to determine if the device is powered up and generating output clocks (and consuming power) by clicking on
the "Read All" button (bottom right-hand corner of Figure 9.9 EVB GUI Window on page 15) and then reviewing the voltage, current,
and power readings for each VDDx supply.
Note: Shutting the VDD and VDDA power supplies “Off” and then “On” will power-down and reset the DUT. Every time you do this, to
reload the Silicon Labs-created default plan into the DUT’s register space, you must go back to the Wizard’s main menu and select
"Write Design to EVB".
Figure 9.10. Write Design to EVB
Failure to do the step above will cause the device to read in a pre-programmed plan from its non-volatile memory (NVM). However, the
plan loaded from the NVM may not be the latest plan recommended by Silicon Labs for evaluation.
At this point, you should verify the presence and frequencies of the output clocks (running in free-run mode from the crystal) using ap-
propriate external instrumentation connected to the output clock SMA connectors. To verify the output clocks are toggling at the correct
frequency and signal format, click on "View Design Report" as highlighted in the figure below.
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Using Si5372 EVB
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Figure 9.11. View Design Report
Your configuration’s design report opens in a new window, as shown in the figure below. Compare the observed output clocks to the
frequencies and formats noted in your default project’s Design Report.
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Using Si5372 EVB
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Figure 9.12. Design Report Window
9.4.2 Verify Locked Mode Operation
Assuming you connect the correct input clocks to the EVB (as noted in the Design Report shown above), the DUT on your EVB will be
running in “locked” mode.
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Using Si5372 EVB
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9.5 Workflow Scenario #2: Modifying the Default Silicon Labs Created Device Configuration
1. To modify the “default” configuration using the CBPro Wizard, select "Edit Configuration with Wizard".
Figure 9.13. Edit Configuration with Wizard
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Using Si5372 EVB
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2. You will now be taken to the Wizard’s step-by-step menus to allow you to change any of the default plan’s operating configurations.
Figure 9.14. Design Wizard
Note: You can click on the icon on the lower left hand of the menu to confirm that your frequency plan is valid. After making your
desired changes, you can click on "Write to EVB" to update the DUT to reconfigure your device in real-time. The Design Write
status window opens each time you make a change.
Figure 9.15. Writing Design Status
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