Silicon Laboratories CP2120 User manual

Rev. 0.1 9/06 Copyright © 2006 by Silicon Laboratories CP2120-EK
CP2120-EK
CP2120 EVALUATION KIT USER’SGUIDE
1. Kit Contents
The CP2120 Evaluation Kit contains a CP2120 evaluation board and a power supply. The following supporting
documents can be downloaded from www.silabs.com:
CP2120 Data Sheet
AN311: CP2120 Porting Guide
2. CP2120 Hardware Interface
The evaluation board is connected to a SPI master and to SMBus devices as shown in Figure 1.
1. Connect the SPI Master’s SPI bus lines to the CP2120. If The CP2120 is the only SPI slave device on the
SPI bus, then the CS pin can be tied low.
2. Connect the CP2120’s INT pin to a port pin of the SPI Master.
3. Connect the CP2120 to SMBus devices through the SMBus lines.
Please refer to "4. Evaluation Board" on page 2 for more information about these steps.
Figure 1. System Connections
3. CP2120 Operation
Once connected as shown in Figure 1, the SPI Master issues commands to the CP2120 across the SPI bus. The
CP2120 responds to commands by initiating an SMBus transfer with SMBus slave devices, reading from or writing
to internal registers, or interfacing with general purpose input/output (I/O) port pins. When an SMBus transaction
completes, the CP2120 pulls the INT pin low, which signals the SPI Master that the command has been processed.
SPI Master CP2120
SMBus
Device
SMBus
Device
SMBus
Device
SCK
CS
MISO
MOSI
INT
SPI Bus
SDA
SCL
SMBus

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4. Evaluation Board
The CP2120 evaluation board comes with a CP2120 device pre-installed for system evaluation and development.
Numerous I/O connections are provided to facilitate prototyping using the evaluation board. Refer to Figure 2 for
the locations of the various I/O connectors.
J1 Power Connector
J2 SPI Master Interface
J3 SMBus Interface
J4 MISO-MOSI Connector
J6 SMBus SDA Pullup Connector
J7 SMBus SCL Pullup Connector
J9 LED Connector
J10 General Purpose I/O Interface
Figure 2. CP2120 Evaluation Board
D7 D0D1D2D3D4D5D6
POWER
J1
J9
J10
J3
J2
J7
J6
SILICON LABORATORIES
SA-TB51PCB
J4

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4.1. J2—SPI Master Interface
Connector J2 provides the SPI Master access to the CP2120 SPI, control, and reset lines. Table 1 shows the
pinout of the J2 header.
4.2. J3—SMBus Interface
Connector J3 provides the CP2120 access to the SMBus. Table 2 shows the pinout of the J3 header.
Note: All pins labeled SCL are tied together, and all pins labeled SDA are tied together. Multiple connections to SCL and SDA
signals are provided to allow multiple devices to connect to the evaluation board.
Table 1. Pinout for J2
Pin 1 SPI Bus—SCLK
Pin 2 SPI Bus—MISO
Pin 3 SPI Bus—MOSI
Pin 4 SPI Bus—CS
Pin 5 INT
Pin 6 Not Used
Pin 7 RST
Pin 8 GND
Pin 9 Not Used
Pin 10 Not Used
Table 2. Pinout for J3
Pin 1 SMBus—SCL
Pin 2 SMBus—SDA
Pin 3 SMBus—SCL
Pin 4 SMBus—SDA
Pin 5 SMBus—SCL
Pin 6 SMBus—SDA
Pin 7 SMBus—SCL
Pin 8 SMBus—SDA
Pin 9 GND
Pin 10 GND

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4.3. J4—SPI MISO/MOSI Connector
Some SPI master systems tie together the MISO and MOSI SPI data lines. The CP2120 evaluation board allows
developers to connect these two signals through a resistor by placing a header on J4.
Note: When operating the SPI bus with a header on J4, only drive the MOSI pin whenever data is being transmitted to the
CP2120. When the SPI bus is idle, or when the CP2120 is transmitting data, the SPI master must set its MOSI pin into
an open-drain state to avoid port pin contention.
4.4. J6 and J7—SMBus Pullup Connectors
Connectors J6 and J7 give developers the option of adding pullup resistors to the SMBus’s SDA and SCL lines.
Removing shorting blocks from these headers disconnects the pullups from the SMBus lines.
Note: The SMBus lines need pullups to VDD in order to function properly. If the headers are removed from J6 and J7, remem-
ber to add pullups to VDD elsewhere on the SMBus.
4.5. J9—LED Connector
Connector J9 allows the CP2120’s General Purpose I/O pins to be connected to the array of LEDs on the
evaluation board. Once a header has been placed connecting a pin on the side closest to the CP2120 to its
corresponding pin on the side of the jumper closest to the LEDs. To use one of the LEDs, place a shorting block on
the J9 pin closest to the LED, connecting the corresponding J9 pin on the side of the connector closer to the
CP2120. See Figure 3 for an example of this connection. Writing a 0 to the connected general purpose I/O pin will
turn on the LED, and writing a 1 to that pin will turn off the LED.
Figure 3. Controlling the LEDs
Shorting Block placed on
GPIO1, with GPIO1
configured to be Digital
Output and set to ‘0’
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6
GPIO7
CP2120
To Control an LED using the CP2120:
Add Shorting Block to LED’s
corresponding port pin
Configure port pin to Digital Output
To turn on LED: Set port pin to ‘0’
To turn off LED: Set port pin to ‘1’
J9

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4.6. J10—General Purpose I/O Interface
Connector J10 enables off-board access to the CP2120’s eight general purpose I/O pins, as well as the Edge-
Triggered Interrupt Source pin. Table 3 shows the pinout for this header.
Table 3. Pinout for J10
Pin 1 GPIO Pin 0
Pin 2 GPIO Pin 1
Pin 3 GPIO Pin 2
Pin 4 GPIO Pin 3
Pin 5 GPIO Pin 4
Pin 6 GPIO Pin 5
Pin 7 GPIO Pin 6
Pin 8 GPIO Pin 7
Pin 9 Edge Triggered Interrupt Source
Pin 10 GND

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5. Schematic

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NOTES:

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