Silicon Laboratories EFR32 G23 Series User manual

EFR32xG23 Wireless SoC
Reference Manual
The EFR32xG23 Wireless SoCs include the EFR32FG23 and EFR32ZG23 Wireless
SoC device families. The EFR32xG23 SoC is an ideal solution for sub-GHz “Internet of
Things” for smart home, security, lighting, building automation, and metering. The high-
performance sub-GHz radio provides long range and is not susceptible to 2.4 GHz inter-
ference from technologies like Wi-Fi.
The single die, multi-core solution, provides industry leading security, low power con-
sumption with fast wakeup times, and an integrated power amplifier, to enable the next
level of secure connectivity for IoT devices.
KEY FEATURES
• 32-bit ARM® Cortex M33 core with 78
MHz maximum operating frequency
• Up to 512 kB of flash and 64 kB of RAM
• Energy-efficient radio core with low active
and sleep currents
• Integrated PA with up to 20 dBm transmit
power
• Robust peripheral set and up to 31 GPIO
Timers and Triggers
32-bit bus
Peripheral Reflex System
Serial
Interfaces
I/O Ports Analog I/F
Lowest power mode with peripheral operational:
USART
EUSART
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
IADC
EM4—Shutoff
Energy Management
Brown-Out
Detector
Voltage
Regulator
Power-On
Reset
SecurityClock Management
HF Crystal
Oscillator
LF Crystal
Oscillator
LF
RC Oscillator
HF
RC Oscillator
Ultra LF RC
Oscillator
Core / Memory
ARM CortexTM M33 processor
with DSP extensions,
FPU and TrustZone
ETM Debug Interface RAM Memory LDMA
Controller
Flash Program Memory
System Real Time
Counter
Timer/Counter
Low Energy Timer Watchdog Timer
Protocol Timer
EM3—StopEM2—Deep SleepEM1—SleepEM0—Active
Fast Startup
RC Oscillator
Back-Up Real
Time Counter
I2C
EUSART
DC-DC
Converter
VDAC
Radio Subsystem
RX/TX Frontend with
Integrated +14 or 20 dBm PA
Frequency Synthesizer
ARM CortexTM
M0+ Radio
Controller
CRC
BUFC RAM
FRC
DEMOD
AGC
IFADC
MOD
Secure Debug
Authentication
Crypto Acceleration
Secure Engine
True Random
Number Generator
DPA
Countermeasures
Temperature
Sensor
ACMP
LCD
LESENSE Pulse Counter
Keypad Scanner
silabs.com | Building a more connected world. Copyright © 2022 by Silicon Laboratories Rev. 1.0

Table of Contents
1. About This Document ...........................29
1.1 Introduction ...............................29
1.2 Conventions ...............................30
1.3 Related Documentation ...........................31
2. System Overview .............................32
2.1 Introduction ...............................33
2.2 Block Diagrams..............................34
2.3 MCU Features overview ...........................35
3. System Processor ............................37
3.1 Introduction ...............................37
3.2 Features ................................38
3.3 Functional Description ...........................38
3.3.1 Interrupt Operation ...........................39
3.3.2 TrustZone ..............................39
3.3.3 Interrupt Request Lines (IRQ) .......................40
4. Memory and Bus System ..........................43
4.1 Introduction ...............................43
4.2 Functional Description ...........................44
4.2.1 Bus Matrix ..............................45
4.2.2 Flash ................................46
4.2.3 SRAM ...............................46
4.2.4 Peripherals ..............................46
5. Radio Transceiver ............................53
5.1 Introduction ...............................54
5.1.1 RF Frequency Synthesizer ........................54
5.1.2 Modulation Modes ...........................55
5.1.3 Transmit Mode ............................55
5.1.4 Receive Mode.............................55
5.1.5 Data Buffering.............................55
5.1.6 Unbuffered Data Transfer .........................55
5.1.7 Frame Format Support ..........................56
5.1.8 Hardware CRC Support .........................56
5.1.9 Convolutional Encoding / Decoding .....................56
5.1.10 Binary Block Encoding / Decoding .....................56
5.1.11 Data Encryption and Authentication .....................57
5.1.12 RF Test Modes ............................57
6. MSC - Memory System Controller ......................58
6.1 Introduction ...............................58
6.2 Features ................................59
silabs.com | Building a more connected world. Rev. 1.0 | 2

6.3 Functional Description ...........................59
6.3.1 Ram Configuration ...........................59
6.3.2 Instruction Cache............................60
6.3.3 Device Information (DI) Page .......................60
6.3.4 User Data (UD) Page Description ......................60
6.3.5 Bootloader ..............................60
6.3.6 Post-reset Behavior ...........................60
6.3.7 Flash Startup .............................60
6.3.8 Flash EM0 / EM1 Power Down .......................60
6.3.9 Wait-states ..............................60
6.3.10 Cortex-M33 If-Then Block Folding......................61
6.3.11 Line Buffering (Prefetch) .........................61
6.3.12 Erase and Write Operations........................62
6.4 DEVINFO - Device Info Page .........................63
6.4.1 DEVINFO Register Map .........................64
6.4.2 DEVINFO Register Description .......................65
6.5 ICACHE - Instruction Cache .........................94
6.5.1 Cache Operation ............................95
6.5.2 Performance Measurement ........................95
6.5.3 ICACHE Register Map ..........................96
6.5.4 ICACHE Register Description .......................97
6.6 SYSCFG - System Configuration .......................103
6.6.1 Ram Retention ...........................103
6.6.2 ECC ...............................104
6.6.3 Software Interrupts ..........................104
6.6.4 Bus faults .............................104
6.6.5 SYSCFG Register Map.........................105
6.6.6 SYSCFG Register Description ......................108
6.6.7 MPAHBRAM Register Map .......................125
6.6.8 MPAHBRAM Register Description .....................126
6.7 MSC Register Map ...........................131
6.8 MSC Register Description .........................133
6.8.1 MSC_IPVERSION - IP Version ID .....................133
6.8.2 MSC_READCTRL - Read Control Register ..................133
6.8.3 MSC_RDATACTRL - Read Data Control Register................134
6.8.4 MSC_WRITECTRL - Write Control Register..................135
6.8.5 MSC_WRITECMD - Write Command Register .................136
6.8.6 MSC_ADDRB - Page Erase/Write Address Buffer ................137
6.8.7 MSC_WDATA - Write Data Register ....................137
6.8.8 MSC_STATUS - Status Register .....................138
6.8.9 MSC_IF - Interrupt Flag Register .....................139
6.8.10 MSC_IEN - Interrupt Enable Register ...................140
6.8.11 MSC_USERDATASIZE - User Data Region Size Register ............141
6.8.12 MSC_CMD - Command Register .....................141
6.8.13 MSC_LOCK - Configuration Lock Register ..................142
6.8.14 MSC_MISCLOCKWORD - Mass Erase and User Data Page Lock Word .......142
6.8.15 MSC_PWRCTRL - Power Control Register .................143
silabs.com | Building a more connected world. Rev. 1.0 | 3

6.8.16 MSC_PAGELOCK0 - Main Space Page 0-31 Lock Word .............144
6.8.17 MSC_PAGELOCK1 - Main Space Page 32-63 Lock Word ............144
7. DBG - Debug Interface ...........................145
7.1 Introduction ..............................145
7.2 Features ...............................145
7.3 Functional Description ..........................146
7.3.1 Debug Pins.............................146
7.3.2 Embedded Trace Macrocell V3.5 (ETM) ...................146
7.3.3 Debug and EM2/EM3 .........................146
8. CMU - Clock Management Unit ........................147
8.1 Introduction ..............................147
8.2 Features ...............................147
8.3 Functional Description ..........................148
8.3.1 System Clocks ...........................151
8.3.2 Switching Clock Source ........................155
8.3.3 RC Oscillator Calibration ........................157
8.3.4 Energy Modes ...........................160
8.3.5 Clock Output ............................160
8.3.6 Clock Input from a Pin .........................161
8.3.7 Clock Output to PRS .........................161
8.3.8 Interrupts .............................161
8.3.9 Protection .............................161
8.4 CMU Register Map ...........................162
8.5 CMU Register Description .........................165
8.5.1 CMU_IPVERSION - IP Version ID .....................165
8.5.2 CMU_STATUS - Status Register .....................166
8.5.3 CMU_LOCK - Configuration Lock Register ..................167
8.5.4 CMU_WDOGLOCK - WDOG Configuration Lock Register .............167
8.5.5 CMU_IF - Interrupt Flag Register .....................168
8.5.6 CMU_IEN - Interrupt Enable Register ....................168
8.5.7 CMU_CALCMD - Calibration Command Register ................169
8.5.8 CMU_CALCTRL - Calibration Control Register .................170
8.5.9 CMU_CALCNT - Calibration Result Counter Register ..............171
8.5.10 CMU_CLKEN0 - Clock Enable Register 0 ..................172
8.5.11 CMU_CLKEN1 - Clock Enable Register 1 ..................174
8.5.12 CMU_SYSCLKCTRL - System Clock Control .................176
8.5.13 CMU_TRACECLKCTRL - Debug Trace Clock Control ..............177
8.5.14 CMU_EXPORTCLKCTRL - Export Clock Control ...............178
8.5.15 CMU_DPLLREFCLKCTRL - Digital PLL Reference Clock Control ..........180
8.5.16 CMU_EM01GRPACLKCTRL - EM01 Peripheral Group a Clock Control ........181
8.5.17 CMU_EM01GRPCCLKCTRL - EM01 Peripheral Group C Clock Control ........182
8.5.18 CMU_EM23GRPACLKCTRL - EM23 Peripheral Group a Clock Control ........183
8.5.19 CMU_EM4GRPACLKCTRL - EM4 Peripheral Group a Clock Control .........183
8.5.20 CMU_IADCCLKCTRL - IADC Clock Control .................184
8.5.21 CMU_WDOG0CLKCTRL - Watchdog0 Clock Control ..............184
silabs.com | Building a more connected world. Rev. 1.0 | 4

8.5.22 CMU_WDOG1CLKCTRL - Watchdog1 Clock Control ..............185
8.5.23 CMU_EUSART0CLKCTRL - EUSART0 Clock Control ..............186
8.5.24 CMU_SYSRTC0CLKCTRL - System RTC0 Clock Control ............187
8.5.25 CMU_LCDCLKCTRL - LCD Clock Control ..................187
8.5.26 CMU_VDAC0CLKCTRL - VDAC0 Clock Control ................188
8.5.27 CMU_PCNT0CLKCTRL - Pulse Counter 0 Clock Control .............189
8.5.28 CMU_RADIOCLKCTRL - Radio Clock Control ................189
8.5.29 CMU_LESENSEHFCLKCTRL - LESENSE HF Clock Control ...........190
9. Oscillators ...............................191
9.1 Introduction ..............................191
9.2 HFXO - High Frequency Crystal Oscillator ....................191
9.2.1 Introduction ............................191
9.2.2 Features .............................192
9.2.3 Functional Description .........................192
9.2.4 HFXO Register Map ..........................196
9.2.5 HFXO Register Description .......................197
9.3 HFRCO - High-Frequency RC Oscillator ....................216
9.3.1 Introduction ............................216
9.3.2 Features .............................216
9.3.3 Functional Description .........................216
9.3.4 HFRCO Register Map .........................221
9.3.5 HFRCO Register Description .......................222
9.4 DPLL - Digital Phased Locked Loop ......................226
9.4.1 Introduction ............................226
9.4.2 Features .............................226
9.4.3 Functional Description .........................226
9.4.4 DPLL Register Map ..........................228
9.4.5 DPLL Register Description .......................229
9.5 LFXO - Low-Frequency Crystal Oscillator ....................234
9.5.1 Introduction ............................234
9.5.2 Features .............................234
9.5.3 Functional Description .........................234
9.5.4 LFXO Register Map ..........................236
9.5.5 LFXO Register Description .......................237
9.6 LFRCO - Low-Frequency RC Oscillator ....................244
9.6.1 Introduction ............................244
9.6.2 Features .............................244
9.6.3 Functional Description .........................244
9.6.4 LFRCO Register Map .........................246
9.6.5 LFRCO Register Description .......................247
9.7 FSRCO - Fast Start RCO .........................250
9.7.1 Introduction ............................250
9.7.2 Features .............................251
9.7.3 Functional Description .........................251
9.7.4 FSRCO Register Map .........................251
9.7.5 FSRCO Register Description .......................251
silabs.com | Building a more connected world. Rev. 1.0 | 5

9.8 ULFRCO - Ultra Low Frequency RC Oscillator ..................251
9.8.1 Introduction ............................251
9.8.2 Features .............................251
9.8.3 Functional Description .........................252
10. SMU - Security Management Unit ......................253
10.1 Introduction .............................253
10.2 Features ..............................253
10.3 Functional Description ..........................254
10.3.1 Bus Level Security ..........................254
10.3.2 Privileged Access Control .......................255
10.3.3 Secure Access Control ........................255
10.3.4 ARM TrustZone ...........................256
10.3.5 Configuring Managers ........................256
10.3.6 Configuring Peripherals ........................256
10.3.7 Configuring Memory .........................257
10.3.8 Cortex-M33 Integration ........................257
10.3.9 Exception Handling .........................258
10.3.10 SMU Lock ............................258
10.4 SMU Register Map ...........................259
10.5 SMU Register Description .........................261
10.5.1 SMU_IPVERSION - IP Version .....................261
10.5.2 SMU_STATUS - Status Register .....................262
10.5.3 SMU_LOCK - Lock Register ......................262
10.5.4 SMU_IF - Interrupt Flag Register .....................263
10.5.5 SMU_IEN - Interrupt Enable Register ...................264
10.5.6 SMU_M33CTRL - M33 Control Settings ..................265
10.5.7 SMU_PPUPATD0 - Privileged Access ...................266
10.5.8 SMU_PPUPATD1 - Privileged Access ...................268
10.5.9 SMU_PPUSATD0 - Secure Access ....................270
10.5.10 SMU_PPUSATD1 - Secure Access ....................272
10.5.11 SMU_PPUFS - Fault Status ......................274
10.5.12 SMU_BMPUPATD0 - Privileged Attribute ..................275
10.5.13 SMU_BMPUSATD0 - Secure Attribute...................276
10.5.14 SMU_BMPUFS - Fault Status .....................277
10.5.15 SMU_BMPUFSADDR - Fault Status Address ................277
10.5.16 SMU_ESAURTYPES0 - Region Types 0 ..................278
10.5.17 SMU_ESAURTYPES1 - Region Types 1 ..................278
10.5.18 SMU_ESAUMRB01 - Movable Region Boundary ...............279
10.5.19 SMU_ESAUMRB12 - Movable Region Boundary ...............279
10.5.20 SMU_ESAUMRB45 - Movable Region Boundary ...............280
10.5.21 SMU_ESAUMRB56 - Movable Region Boundary ...............280
11. SE - Secure Engine Subsystem .......................281
11.1 Introduction .............................281
11.2 Security Features ...........................281
11.2.1 Security Features Overview .......................281
silabs.com | Building a more connected world. Rev. 1.0 | 6

11.2.2 Secure Boot with Root of Trust and Secure Loader (RTSL) ............282
11.2.3 Secure Debug ...........................282
11.2.4 Cryptographic Accelerator .......................282
11.2.5 True Random Number Generation ....................283
11.3 SE Mailbox .............................283
11.3.1 Sending Commands .........................283
11.3.2 Receiving Responses ........................283
11.3.3 MAILBOX Register Map ........................284
11.3.4 MAILBOX Register Description .....................284
12. EMU - Energy Management Unit ......................287
12.1 Introduction..............................287
12.2 Features ..............................288
12.3 Functional Description ..........................289
12.3.1 Energy Modes ...........................290
12.3.2 Entering Low Energy Modes ......................294
12.3.3 Exiting a Low Energy Mode ......................295
12.3.4 Power Domains ...........................296
12.3.5 Voltage Scaling ...........................296
12.3.6 EM0 / EM1 Peripheral Register Retention ..................297
12.3.7 Power Configurations .........................297
12.3.8 Buck DC-DC Interface ........................301
12.3.9 EFP01 Communication ........................304
12.3.10 Brown Out Detector (BOD) ......................305
12.3.11 Reset Management Unit .......................306
12.3.12 Temperature Sensor .........................308
12.3.13 Register Resets ..........................309
12.3.14 Register Locks ...........................309
12.4 EMU Register Map ...........................310
12.5 EMU Register Description .........................312
12.5.1 EMU_DECBOD - DECOUPLE LVBOD Control Register .............312
12.5.2 EMU_BOD3SENSE - BOD3SENSE Control Register ..............313
12.5.3 EMU_VREGVDDCMPCTRL - DC-DC VREGVDD Comparator Control Register .....313
12.5.4 EMU_PD1PARETCTRL - PD1 Partial Retention Control .............314
12.5.5 EMU_IPVERSION - IP Version .....................314
12.5.6 EMU_LOCK - EMU Configuration Lock Register ................315
12.5.7 EMU_IF - Interrupt Flags ........................316
12.5.8 EMU_IEN - Interrupt Enables ......................317
12.5.9 EMU_EM4CTRL - EM4 Control .....................318
12.5.10 EMU_CMD - EMU Command Register ..................319
12.5.11 EMU_CTRL - EMU Control Register ...................320
12.5.12 EMU_TEMPLIMITS - EMU Temperature Thresholds ..............321
12.5.13 EMU_STATUS - EMU Status Register...................322
12.5.14 EMU_TEMP - Temperature ......................323
12.5.15 EMU_RSTCTRL - Reset Management Control Register .............324
12.5.16 EMU_RSTCAUSE - Reset Cause ....................326
12.5.17 EMU_DGIF - Interrupt Flags Debug ...................327
silabs.com | Building a more connected world. Rev. 1.0 | 7

12.5.18 EMU_DGIEN - Interrupt Enables Debug ..................328
12.5.19 EMU_EFPIF - EFP Interrupt Register ...................328
12.5.20 EMU_EFPIEN - EFP Interrupt Enable Register ................329
12.6 DCDC Register Map ..........................330
12.7 DCDC Register Description ........................331
12.7.1 DCDC_IPVERSION - IPVERSION ....................331
12.7.2 DCDC_CTRL - Control ........................332
12.7.3 DCDC_EM01CTRL0 - EM01 Control....................333
12.7.4 DCDC_EM23CTRL0 - EM23 Control....................334
12.7.5 DCDC_PFMXCTRL - PFMX Control Register .................335
12.7.6 DCDC_IF - Interrupt Flags .......................336
12.7.7 DCDC_IEN - Interrupt Enable ......................337
12.7.8 DCDC_STATUS - Status Register ....................338
12.7.9 DCDC_SYNCBUSY - Syncbusy Status Register ................339
12.7.10 DCDC_LOCK - Lock Register .....................340
12.7.11 DCDC_LOCKSTATUS - Lock Status Register ................340
13. PRS - Peripheral Reflex System .......................341
13.1 Introduction..............................341
13.2 Features ..............................341
13.3 Functional Description ..........................342
13.3.1 Asynchronous Channel Functions.....................342
13.3.2 Configurable Logic ..........................343
13.3.3 Producers .............................344
13.3.4 Consumers ............................351
13.4 PRS Register Map ...........................352
13.5 PRS Register Description .........................368
13.5.1 PRS_IPVERSION - PRS IPVERSION ...................368
13.5.2 PRS_ASYNC_SWPULSE - Software Pulse Register ..............369
13.5.3 PRS_ASYNC_SWLEVEL - Software Level Register ..............370
13.5.4 PRS_ASYNC_PEEK - Async Channel Values ................371
13.5.5 PRS_SYNC_PEEK - Sync Channel Values .................372
13.5.6 PRS_ASYNC_CHx_CTRL - Async Channel Control Register ...........373
13.5.7 PRS_SYNC_CHx_CTRL - Sync Channel Control Register ............374
13.5.8 PRS_CONSUMER_CMU_CALDN - CALDN Consumer Register ..........375
13.5.9 PRS_CONSUMER_CMU_CALUP - CALUP Consumer Register ..........375
13.5.10 PRS_CONSUMER_EUSART0_CLK - CLK Consumer Register ..........376
13.5.11 PRS_CONSUMER_EUSART0_RX - RX Consumer Register ...........376
13.5.12 PRS_CONSUMER_EUSART0_TRIGGER - TRIGGER Consumer Register ......377
13.5.13 PRS_CONSUMER_EUSART1_CLK - CLK Consumer Register ..........377
13.5.14 PRS_CONSUMER_EUSART1_RX - RX Consumer Register ...........378
13.5.15 PRS_CONSUMER_EUSART1_TRIGGER - TRIGGER Consumer Register ......378
13.5.16 PRS_CONSUMER_EUSART2_CLK - CLK Consumer Register ..........379
13.5.17 PRS_CONSUMER_EUSART2_RX - RX Consumer Register ...........379
13.5.18 PRS_CONSUMER_EUSART2_TRIGGER - TRIGGER Consumer Register ......380
13.5.19 PRS_CONSUMER_IADC0_SCANTRIGGER - SCAN Consumer Register.......380
13.5.20 PRS_CONSUMER_IADC0_SINGLETRIGGER - SINGLE Consumer Register .....381
silabs.com | Building a more connected world. Rev. 1.0 | 8

13.5.21 PRS_CONSUMER_LDMAXBAR_DMAREQ0 - DMAREQ0 Consumer Register .....381
13.5.22 PRS_CONSUMER_LDMAXBAR_DMAREQ1 - DMAREQ1 Consumer Register .....382
13.5.23 PRS_CONSUMER_LESENSE_START - START Consumer Register ........382
13.5.24 PRS_CONSUMER_LETIMER0_CLEAR - CLEAR Consumer Register ........383
13.5.25 PRS_CONSUMER_LETIMER0_START - START Consumer Register ........383
13.5.26 PRS_CONSUMER_LETIMER0_STOP - STOP Consumer Register .........384
13.5.27 PRS_CONSUMER_MODEM_DIN - MODEM DIN Consumer Register ........384
13.5.28 PRS_CONSUMER_PCNT0_S0IN - S0IN Consumer Register ...........385
13.5.29 PRS_CONSUMER_PCNT0_S1IN - S1IN Consumer Register ...........385
13.5.30 PRS_CONSUMER_RAC_CLR - CLR Consumer Register ............386
13.5.31 PRS_CONSUMER_RAC_CTIIN0 - CTI Consumer Register ...........386
13.5.32 PRS_CONSUMER_RAC_CTIIN1 - CTI Consumer Register ...........387
13.5.33 PRS_CONSUMER_RAC_CTIIN2 - CTI Consumer Register ...........387
13.5.34 PRS_CONSUMER_RAC_CTIIN3 - CTI Consumer Register ...........388
13.5.35 PRS_CONSUMER_RAC_FORCETX - FORCETX Consumer Register ........388
13.5.36 PRS_CONSUMER_RAC_RXDIS - RXDIS Consumer Register ..........389
13.5.37 PRS_CONSUMER_RAC_RXEN - RXEN Consumer Register ...........389
13.5.38 PRS_CONSUMER_RAC_TXEN - TXEN Consumer Register ...........390
13.5.39 PRS_CONSUMER_SETAMPER_TAMPERSRC25 - TAMPERSRC25 Consumer Register . 390
13.5.40 PRS_CONSUMER_SETAMPER_TAMPERSRC26 - TAMPERSRC26 Consumer Register . 391
13.5.41 PRS_CONSUMER_SETAMPER_TAMPERSRC27 - TAMPERSRC27 Consumer Register . 391
13.5.42 PRS_CONSUMER_SETAMPER_TAMPERSRC28 - TAMPERSRC28 Consumer Register . 392
13.5.43 PRS_CONSUMER_SETAMPER_TAMPERSRC29 - TAMPERSRC29 Consumer Register . 392
13.5.44 PRS_CONSUMER_SETAMPER_TAMPERSRC30 - TAMPERSRC30 Consumer Register . 393
13.5.45 PRS_CONSUMER_SETAMPER_TAMPERSRC31 - TAMPERSRC31 Consumer Register . 393
13.5.46 PRS_CONSUMER_SYSRTC0_IN0 - IN0 Consumer Register ...........394
13.5.47 PRS_CONSUMER_SYSRTC0_IN1 - IN1 Consumer Register ...........394
13.5.48 PRS_CONSUMER_HFXO0_OSCREQ - OSCREQ Consumer Register .......395
13.5.49 PRS_CONSUMER_HFXO0_TIMEOUT - TIMEOUT Consumer Register .......395
13.5.50 PRS_CONSUMER_CORE_CTIIN0 - CTI0 Consumer Selection ..........396
13.5.51 PRS_CONSUMER_CORE_CTIIN1 - CTI1 Consumer Selection ..........396
13.5.52 PRS_CONSUMER_CORE_CTIIN2 - CTI2 Consumer Selection ..........397
13.5.53 PRS_CONSUMER_CORE_CTIIN3 - CTI3 Consumer Selection ..........397
13.5.54 PRS_CONSUMER_CORE_M33RXEV - M33 Consumer Selection .........398
13.5.55 PRS_CONSUMER_TIMER0_CC0 - CC0 Consumer Register ...........398
13.5.56 PRS_CONSUMER_TIMER0_CC1 - CC1 Consumer Register ...........399
13.5.57 PRS_CONSUMER_TIMER0_CC2 - CC2 Consumer Register ...........399
13.5.58 PRS_CONSUMER_TIMER0_DTI - DTI Consumer Register ...........400
13.5.59 PRS_CONSUMER_TIMER0_DTIFS1 - DTI Consumer Register ..........400
13.5.60 PRS_CONSUMER_TIMER0_DTIFS2 - DTI Consumer Register ..........401
13.5.61 PRS_CONSUMER_TIMER1_CC0 - CC0 Consumer Register ...........401
13.5.62 PRS_CONSUMER_TIMER1_CC1 - CC1 Consumer Register ...........402
13.5.63 PRS_CONSUMER_TIMER1_CC2 - CC2 Consumer Register ...........402
13.5.64 PRS_CONSUMER_TIMER1_DTI - DTI Consumer Register ...........403
13.5.65 PRS_CONSUMER_TIMER1_DTIFS1 - DTI Consumer Register ..........403
13.5.66 PRS_CONSUMER_TIMER1_DTIFS2 - DTI Consumer Register ..........404
13.5.67 PRS_CONSUMER_TIMER2_CC0 - CC0 Consumer Register ...........404
13.5.68 PRS_CONSUMER_TIMER2_CC1 - CC1 Consumer Register ...........405
silabs.com | Building a more connected world. Rev. 1.0 | 9

13.5.69 PRS_CONSUMER_TIMER2_CC2 - CC2 Consumer Register ...........405
13.5.70 PRS_CONSUMER_TIMER2_DTI - DTI Consumer Register ...........406
13.5.71 PRS_CONSUMER_TIMER2_DTIFS1 - DTI Consumer Register ..........406
13.5.72 PRS_CONSUMER_TIMER2_DTIFS2 - DTI Consumer Register ..........407
13.5.73 PRS_CONSUMER_TIMER3_CC0 - CC0 Consumer Register ...........407
13.5.74 PRS_CONSUMER_TIMER3_CC1 - CC1 Consumer Register ...........408
13.5.75 PRS_CONSUMER_TIMER3_CC2 - CC2 Consumer Register ...........408
13.5.76 PRS_CONSUMER_TIMER3_DTI - DTI Consumer Register ...........409
13.5.77 PRS_CONSUMER_TIMER3_DTIFS1 - DTI Consumer Register ..........409
13.5.78 PRS_CONSUMER_TIMER3_DTIFS2 - DTI Consumer Register ..........410
13.5.79 PRS_CONSUMER_TIMER4_CC0 - CC0 Consumer Register ...........410
13.5.80 PRS_CONSUMER_TIMER4_CC1 - CC1 Consumer Register ...........411
13.5.81 PRS_CONSUMER_TIMER4_CC2 - CC2 Consumer Register ...........411
13.5.82 PRS_CONSUMER_TIMER4_DTI - DTI Consumer Register ...........412
13.5.83 PRS_CONSUMER_TIMER4_DTIFS1 - DTI Consumer Register ..........412
13.5.84 PRS_CONSUMER_TIMER4_DTIFS2 - DTI Consumer Register ..........413
13.5.85 PRS_CONSUMER_USART0_CLK - CLK Consumer Register ...........413
13.5.86 PRS_CONSUMER_USART0_IR - IR Consumer Register ............414
13.5.87 PRS_CONSUMER_USART0_RX - RX Consumer Register ...........414
13.5.88 PRS_CONSUMER_USART0_TRIGGER - TRIGGER Consumer Register.......415
13.5.89 PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 - ASYNCTRIG Consumer Register ...415
13.5.90 PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 - ASYNCTRIG Consumer Register ...416
13.5.91 PRS_CONSUMER_VDAC0_SYNCTRIGCH0 - SYNCTRIG Consumer Register.....416
13.5.92 PRS_CONSUMER_VDAC0_SYNCTRIGCH1 - SYNCTRIG Consumer Register.....417
13.5.93 PRS_CONSUMER_WDOG0_SRC0 - SRC0 Consumer Register ..........417
13.5.94 PRS_CONSUMER_WDOG0_SRC1 - SRC1 Consumer Register ..........418
13.5.95 PRS_CONSUMER_WDOG1_SRC0 - SRC0 Consumer Register ..........418
13.5.96 PRS_CONSUMER_WDOG1_SRC1 - SRC1 Consumer Register ..........419
14. GPCRC - General Purpose Cyclic Redundancy Check ..............420
14.1 Introduction..............................420
14.2 Features ..............................420
14.3 Functional Description ..........................421
14.3.1 Polynomial Specification ........................422
14.3.2 Input and Output Specification ......................422
14.3.3 Initialization ............................422
14.3.4 DMA Usage ............................422
14.3.5 Byte-Level Bit Reversal and Byte Reordering .................423
14.4 GPCRC Register Map ..........................426
14.5 GPCRC Register Description ........................427
14.5.1 GPCRC_IPVERSION - IP Version ID ...................427
14.5.2 GPCRC_EN - CRC Enable .......................428
14.5.3 GPCRC_CTRL - Control Register .....................429
14.5.4 GPCRC_CMD - Command Register ....................430
14.5.5 GPCRC_INIT - CRC Init Value ......................430
14.5.6 GPCRC_POLY - CRC Polynomial Value ..................431
14.5.7 GPCRC_INPUTDATA - Input 32-Bit Data Register ...............431
silabs.com | Building a more connected world. Rev. 1.0 | 10