Silicon Laboratories EFR32 G23 Series User manual

EFR32xG23 Wireless SoC
Reference Manual
The EFR32xG23 Wireless SoCs include the EFR32FG23 and EFR32ZG23 Wireless
SoC device families. The EFR32xG23 SoC is an ideal solution for sub-GHz “Internet of
Things” for smart home, security, lighting, building automation, and metering. The high-
performance sub-GHz radio provides long range and is not susceptible to 2.4 GHz inter-
ference from technologies like Wi-Fi.
The single die, multi-core solution, provides industry leading security, low power con-
sumption with fast wakeup times, and an integrated power amplifier, to enable the next
level of secure connectivity for IoT devices.
KEY FEATURES
• 32-bit ARM® Cortex M33 core with 78
MHz maximum operating frequency
• Up to 512 kB of flash and 64 kB of RAM
• Energy-efficient radio core with low active
and sleep currents
• Integrated PA with up to 20 dBm transmit
power
• Robust peripheral set and up to 31 GPIO
Timers and Triggers
32-bit bus
Peripheral Reflex System
Serial
Interfaces
I/O Ports Analog I/F
Lowest power mode with peripheral operational:
USART
EUSART
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
IADC
EM4—Shutoff
Energy Management
Brown-Out
Detector
Voltage
Regulator
Power-On
Reset
SecurityClock Management
HF Crystal
Oscillator
LF Crystal
Oscillator
LF
RC Oscillator
HF
RC Oscillator
Ultra LF RC
Oscillator
Core / Memory
ARM CortexTM M33 processor
with DSP extensions,
FPU and TrustZone
ETM Debug Interface RAM Memory LDMA
Controller
Flash Program Memory
System Real Time
Counter
Timer/Counter
Low Energy Timer Watchdog Timer
Protocol Timer
EM3—StopEM2—Deep SleepEM1—SleepEM0—Active
Fast Startup
RC Oscillator
Back-Up Real
Time Counter
I2C
EUSART
DC-DC
Converter
VDAC
Radio Subsystem
RX/TX Frontend with
Integrated +14 or 20 dBm PA
Frequency Synthesizer
ARM CortexTM
M0+ Radio
Controller
CRC
BUFC RAM
FRC
DEMOD
AGC
IFADC
MOD
Secure Debug
Authentication
Crypto Acceleration
Secure Engine
True Random
Number Generator
DPA
Countermeasures
Temperature
Sensor
ACMP
LCD
LESENSE Pulse Counter
Keypad Scanner
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Table of Contents
1. About This Document ...........................29
1.1 Introduction ...............................29
1.2 Conventions ...............................30
1.3 Related Documentation ...........................31
2. System Overview .............................32
2.1 Introduction ...............................33
2.2 Block Diagrams..............................34
2.3 MCU Features overview ...........................35
3. System Processor ............................37
3.1 Introduction ...............................37
3.2 Features ................................38
3.3 Functional Description ...........................38
3.3.1 Interrupt Operation ...........................39
3.3.2 TrustZone ..............................39
3.3.3 Interrupt Request Lines (IRQ) .......................40
4. Memory and Bus System ..........................43
4.1 Introduction ...............................43
4.2 Functional Description ...........................44
4.2.1 Bus Matrix ..............................45
4.2.2 Flash ................................46
4.2.3 SRAM ...............................46
4.2.4 Peripherals ..............................46
5. Radio Transceiver ............................53
5.1 Introduction ...............................54
5.1.1 RF Frequency Synthesizer ........................54
5.1.2 Modulation Modes ...........................55
5.1.3 Transmit Mode ............................55
5.1.4 Receive Mode.............................55
5.1.5 Data Buffering.............................55
5.1.6 Unbuffered Data Transfer .........................55
5.1.7 Frame Format Support ..........................56
5.1.8 Hardware CRC Support .........................56
5.1.9 Convolutional Encoding / Decoding .....................56
5.1.10 Binary Block Encoding / Decoding .....................56
5.1.11 Data Encryption and Authentication .....................57
5.1.12 RF Test Modes ............................57
6. MSC - Memory System Controller ......................58
6.1 Introduction ...............................58
6.2 Features ................................59
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6.3 Functional Description ...........................59
6.3.1 Ram Configuration ...........................59
6.3.2 Instruction Cache............................60
6.3.3 Device Information (DI) Page .......................60
6.3.4 User Data (UD) Page Description ......................60
6.3.5 Bootloader ..............................60
6.3.6 Post-reset Behavior ...........................60
6.3.7 Flash Startup .............................60
6.3.8 Flash EM0 / EM1 Power Down .......................60
6.3.9 Wait-states ..............................60
6.3.10 Cortex-M33 If-Then Block Folding......................61
6.3.11 Line Buffering (Prefetch) .........................61
6.3.12 Erase and Write Operations........................62
6.4 DEVINFO - Device Info Page .........................63
6.4.1 DEVINFO Register Map .........................64
6.4.2 DEVINFO Register Description .......................65
6.5 ICACHE - Instruction Cache .........................94
6.5.1 Cache Operation ............................95
6.5.2 Performance Measurement ........................95
6.5.3 ICACHE Register Map ..........................96
6.5.4 ICACHE Register Description .......................97
6.6 SYSCFG - System Configuration .......................103
6.6.1 Ram Retention ...........................103
6.6.2 ECC ...............................104
6.6.3 Software Interrupts ..........................104
6.6.4 Bus faults .............................104
6.6.5 SYSCFG Register Map.........................105
6.6.6 SYSCFG Register Description ......................108
6.6.7 MPAHBRAM Register Map .......................125
6.6.8 MPAHBRAM Register Description .....................126
6.7 MSC Register Map ...........................131
6.8 MSC Register Description .........................133
6.8.1 MSC_IPVERSION - IP Version ID .....................133
6.8.2 MSC_READCTRL - Read Control Register ..................133
6.8.3 MSC_RDATACTRL - Read Data Control Register................134
6.8.4 MSC_WRITECTRL - Write Control Register..................135
6.8.5 MSC_WRITECMD - Write Command Register .................136
6.8.6 MSC_ADDRB - Page Erase/Write Address Buffer ................137
6.8.7 MSC_WDATA - Write Data Register ....................137
6.8.8 MSC_STATUS - Status Register .....................138
6.8.9 MSC_IF - Interrupt Flag Register .....................139
6.8.10 MSC_IEN - Interrupt Enable Register ...................140
6.8.11 MSC_USERDATASIZE - User Data Region Size Register ............141
6.8.12 MSC_CMD - Command Register .....................141
6.8.13 MSC_LOCK - Configuration Lock Register ..................142
6.8.14 MSC_MISCLOCKWORD - Mass Erase and User Data Page Lock Word .......142
6.8.15 MSC_PWRCTRL - Power Control Register .................143
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6.8.16 MSC_PAGELOCK0 - Main Space Page 0-31 Lock Word .............144
6.8.17 MSC_PAGELOCK1 - Main Space Page 32-63 Lock Word ............144
7. DBG - Debug Interface ...........................145
7.1 Introduction ..............................145
7.2 Features ...............................145
7.3 Functional Description ..........................146
7.3.1 Debug Pins.............................146
7.3.2 Embedded Trace Macrocell V3.5 (ETM) ...................146
7.3.3 Debug and EM2/EM3 .........................146
8. CMU - Clock Management Unit ........................147
8.1 Introduction ..............................147
8.2 Features ...............................147
8.3 Functional Description ..........................148
8.3.1 System Clocks ...........................151
8.3.2 Switching Clock Source ........................155
8.3.3 RC Oscillator Calibration ........................157
8.3.4 Energy Modes ...........................160
8.3.5 Clock Output ............................160
8.3.6 Clock Input from a Pin .........................161
8.3.7 Clock Output to PRS .........................161
8.3.8 Interrupts .............................161
8.3.9 Protection .............................161
8.4 CMU Register Map ...........................162
8.5 CMU Register Description .........................165
8.5.1 CMU_IPVERSION - IP Version ID .....................165
8.5.2 CMU_STATUS - Status Register .....................166
8.5.3 CMU_LOCK - Configuration Lock Register ..................167
8.5.4 CMU_WDOGLOCK - WDOG Configuration Lock Register .............167
8.5.5 CMU_IF - Interrupt Flag Register .....................168
8.5.6 CMU_IEN - Interrupt Enable Register ....................168
8.5.7 CMU_CALCMD - Calibration Command Register ................169
8.5.8 CMU_CALCTRL - Calibration Control Register .................170
8.5.9 CMU_CALCNT - Calibration Result Counter Register ..............171
8.5.10 CMU_CLKEN0 - Clock Enable Register 0 ..................172
8.5.11 CMU_CLKEN1 - Clock Enable Register 1 ..................174
8.5.12 CMU_SYSCLKCTRL - System Clock Control .................176
8.5.13 CMU_TRACECLKCTRL - Debug Trace Clock Control ..............177
8.5.14 CMU_EXPORTCLKCTRL - Export Clock Control ...............178
8.5.15 CMU_DPLLREFCLKCTRL - Digital PLL Reference Clock Control ..........180
8.5.16 CMU_EM01GRPACLKCTRL - EM01 Peripheral Group a Clock Control ........181
8.5.17 CMU_EM01GRPCCLKCTRL - EM01 Peripheral Group C Clock Control ........182
8.5.18 CMU_EM23GRPACLKCTRL - EM23 Peripheral Group a Clock Control ........183
8.5.19 CMU_EM4GRPACLKCTRL - EM4 Peripheral Group a Clock Control .........183
8.5.20 CMU_IADCCLKCTRL - IADC Clock Control .................184
8.5.21 CMU_WDOG0CLKCTRL - Watchdog0 Clock Control ..............184
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8.5.22 CMU_WDOG1CLKCTRL - Watchdog1 Clock Control ..............185
8.5.23 CMU_EUSART0CLKCTRL - EUSART0 Clock Control ..............186
8.5.24 CMU_SYSRTC0CLKCTRL - System RTC0 Clock Control ............187
8.5.25 CMU_LCDCLKCTRL - LCD Clock Control ..................187
8.5.26 CMU_VDAC0CLKCTRL - VDAC0 Clock Control ................188
8.5.27 CMU_PCNT0CLKCTRL - Pulse Counter 0 Clock Control .............189
8.5.28 CMU_RADIOCLKCTRL - Radio Clock Control ................189
8.5.29 CMU_LESENSEHFCLKCTRL - LESENSE HF Clock Control ...........190
9. Oscillators ...............................191
9.1 Introduction ..............................191
9.2 HFXO - High Frequency Crystal Oscillator ....................191
9.2.1 Introduction ............................191
9.2.2 Features .............................192
9.2.3 Functional Description .........................192
9.2.4 HFXO Register Map ..........................196
9.2.5 HFXO Register Description .......................197
9.3 HFRCO - High-Frequency RC Oscillator ....................216
9.3.1 Introduction ............................216
9.3.2 Features .............................216
9.3.3 Functional Description .........................216
9.3.4 HFRCO Register Map .........................221
9.3.5 HFRCO Register Description .......................222
9.4 DPLL - Digital Phased Locked Loop ......................226
9.4.1 Introduction ............................226
9.4.2 Features .............................226
9.4.3 Functional Description .........................226
9.4.4 DPLL Register Map ..........................228
9.4.5 DPLL Register Description .......................229
9.5 LFXO - Low-Frequency Crystal Oscillator ....................234
9.5.1 Introduction ............................234
9.5.2 Features .............................234
9.5.3 Functional Description .........................234
9.5.4 LFXO Register Map ..........................236
9.5.5 LFXO Register Description .......................237
9.6 LFRCO - Low-Frequency RC Oscillator ....................244
9.6.1 Introduction ............................244
9.6.2 Features .............................244
9.6.3 Functional Description .........................244
9.6.4 LFRCO Register Map .........................246
9.6.5 LFRCO Register Description .......................247
9.7 FSRCO - Fast Start RCO .........................250
9.7.1 Introduction ............................250
9.7.2 Features .............................251
9.7.3 Functional Description .........................251
9.7.4 FSRCO Register Map .........................251
9.7.5 FSRCO Register Description .......................251
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9.8 ULFRCO - Ultra Low Frequency RC Oscillator ..................251
9.8.1 Introduction ............................251
9.8.2 Features .............................251
9.8.3 Functional Description .........................252
10. SMU - Security Management Unit ......................253
10.1 Introduction .............................253
10.2 Features ..............................253
10.3 Functional Description ..........................254
10.3.1 Bus Level Security ..........................254
10.3.2 Privileged Access Control .......................255
10.3.3 Secure Access Control ........................255
10.3.4 ARM TrustZone ...........................256
10.3.5 Configuring Managers ........................256
10.3.6 Configuring Peripherals ........................256
10.3.7 Configuring Memory .........................257
10.3.8 Cortex-M33 Integration ........................257
10.3.9 Exception Handling .........................258
10.3.10 SMU Lock ............................258
10.4 SMU Register Map ...........................259
10.5 SMU Register Description .........................261
10.5.1 SMU_IPVERSION - IP Version .....................261
10.5.2 SMU_STATUS - Status Register .....................262
10.5.3 SMU_LOCK - Lock Register ......................262
10.5.4 SMU_IF - Interrupt Flag Register .....................263
10.5.5 SMU_IEN - Interrupt Enable Register ...................264
10.5.6 SMU_M33CTRL - M33 Control Settings ..................265
10.5.7 SMU_PPUPATD0 - Privileged Access ...................266
10.5.8 SMU_PPUPATD1 - Privileged Access ...................268
10.5.9 SMU_PPUSATD0 - Secure Access ....................270
10.5.10 SMU_PPUSATD1 - Secure Access ....................272
10.5.11 SMU_PPUFS - Fault Status ......................274
10.5.12 SMU_BMPUPATD0 - Privileged Attribute ..................275
10.5.13 SMU_BMPUSATD0 - Secure Attribute...................276
10.5.14 SMU_BMPUFS - Fault Status .....................277
10.5.15 SMU_BMPUFSADDR - Fault Status Address ................277
10.5.16 SMU_ESAURTYPES0 - Region Types 0 ..................278
10.5.17 SMU_ESAURTYPES1 - Region Types 1 ..................278
10.5.18 SMU_ESAUMRB01 - Movable Region Boundary ...............279
10.5.19 SMU_ESAUMRB12 - Movable Region Boundary ...............279
10.5.20 SMU_ESAUMRB45 - Movable Region Boundary ...............280
10.5.21 SMU_ESAUMRB56 - Movable Region Boundary ...............280
11. SE - Secure Engine Subsystem .......................281
11.1 Introduction .............................281
11.2 Security Features ...........................281
11.2.1 Security Features Overview .......................281
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11.2.2 Secure Boot with Root of Trust and Secure Loader (RTSL) ............282
11.2.3 Secure Debug ...........................282
11.2.4 Cryptographic Accelerator .......................282
11.2.5 True Random Number Generation ....................283
11.3 SE Mailbox .............................283
11.3.1 Sending Commands .........................283
11.3.2 Receiving Responses ........................283
11.3.3 MAILBOX Register Map ........................284
11.3.4 MAILBOX Register Description .....................284
12. EMU - Energy Management Unit ......................287
12.1 Introduction..............................287
12.2 Features ..............................288
12.3 Functional Description ..........................289
12.3.1 Energy Modes ...........................290
12.3.2 Entering Low Energy Modes ......................294
12.3.3 Exiting a Low Energy Mode ......................295
12.3.4 Power Domains ...........................296
12.3.5 Voltage Scaling ...........................296
12.3.6 EM0 / EM1 Peripheral Register Retention ..................297
12.3.7 Power Configurations .........................297
12.3.8 Buck DC-DC Interface ........................301
12.3.9 EFP01 Communication ........................304
12.3.10 Brown Out Detector (BOD) ......................305
12.3.11 Reset Management Unit .......................306
12.3.12 Temperature Sensor .........................308
12.3.13 Register Resets ..........................309
12.3.14 Register Locks ...........................309
12.4 EMU Register Map ...........................310
12.5 EMU Register Description .........................312
12.5.1 EMU_DECBOD - DECOUPLE LVBOD Control Register .............312
12.5.2 EMU_BOD3SENSE - BOD3SENSE Control Register ..............313
12.5.3 EMU_VREGVDDCMPCTRL - DC-DC VREGVDD Comparator Control Register .....313
12.5.4 EMU_PD1PARETCTRL - PD1 Partial Retention Control .............314
12.5.5 EMU_IPVERSION - IP Version .....................314
12.5.6 EMU_LOCK - EMU Configuration Lock Register ................315
12.5.7 EMU_IF - Interrupt Flags ........................316
12.5.8 EMU_IEN - Interrupt Enables ......................317
12.5.9 EMU_EM4CTRL - EM4 Control .....................318
12.5.10 EMU_CMD - EMU Command Register ..................319
12.5.11 EMU_CTRL - EMU Control Register ...................320
12.5.12 EMU_TEMPLIMITS - EMU Temperature Thresholds ..............321
12.5.13 EMU_STATUS - EMU Status Register...................322
12.5.14 EMU_TEMP - Temperature ......................323
12.5.15 EMU_RSTCTRL - Reset Management Control Register .............324
12.5.16 EMU_RSTCAUSE - Reset Cause ....................326
12.5.17 EMU_DGIF - Interrupt Flags Debug ...................327
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12.5.18 EMU_DGIEN - Interrupt Enables Debug ..................328
12.5.19 EMU_EFPIF - EFP Interrupt Register ...................328
12.5.20 EMU_EFPIEN - EFP Interrupt Enable Register ................329
12.6 DCDC Register Map ..........................330
12.7 DCDC Register Description ........................331
12.7.1 DCDC_IPVERSION - IPVERSION ....................331
12.7.2 DCDC_CTRL - Control ........................332
12.7.3 DCDC_EM01CTRL0 - EM01 Control....................333
12.7.4 DCDC_EM23CTRL0 - EM23 Control....................334
12.7.5 DCDC_PFMXCTRL - PFMX Control Register .................335
12.7.6 DCDC_IF - Interrupt Flags .......................336
12.7.7 DCDC_IEN - Interrupt Enable ......................337
12.7.8 DCDC_STATUS - Status Register ....................338
12.7.9 DCDC_SYNCBUSY - Syncbusy Status Register ................339
12.7.10 DCDC_LOCK - Lock Register .....................340
12.7.11 DCDC_LOCKSTATUS - Lock Status Register ................340
13. PRS - Peripheral Reflex System .......................341
13.1 Introduction..............................341
13.2 Features ..............................341
13.3 Functional Description ..........................342
13.3.1 Asynchronous Channel Functions.....................342
13.3.2 Configurable Logic ..........................343
13.3.3 Producers .............................344
13.3.4 Consumers ............................351
13.4 PRS Register Map ...........................352
13.5 PRS Register Description .........................368
13.5.1 PRS_IPVERSION - PRS IPVERSION ...................368
13.5.2 PRS_ASYNC_SWPULSE - Software Pulse Register ..............369
13.5.3 PRS_ASYNC_SWLEVEL - Software Level Register ..............370
13.5.4 PRS_ASYNC_PEEK - Async Channel Values ................371
13.5.5 PRS_SYNC_PEEK - Sync Channel Values .................372
13.5.6 PRS_ASYNC_CHx_CTRL - Async Channel Control Register ...........373
13.5.7 PRS_SYNC_CHx_CTRL - Sync Channel Control Register ............374
13.5.8 PRS_CONSUMER_CMU_CALDN - CALDN Consumer Register ..........375
13.5.9 PRS_CONSUMER_CMU_CALUP - CALUP Consumer Register ..........375
13.5.10 PRS_CONSUMER_EUSART0_CLK - CLK Consumer Register ..........376
13.5.11 PRS_CONSUMER_EUSART0_RX - RX Consumer Register ...........376
13.5.12 PRS_CONSUMER_EUSART0_TRIGGER - TRIGGER Consumer Register ......377
13.5.13 PRS_CONSUMER_EUSART1_CLK - CLK Consumer Register ..........377
13.5.14 PRS_CONSUMER_EUSART1_RX - RX Consumer Register ...........378
13.5.15 PRS_CONSUMER_EUSART1_TRIGGER - TRIGGER Consumer Register ......378
13.5.16 PRS_CONSUMER_EUSART2_CLK - CLK Consumer Register ..........379
13.5.17 PRS_CONSUMER_EUSART2_RX - RX Consumer Register ...........379
13.5.18 PRS_CONSUMER_EUSART2_TRIGGER - TRIGGER Consumer Register ......380
13.5.19 PRS_CONSUMER_IADC0_SCANTRIGGER - SCAN Consumer Register.......380
13.5.20 PRS_CONSUMER_IADC0_SINGLETRIGGER - SINGLE Consumer Register .....381
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13.5.21 PRS_CONSUMER_LDMAXBAR_DMAREQ0 - DMAREQ0 Consumer Register .....381
13.5.22 PRS_CONSUMER_LDMAXBAR_DMAREQ1 - DMAREQ1 Consumer Register .....382
13.5.23 PRS_CONSUMER_LESENSE_START - START Consumer Register ........382
13.5.24 PRS_CONSUMER_LETIMER0_CLEAR - CLEAR Consumer Register ........383
13.5.25 PRS_CONSUMER_LETIMER0_START - START Consumer Register ........383
13.5.26 PRS_CONSUMER_LETIMER0_STOP - STOP Consumer Register .........384
13.5.27 PRS_CONSUMER_MODEM_DIN - MODEM DIN Consumer Register ........384
13.5.28 PRS_CONSUMER_PCNT0_S0IN - S0IN Consumer Register ...........385
13.5.29 PRS_CONSUMER_PCNT0_S1IN - S1IN Consumer Register ...........385
13.5.30 PRS_CONSUMER_RAC_CLR - CLR Consumer Register ............386
13.5.31 PRS_CONSUMER_RAC_CTIIN0 - CTI Consumer Register ...........386
13.5.32 PRS_CONSUMER_RAC_CTIIN1 - CTI Consumer Register ...........387
13.5.33 PRS_CONSUMER_RAC_CTIIN2 - CTI Consumer Register ...........387
13.5.34 PRS_CONSUMER_RAC_CTIIN3 - CTI Consumer Register ...........388
13.5.35 PRS_CONSUMER_RAC_FORCETX - FORCETX Consumer Register ........388
13.5.36 PRS_CONSUMER_RAC_RXDIS - RXDIS Consumer Register ..........389
13.5.37 PRS_CONSUMER_RAC_RXEN - RXEN Consumer Register ...........389
13.5.38 PRS_CONSUMER_RAC_TXEN - TXEN Consumer Register ...........390
13.5.39 PRS_CONSUMER_SETAMPER_TAMPERSRC25 - TAMPERSRC25 Consumer Register . 390
13.5.40 PRS_CONSUMER_SETAMPER_TAMPERSRC26 - TAMPERSRC26 Consumer Register . 391
13.5.41 PRS_CONSUMER_SETAMPER_TAMPERSRC27 - TAMPERSRC27 Consumer Register . 391
13.5.42 PRS_CONSUMER_SETAMPER_TAMPERSRC28 - TAMPERSRC28 Consumer Register . 392
13.5.43 PRS_CONSUMER_SETAMPER_TAMPERSRC29 - TAMPERSRC29 Consumer Register . 392
13.5.44 PRS_CONSUMER_SETAMPER_TAMPERSRC30 - TAMPERSRC30 Consumer Register . 393
13.5.45 PRS_CONSUMER_SETAMPER_TAMPERSRC31 - TAMPERSRC31 Consumer Register . 393
13.5.46 PRS_CONSUMER_SYSRTC0_IN0 - IN0 Consumer Register ...........394
13.5.47 PRS_CONSUMER_SYSRTC0_IN1 - IN1 Consumer Register ...........394
13.5.48 PRS_CONSUMER_HFXO0_OSCREQ - OSCREQ Consumer Register .......395
13.5.49 PRS_CONSUMER_HFXO0_TIMEOUT - TIMEOUT Consumer Register .......395
13.5.50 PRS_CONSUMER_CORE_CTIIN0 - CTI0 Consumer Selection ..........396
13.5.51 PRS_CONSUMER_CORE_CTIIN1 - CTI1 Consumer Selection ..........396
13.5.52 PRS_CONSUMER_CORE_CTIIN2 - CTI2 Consumer Selection ..........397
13.5.53 PRS_CONSUMER_CORE_CTIIN3 - CTI3 Consumer Selection ..........397
13.5.54 PRS_CONSUMER_CORE_M33RXEV - M33 Consumer Selection .........398
13.5.55 PRS_CONSUMER_TIMER0_CC0 - CC0 Consumer Register ...........398
13.5.56 PRS_CONSUMER_TIMER0_CC1 - CC1 Consumer Register ...........399
13.5.57 PRS_CONSUMER_TIMER0_CC2 - CC2 Consumer Register ...........399
13.5.58 PRS_CONSUMER_TIMER0_DTI - DTI Consumer Register ...........400
13.5.59 PRS_CONSUMER_TIMER0_DTIFS1 - DTI Consumer Register ..........400
13.5.60 PRS_CONSUMER_TIMER0_DTIFS2 - DTI Consumer Register ..........401
13.5.61 PRS_CONSUMER_TIMER1_CC0 - CC0 Consumer Register ...........401
13.5.62 PRS_CONSUMER_TIMER1_CC1 - CC1 Consumer Register ...........402
13.5.63 PRS_CONSUMER_TIMER1_CC2 - CC2 Consumer Register ...........402
13.5.64 PRS_CONSUMER_TIMER1_DTI - DTI Consumer Register ...........403
13.5.65 PRS_CONSUMER_TIMER1_DTIFS1 - DTI Consumer Register ..........403
13.5.66 PRS_CONSUMER_TIMER1_DTIFS2 - DTI Consumer Register ..........404
13.5.67 PRS_CONSUMER_TIMER2_CC0 - CC0 Consumer Register ...........404
13.5.68 PRS_CONSUMER_TIMER2_CC1 - CC1 Consumer Register ...........405
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13.5.69 PRS_CONSUMER_TIMER2_CC2 - CC2 Consumer Register ...........405
13.5.70 PRS_CONSUMER_TIMER2_DTI - DTI Consumer Register ...........406
13.5.71 PRS_CONSUMER_TIMER2_DTIFS1 - DTI Consumer Register ..........406
13.5.72 PRS_CONSUMER_TIMER2_DTIFS2 - DTI Consumer Register ..........407
13.5.73 PRS_CONSUMER_TIMER3_CC0 - CC0 Consumer Register ...........407
13.5.74 PRS_CONSUMER_TIMER3_CC1 - CC1 Consumer Register ...........408
13.5.75 PRS_CONSUMER_TIMER3_CC2 - CC2 Consumer Register ...........408
13.5.76 PRS_CONSUMER_TIMER3_DTI - DTI Consumer Register ...........409
13.5.77 PRS_CONSUMER_TIMER3_DTIFS1 - DTI Consumer Register ..........409
13.5.78 PRS_CONSUMER_TIMER3_DTIFS2 - DTI Consumer Register ..........410
13.5.79 PRS_CONSUMER_TIMER4_CC0 - CC0 Consumer Register ...........410
13.5.80 PRS_CONSUMER_TIMER4_CC1 - CC1 Consumer Register ...........411
13.5.81 PRS_CONSUMER_TIMER4_CC2 - CC2 Consumer Register ...........411
13.5.82 PRS_CONSUMER_TIMER4_DTI - DTI Consumer Register ...........412
13.5.83 PRS_CONSUMER_TIMER4_DTIFS1 - DTI Consumer Register ..........412
13.5.84 PRS_CONSUMER_TIMER4_DTIFS2 - DTI Consumer Register ..........413
13.5.85 PRS_CONSUMER_USART0_CLK - CLK Consumer Register ...........413
13.5.86 PRS_CONSUMER_USART0_IR - IR Consumer Register ............414
13.5.87 PRS_CONSUMER_USART0_RX - RX Consumer Register ...........414
13.5.88 PRS_CONSUMER_USART0_TRIGGER - TRIGGER Consumer Register.......415
13.5.89 PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 - ASYNCTRIG Consumer Register ...415
13.5.90 PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 - ASYNCTRIG Consumer Register ...416
13.5.91 PRS_CONSUMER_VDAC0_SYNCTRIGCH0 - SYNCTRIG Consumer Register.....416
13.5.92 PRS_CONSUMER_VDAC0_SYNCTRIGCH1 - SYNCTRIG Consumer Register.....417
13.5.93 PRS_CONSUMER_WDOG0_SRC0 - SRC0 Consumer Register ..........417
13.5.94 PRS_CONSUMER_WDOG0_SRC1 - SRC1 Consumer Register ..........418
13.5.95 PRS_CONSUMER_WDOG1_SRC0 - SRC0 Consumer Register ..........418
13.5.96 PRS_CONSUMER_WDOG1_SRC1 - SRC1 Consumer Register ..........419
14. GPCRC - General Purpose Cyclic Redundancy Check ..............420
14.1 Introduction..............................420
14.2 Features ..............................420
14.3 Functional Description ..........................421
14.3.1 Polynomial Specification ........................422
14.3.2 Input and Output Specification ......................422
14.3.3 Initialization ............................422
14.3.4 DMA Usage ............................422
14.3.5 Byte-Level Bit Reversal and Byte Reordering .................423
14.4 GPCRC Register Map ..........................426
14.5 GPCRC Register Description ........................427
14.5.1 GPCRC_IPVERSION - IP Version ID ...................427
14.5.2 GPCRC_EN - CRC Enable .......................428
14.5.3 GPCRC_CTRL - Control Register .....................429
14.5.4 GPCRC_CMD - Command Register ....................430
14.5.5 GPCRC_INIT - CRC Init Value ......................430
14.5.6 GPCRC_POLY - CRC Polynomial Value ..................431
14.5.7 GPCRC_INPUTDATA - Input 32-Bit Data Register ...............431
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14.5.8 GPCRC_INPUTDATAHWORD - Input 16-Bit Data Register ............432
14.5.9 GPCRC_INPUTDATABYTE - Input 8-Bit Data Register .............432
14.5.10 GPCRC_DATA - CRC Data Register ...................433
14.5.11 GPCRC_DATAREV - CRC Data Reverse Register ..............433
14.5.12 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register ...........434
15. SYSRTC - System RTC ..........................435
15.1 Introduction..............................435
15.2 Features ..............................436
15.3 Functional Description ..........................436
15.3.1 Interrupts and Wake Events.......................436
15.3.2 Counter .............................436
15.3.3 Compare Events ..........................436
15.3.4 Capture Events ...........................437
15.3.5 SYSRTC Behavior on SWRST/Disablement/STOP ...............437
15.3.6 Debug Functionality .........................437
15.4 SYSRTC Register Map ..........................438
15.5 SYSRTC Register Description .......................440
15.5.1 SYSRTC_IPVERSION - IP VERSION ...................440
15.5.2 SYSRTC_EN - Module Enable Register ..................440
15.5.3 SYSRTC_SWRST - Software Reset Register .................441
15.5.4 SYSRTC_CFG - Configuration Register ..................441
15.5.5 SYSRTC_CMD - Command Register ...................442
15.5.6 SYSRTC_STATUS - Status Register ...................442
15.5.7 SYSRTC_CNT - Counter Value Register ..................443
15.5.8 SYSRTC_SYNCBUSY - Synchronization Busy Register .............443
15.5.9 SYSRTC_LOCK - Configuration Lock Register ................444
15.5.10 SYSRTC_GRP0_IF - Group Interrupt Flags .................444
15.5.11 SYSRTC_GRP0_IEN - Group Interrupt Enables ...............445
15.5.12 SYSRTC_GRP0_CTRL - Group Control Register ...............446
15.5.13 SYSRTC_GRP0_CMP0VALUE - Compare 0 Value Register ...........447
15.5.14 SYSRTC_GRP0_CMP1VALUE - Compare 1 Value Register ...........447
15.5.15 SYSRTC_GRP0_CAP0VALUE - Capture 0 Value Register ............448
15.5.16 SYSRTC_GRP0_SYNCBUSY - Synchronization Busy Register ..........448
16. BURTC - Back-Up Real Time Counter .....................449
16.1 Introduction..............................449
16.2 Features ..............................449
16.3 Functional Description ..........................450
16.3.1 Clock Selection ...........................450
16.3.2 Configuration ...........................450
16.3.3 Debug Features and Description .....................450
16.3.4 Counter .............................451
16.3.5 Compare Channel ..........................452
16.3.6 Interrupts .............................452
16.3.7 Register Lock ...........................452
16.4 BURTC Register Map ..........................453
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16.5 BURTC Register Description ........................454
16.5.1 BURTC_IPVERSION - IP Version ID....................454
16.5.2 BURTC_EN - Module Enable Register ...................455
16.5.3 BURTC_CFG - Configuration Register ...................456
16.5.4 BURTC_CMD - Command Register ....................457
16.5.5 BURTC_STATUS - Status Register ....................458
16.5.6 BURTC_IF - Interrupt Flag Register ....................458
16.5.7 BURTC_IEN - Interrupt Enable Register ..................459
16.5.8 BURTC_PRECNT - Pre-Counter Value Register ................459
16.5.9 BURTC_CNT - Counter Value Register ...................460
16.5.10 BURTC_EM4WUEN - EM4 Wakeup Request Enable Register ..........460
16.5.11 BURTC_SYNCBUSY - Synchronization Busy Register .............461
16.5.12 BURTC_LOCK - Configuration Lock Register ................462
16.5.13 BURTC_COMP - Compare Value Register .................462
17. BURAM - Backup RAM ..........................463
17.1 Introduction..............................463
17.2 Functional Description ..........................463
17.3 BURAM Register Map ..........................463
17.4 BURAM Register Description ........................464
17.4.1 BURAM_RETx_REG - Retention Register ..................464
18. LETIMER - Low Energy Timer ........................465
18.1 Introduction..............................465
18.2 Features ..............................465
18.3 Functional Description ..........................466
18.3.1 Internal Overview ..........................467
18.3.2 Free Running Mode .........................468
18.3.3 One-shot Mode ...........................469
18.3.4 Buffered Mode ...........................470
18.3.5 Double Mode ...........................471
18.4 Clock Frequency ............................472
18.5 PRS Input Triggers ...........................473
18.6 Debug ...............................473
18.7 Output Action .............................474
18.8 PRS Output .............................474
18.9 Interrupts ..............................474
18.10 Using the LETIMER in EM3 ........................474
18.11 Register Access............................474
18.12 Programmer's Model ..........................475
18.12.1 Free Running Mode .........................475
18.12.2 One Shot Mode ..........................476
18.12.3 DOUBLE Mode ..........................476
18.12.4 BUFFERED Mode .........................477
18.12.5 Continuous Output Generation .....................478
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18.12.6 PWM Output ...........................479
18.13 LETIMER Register Map .........................480
18.14 LETIMER Register Description .......................482
18.14.1 LETIMER_IPVERSION - IP Version ...................482
18.14.2 LETIMER_EN - Module En ......................482
18.14.3 LETIMER_SWRST - Software Reset Register ................483
18.14.4 LETIMER_CTRL - Control Register ....................484
18.14.5 LETIMER_CMD - Command Register ...................486
18.14.6 LETIMER_STATUS - Status Register ...................487
18.14.7 LETIMER_CNT - Counter Value Register..................487
18.14.8 LETIMER_COMP0 - Compare Value Register 0 ...............488
18.14.9 LETIMER_COMP1 - Compare Value Register 1 ...............488
18.14.10 LETIMER_TOP - Counter TOP Value Register ...............489
18.14.11 LETIMER_TOPBUFF - Buffered Counter TOP Value .............489
18.14.12 LETIMER_REP0 - Repeat Counter Register 0................490
18.14.13 LETIMER_REP1 - Repeat Counter Register 1................490
18.14.14 LETIMER_IF - Interrupt Flag Register ..................491
18.14.15 LETIMER_IEN - Interrupt Enable Register .................492
18.14.16 LETIMER_LOCK - Configuration Lock Register ...............493
18.14.17 LETIMER_SYNCBUSY - Synchronization Busy Register ............494
18.14.18 LETIMER_PRSMODE - PRS Input Mode Select Register ............495
19. TIMER - Timer/Counter ..........................497
19.1 Introduction..............................497
19.2 Features ..............................498
19.3 Functional Description ..........................499
19.3.1 Register Access...........................499
19.3.2 Counter Modes ...........................500
19.3.3 Compare/Capture Channels ......................506
19.3.4 Dead-Time Insertion Unit .......................517
19.3.5 Debug Mode ............................521
19.3.6 Interrupts, DMA and PRS Output .....................521
19.3.7 GPIO Input/Output ..........................521
19.4 TIMER Register Map ..........................522
19.5 TIMER Register Description ........................525
19.5.1 TIMER_IPVERSION - IP Version ID ....................525
19.5.2 TIMER_CFG - Configuration Register ...................526
19.5.3 TIMER_CTRL - Control Register .....................529
19.5.4 TIMER_CMD - Command Register ....................530
19.5.5 TIMER_STATUS - Status Register ....................531
19.5.6 TIMER_IF - Interrupt Flag Register ....................534
19.5.7 TIMER_IEN - Interrupt Enable Register ...................536
19.5.8 TIMER_TOP - Counter Top Value Register .................537
19.5.9 TIMER_TOPB - Counter Top Value Buffer Register ...............537
19.5.10 TIMER_CNT - Counter Value Register ..................538
19.5.11 TIMER_LOCK - TIMER Configuration Lock Register ..............538
19.5.12 TIMER_EN - Module En .......................539
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19.5.13 TIMER_CCx_CFG - CC Channel Configuration Register ............540
19.5.14 TIMER_CCx_CTRL - CC Channel Control Register ..............542
19.5.15 TIMER_CCx_OC - OC Channel Value Register ...............543
19.5.16 TIMER_CCx_OCB - OC Channel Value Buffer Register .............544
19.5.17 TIMER_CCx_ICF - IC Channel Value Register ................544
19.5.18 TIMER_CCx_ICOF - IC Channel Value Overflow Register ............544
19.5.19 TIMER_DTCFG - DTI Configuration Register ................545
19.5.20 TIMER_DTTIMECFG - DTI Time Configuration Register ............546
19.5.21 TIMER_DTFCFG - DTI Fault Configuration Register ..............547
19.5.22 TIMER_DTCTRL - DTI Control Register ..................548
19.5.23 TIMER_DTOGEN - DTI Output Generation Enable Register ...........549
19.5.24 TIMER_DTFAULT - DTI Fault Register ..................550
19.5.25 TIMER_DTFAULTC - DTI Fault Clear Register ................551
19.5.26 TIMER_DTLOCK - DTI Configuration Lock Register ..............552
20. USART - Universal Synchronous Asynchronous Receiver/Transmitter ........553
20.1 Introduction..............................553
20.2 Features ..............................554
20.3 Functional Description ..........................555
20.3.1 Modes of Operation .........................556
20.3.2 Asynchronous Operation ........................556
20.3.3 Synchronous Operation ........................572
20.3.4 Hardware Flow Control ........................578
20.3.5 Debug Halt ............................578
20.3.6 PRS-triggered Transmissions ......................578
20.3.7 PRS RX Input ...........................578
20.3.8 PRS CLK Input ...........................579
20.3.9 DMA Support ...........................579
20.3.10 Timer ..............................580
20.3.11 Interrupts ............................585
20.3.12 IrDA Modulator/ Demodulator ......................586
20.4 USART Register Map ..........................587
20.5 USART Register Description ........................590
20.5.1 USART_IPVERSION - IPVERSION ....................590
20.5.2 USART_EN - USART Enable ......................590
20.5.3 USART_CTRL - Control Register .....................591
20.5.4 USART_FRAME - USART Frame Format Register ...............596
20.5.5 USART_TRIGCTRL - USART Trigger Control Register .............598
20.5.6 USART_CMD - Command Register ....................599
20.5.7 USART_STATUS - USART Status Register .................601
20.5.8 USART_CLKDIV - Clock Control Register ..................602
20.5.9 USART_RXDATAX - RX Buffer Data Extended Register .............603
20.5.10 USART_RXDATA - RX Buffer Data Register ................603
20.5.11 USART_RXDOUBLEX - RX Buffer Double Data Extended Register .........604
20.5.12 USART_RXDOUBLE - RX FIFO Double Data Register .............605
20.5.13 USART_RXDATAXP - RX Buffer Data Extended Peek Register ..........605
20.5.14 USART_RXDOUBLEXP - RX Buffer Double Data Extended Peek R... ........606
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20.5.15 USART_TXDATAX - TX Buffer Data Extended Register .............607
20.5.16 USART_TXDATA - TX Buffer Data Register .................608
20.5.17 USART_TXDOUBLEX - TX Buffer Double Data Extended Register .........609
20.5.18 USART_TXDOUBLE - TX Buffer Double Data Register .............610
20.5.19 USART_IF - Interrupt Flag Register....................611
20.5.20 USART_IEN - Interrupt Enable Register ..................613
20.5.21 USART_IRCTRL - IrDA Control Register ..................614
20.5.22 USART_I2SCTRL - I2S Control Register ..................615
20.5.23 USART_TIMING - Timing Register ....................617
20.5.24 USART_CTRLX - Control Register Extended ................619
20.5.25 USART_TIMECMP0 - Timer Compare 0 ..................621
20.5.26 USART_TIMECMP1 - Timer Compare 1 ..................623
20.5.27 USART_TIMECMP2 - Timer Compare 2 ..................625
21. EUSART - Universal Synchronous Asynchronous Receiver/Transmitter ........627
21.1 Introduction..............................627
21.2 Features ..............................628
21.3 Functional Description ..........................629
21.3.1 Modes of Operation .........................630
21.3.2 Asynchronous Operation .......................630
21.3.3 Synchronous Operation ........................650
21.3.4 Debug Halt ............................653
21.3.5 PRS-triggered Transmissions ......................653
21.3.6 PRS RX Input ...........................654
21.3.7 PRS CLK Input ...........................654
21.3.8 DMA Support ...........................654
21.4 EUSART Register Map ..........................655
21.5 EUSART Register Description .......................657
21.5.1 EUSART_IPVERSION - IP Version ID ...................657
21.5.2 EUSART_EN - Enable Register .....................658
21.5.3 EUSART_CFG0 - Configuration 0 Register .................659
21.5.4 EUSART_CFG1 - Configuration 1 Register .................662
21.5.5 EUSART_CFG2 - Configuration 2 Register .................667
21.5.6 EUSART_FRAMECFG - Frame Format Register ...............669
21.5.7 EUSART_DTXDATCFG - Default TX DATA Register ..............670
21.5.8 EUSART_IRHFCFG - HF IrDA Mod Config Register ..............671
21.5.9 EUSART_IRLFCFG - LF IrDA Pulse Config Register ..............672
21.5.10 EUSART_TIMINGCFG - Timing Register ..................673
21.5.11 EUSART_STARTFRAMECFG - Start Frame Register .............675
21.5.12 EUSART_SIGFRAMECFG - Signal Frame Register ..............675
21.5.13 EUSART_CLKDIV - Clock Divider Register .................676
21.5.14 EUSART_TRIGCTRL - Trigger Control Register ...............676
21.5.15 EUSART_CMD - Command Register ...................677
21.5.16 EUSART_RXDATA - RX Data Register ..................678
21.5.17 EUSART_RXDATAP - RX Data Peek Register ................678
21.5.18 EUSART_TXDATA - TX Data Register ..................679
21.5.19 EUSART_STATUS - Status Register ...................680
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21.5.20 EUSART_IF - Interrupt Flag Register ...................682
21.5.21 EUSART_IEN - Interrupt Enable Register .................684
21.5.22 EUSART_SYNCBUSY - Synchronization Busy Register .............686
22. I2C - Inter-Integrated Circuit Interface .....................688
22.1 Introduction..............................688
22.2 Features ..............................688
22.3 Functional Description ..........................689
22.3.1 I2C-Bus Overview ..........................690
22.3.2 Enable and Reset ..........................694
22.3.3 Pin Configuration ..........................694
22.3.4 Safely Disabling and Changing Follower Configuration..............694
22.3.5 Clock Generation ..........................695
22.3.6 Arbitration .............................695
22.3.7 Buffers ..............................695
22.3.8 Leader Operation ..........................698
22.3.9 Bus States ............................706
22.3.10 Follower Operation .........................706
22.3.11 Transfer Automation .........................710
22.3.12 Using 10-bit Addresses ........................711
22.3.13 Error Handling ...........................711
22.3.14 DMA Support ...........................713
22.3.15 Interrupts ............................713
22.3.16 Wake-up .............................713
22.4 I2C Register Map............................714
22.5 I2C Register Description .........................716
22.5.1 I2C_IPVERSION - IP VERSION Register ..................716
22.5.2 I2C_EN - Enable Register .......................716
22.5.3 I2C_CTRL - Control Register ......................717
22.5.4 I2C_CMD - Command Register .....................721
22.5.5 I2C_STATE - State Register ......................722
22.5.6 I2C_STATUS - Status Register .....................723
22.5.7 I2C_CLKDIV - Clock Division Register ...................724
22.5.8 I2C_SADDR - Follower Address Register ..................724
22.5.9 I2C_SADDRMASK - Follower Address Mask Register ..............725
22.5.10 I2C_RXDATA - Receive Buffer Data Register ................725
22.5.11 I2C_RXDOUBLE - Receive Buffer Double Data Register ............726
22.5.12 I2C_RXDATAP - Receive Buffer Data Peek Register ..............726
22.5.13 I2C_RXDOUBLEP - Receive Buffer Double Data Peek Register ..........727
22.5.14 I2C_TXDATA - Transmit Buffer Data Register ................727
22.5.15 I2C_TXDOUBLE - Transmit Buffer Double Data Register ............728
22.5.16 I2C_IF - Interrupt Flag Register .....................729
22.5.17 I2C_IEN - Interrupt Enable Register ...................731
23. IADC - Incremental Analog to Digital Converter .................733
23.1 Introduction..............................733
23.2 Features ..............................734
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23.3 Functional Description ..........................735
23.3.1 Register Access...........................736
23.3.2 Clocking .............................737
23.3.3 Conversion Timing ..........................738
23.3.4 Reference Selection and Analog Gain ...................745
23.3.5 Input and Configuration Selection .....................746
23.3.6 Gain and Offset Correction .......................751
23.3.7 Output Data FIFOs ..........................755
23.3.8 Window Compare ..........................758
23.3.9 Interrupts .............................759
23.3.10 LESENSE Interface .........................759
23.4 IADC Register Map ...........................760
23.5 IADC Register Description.........................763
23.5.1 IADC_IPVERSION - IPVERSION .....................763
23.5.2 IADC_EN - Enable ..........................763
23.5.3 IADC_CTRL - Control .........................764
23.5.4 IADC_CMD - Command ........................766
23.5.5 IADC_TIMER - Timer .........................767
23.5.6 IADC_STATUS - Status ........................768
23.5.7 IADC_MASKREQ - Mask Request ....................769
23.5.8 IADC_STMASK - Scan Table Mask ....................770
23.5.9 IADC_CMPTHR - Digital Window Comparator Threshold .............770
23.5.10 IADC_IF - Interrupt Flags .......................771
23.5.11 IADC_IEN - Interrupt Enable ......................773
23.5.12 IADC_TRIGGER - Trigger .......................775
23.5.13 IADC_CFGx - Configuration ......................778
23.5.14 IADC_SCALEx - Scaling .......................780
23.5.15 IADC_SCHEDx - Scheduling ......................780
23.5.16 IADC_SINGLEFIFOCFG - Single FIFO Configuration .............781
23.5.17 IADC_SINGLEFIFODATA - Single FIFO DATA ................782
23.5.18 IADC_SINGLEFIFOSTAT - Single FIFO Status ................783
23.5.19 IADC_SINGLEDATA - Single Data ....................783
23.5.20 IADC_SCANFIFOCFG - Scan FIFO Configuration ...............784
23.5.21 IADC_SCANFIFODATA - Scan FIFO Read Data ...............785
23.5.22 IADC_SCANFIFOSTAT - Scan FIFO Status .................786
23.5.23 IADC_SCANDATA - Scan Data .....................786
23.5.24 IADC_SINGLE - Single Queue Port Selection ................787
23.5.25 IADC_SCANx - SCAN Entry ......................789
24. GPIO - General Purpose Input/Output .....................791
24.1 Introduction .............................791
24.2 Features ..............................792
24.3 Functional Description ..........................793
24.3.1 Pin Configuration ..........................794
24.3.2 Alternate Port Control ........................796
24.3.3 Slew Rate .............................796
24.3.4 Input Disable ............................796
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24.3.5 Configuration Lock ..........................796
24.3.6 EM2 Functionality ..........................796
24.3.7 EM4 Functionality ..........................796
24.3.8 EM4 Wakeup ...........................797
24.3.9 Debug Connections .........................797
24.3.10 Interrupt Generation .........................798
24.3.11 Output to PRS ...........................799
24.3.12 Peripheral Resource Routing ......................799
24.4 Synchronization ............................807
24.5 GPIO Register Map ...........................808
24.6 GPIO Register Description ........................836
24.6.1 GPIO_IPVERSION - Main .......................836
24.6.2 GPIO_PORTA_CTRL - Port Control ....................837
24.6.3 GPIO_PORTA_MODEL - Mode Low ....................838
24.6.4 GPIO_PORTA_MODEH - Mode High ...................843
24.6.5 GPIO_PORTA_DOUT - Data Out .....................845
24.6.6 GPIO_PORTA_DIN - Data in ......................845
24.6.7 GPIO_PORTB_CTRL - Port Control ....................846
24.6.8 GPIO_PORTB_MODEL - Mode Low ....................847
24.6.9 GPIO_PORTB_DOUT - Data Out .....................851
24.6.10 GPIO_PORTB_DIN - Data in ......................851
24.6.11 GPIO_PORTC_CTRL - Port Control ...................852
24.6.12 GPIO_PORTC_MODEL - Mode Low ...................853
24.6.13 GPIO_PORTC_MODEH - Mode High ...................858
24.6.14 GPIO_PORTC_DOUT - Data Out ....................859
24.6.15 GPIO_PORTC_DIN - Data in ......................860
24.6.16 GPIO_PORTD_CTRL - Port Control ...................861
24.6.17 GPIO_PORTD_MODEL - Mode Low ...................862
24.6.18 GPIO_PORTD_DOUT - Data Out ....................865
24.6.19 GPIO_PORTD_DIN - Data in ......................866
24.6.20 GPIO_LOCK - Lock Register ......................866
24.6.21 GPIO_GPIOLOCKSTATUS - Lock Status .................867
24.6.22 GPIO_ABUSALLOC - A Bus Allocation ..................868
24.6.23 GPIO_BBUSALLOC - B Bus Allocation ..................870
24.6.24 GPIO_CDBUSALLOC - CD Bus Allocation .................872
24.6.25 GPIO_EXTIPSELL - External Interrupt Port Select Low .............874
24.6.26 GPIO_EXTIPSELH - External Interrupt Port Select High .............877
24.6.27 GPIO_EXTIPINSELL - External Interrupt Pin Select Low ............879
24.6.28 GPIO_EXTIPINSELH - External Interrupt Pin Select High ............882
24.6.29 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger ............883
24.6.30 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger ............884
24.6.31 GPIO_IF - Interrupt Flag .......................885
24.6.32 GPIO_IEN - Interrupt Enable ......................887
24.6.33 GPIO_EM4WUEN - EM4 Wakeup Enable .................889
24.6.34 GPIO_EM4WUPOL - EM4 Wakeup Polarity .................889
24.6.35 GPIO_DBGROUTEPEN - Debugger Route Pin Enable .............890
24.6.36 GPIO_TRACEROUTEPEN - Trace Route Pin Enable .............891
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24.6.37 GPIO_LCDSEG - LCD Segment Enable ..................892
24.6.38 GPIO_LCDCOM - LCD Common Enable ..................892
24.6.39 GPIO_ACMP0_ROUTEEN - ACMP0 Pin Enable ...............893
24.6.40 GPIO_ACMP0_ACMPOUTROUTE - ACMPOUT Port/Pin Select ..........893
24.6.41 GPIO_ACMP1_ROUTEEN - ACMP1 Pin Enable ...............894
24.6.42 GPIO_ACMP1_ACMPOUTROUTE - ACMPOUT Port/Pin Select ..........894
24.6.43 GPIO_CMU_ROUTEEN - CMU Pin Enable .................895
24.6.44 GPIO_CMU_CLKIN0ROUTE - CLKIN0 Port/Pin Select .............895
24.6.45 GPIO_CMU_CLKOUT0ROUTE - CLKOUT0 Port/Pin Select ...........896
24.6.46 GPIO_CMU_CLKOUT1ROUTE - CLKOUT1 Port/Pin Select ...........896
24.6.47 GPIO_CMU_CLKOUT2ROUTE - CLKOUT2 Port/Pin Select ...........897
24.6.48 GPIO_EUSART0_ROUTEEN - EUSART0 Pin Enable .............898
24.6.49 GPIO_EUSART0_CSROUTE - CS Port/Pin Select ..............899
24.6.50 GPIO_EUSART0_CTSROUTE - CTS Port/Pin Select .............899
24.6.51 GPIO_EUSART0_RTSROUTE - RTS Port/Pin Select .............900
24.6.52 GPIO_EUSART0_RXROUTE - RX Port/Pin Select ..............900
24.6.53 GPIO_EUSART0_SCLKROUTE - SCLK Port/Pin Select ............901
24.6.54 GPIO_EUSART0_TXROUTE - TX Port/Pin Select ...............901
24.6.55 GPIO_EUSART1_ROUTEEN - EUSART1 Pin Enable .............902
24.6.56 GPIO_EUSART1_CSROUTE - CS Port/Pin Select ..............903
24.6.57 GPIO_EUSART1_CTSROUTE - CTS Port/Pin Select .............903
24.6.58 GPIO_EUSART1_RTSROUTE - RTS Port/Pin Select .............904
24.6.59 GPIO_EUSART1_RXROUTE - RX Port/Pin Select ..............904
24.6.60 GPIO_EUSART1_SCLKROUTE - SCLK Port/Pin Select ............905
24.6.61 GPIO_EUSART1_TXROUTE - TX Port/Pin Select ...............905
24.6.62 GPIO_EUSART2_ROUTEEN - EUSART2 Pin Enable .............906
24.6.63 GPIO_EUSART2_CSROUTE - CS Port/Pin Select ..............907
24.6.64 GPIO_EUSART2_CTSROUTE - CTS Port/Pin Select .............907
24.6.65 GPIO_EUSART2_RTSROUTE - RTS Port/Pin Select .............908
24.6.66 GPIO_EUSART2_RXROUTE - RX Port/Pin Select ..............908
24.6.67 GPIO_EUSART2_SCLKROUTE - SCLK Port/Pin Select ............909
24.6.68 GPIO_EUSART2_TXROUTE - TX Port/Pin Select ...............909
24.6.69 GPIO_FRC_ROUTEEN - FRC Pin Enable .................910
24.6.70 GPIO_FRC_DCLKROUTE - DCLK Port/Pin Select ..............910
24.6.71 GPIO_FRC_DFRAMEROUTE - DFRAME Port/Pin Select ............911
24.6.72 GPIO_FRC_DOUTROUTE - DOUT Port/Pin Select ..............911
24.6.73 GPIO_I2C0_ROUTEEN - I2C0 Pin Enable .................912
24.6.74 GPIO_I2C0_SCLROUTE - SCL Port/Pin Select ...............912
24.6.75 GPIO_I2C0_SDAROUTE - SDA Port/Pin Select ...............913
24.6.76 GPIO_I2C1_ROUTEEN - I2C1 Pin Enable .................913
24.6.77 GPIO_I2C1_SCLROUTE - SCL Port/Pin Select ...............914
24.6.78 GPIO_I2C1_SDAROUTE - SDA Port/Pin Select ...............914
24.6.79 GPIO_KEYSCAN_ROUTEEN - KEYSCAN Pin Enable .............915
24.6.80 GPIO_KEYSCAN_COLOUT0ROUTE - COLOUT0 Port/Pin Select .........916
24.6.81 GPIO_KEYSCAN_COLOUT1ROUTE - COLOUT1 Port/Pin Select .........916
24.6.82 GPIO_KEYSCAN_COLOUT2ROUTE - COLOUT2 Port/Pin Select .........917
24.6.83 GPIO_KEYSCAN_COLOUT3ROUTE - COLOUT3 Port/Pin Select .........917
24.6.84 GPIO_KEYSCAN_COLOUT4ROUTE - COLOUT4 Port/Pin Select .........918
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24.6.85 GPIO_KEYSCAN_COLOUT5ROUTE - COLOUT5 Port/Pin Select .........918
24.6.86 GPIO_KEYSCAN_COLOUT6ROUTE - COLOUT6 Port/Pin Select .........919
24.6.87 GPIO_KEYSCAN_COLOUT7ROUTE - COLOUT7 Port/Pin Select .........919
24.6.88 GPIO_KEYSCAN_ROWSENSE0ROUTE - ROWSENSE0 Port/Pin Select ......920
24.6.89 GPIO_KEYSCAN_ROWSENSE1ROUTE - ROWSENSE1 Port/Pin Select ......920
24.6.90 GPIO_KEYSCAN_ROWSENSE2ROUTE - ROWSENSE2 Port/Pin Select ......921
24.6.91 GPIO_KEYSCAN_ROWSENSE3ROUTE - ROWSENSE3 Port/Pin Select ......921
24.6.92 GPIO_KEYSCAN_ROWSENSE4ROUTE - ROWSENSE4 Port/Pin Select ......922
24.6.93 GPIO_KEYSCAN_ROWSENSE5ROUTE - ROWSENSE5 Port/Pin Select ......922
24.6.94 GPIO_LESENSE_ROUTEEN - LESENSE Pin Enable .............923
24.6.95 GPIO_LESENSE_CH0OUTROUTE - CH0OUT Port/Pin Select ..........924
24.6.96 GPIO_LESENSE_CH1OUTROUTE - CH1OUT Port/Pin Select ..........925
24.6.97 GPIO_LESENSE_CH2OUTROUTE - CH2OUT Port/Pin Select ..........925
24.6.98 GPIO_LESENSE_CH3OUTROUTE - CH3OUT Port/Pin Select ..........926
24.6.99 GPIO_LESENSE_CH4OUTROUTE - CH4OUT Port/Pin Select ..........926
24.6.100 GPIO_LESENSE_CH5OUTROUTE - CH5OUT Port/Pin Select ..........927
24.6.101 GPIO_LESENSE_CH6OUTROUTE - CH6OUT Port/Pin Select ..........927
24.6.102 GPIO_LESENSE_CH7OUTROUTE - CH7OUT Port/Pin Select ..........928
24.6.103 GPIO_LESENSE_CH8OUTROUTE - CH8OUT Port/Pin Select ..........928
24.6.104 GPIO_LESENSE_CH9OUTROUTE - CH9OUT Port/Pin Select ..........929
24.6.105 GPIO_LESENSE_CH10OUTROUTE - CH10OUT Port/Pin Select .........929
24.6.106 GPIO_LESENSE_CH11OUTROUTE - CH11OUT Port/Pin Select .........930
24.6.107 GPIO_LESENSE_CH12OUTROUTE - CH12OUT Port/Pin Select .........930
24.6.108 GPIO_LESENSE_CH13OUTROUTE - CH13OUT Port/Pin Select .........931
24.6.109 GPIO_LESENSE_CH14OUTROUTE - CH14OUT Port/Pin Select .........931
24.6.110 GPIO_LESENSE_CH15OUTROUTE - CH15OUT Port/Pin Select .........932
24.6.111 GPIO_LETIMER_ROUTEEN - LETIMER Pin Enable .............932
24.6.112 GPIO_LETIMER_OUT0ROUTE - OUT0 Port/Pin Select ............933
24.6.113 GPIO_LETIMER_OUT1ROUTE - OUT1 Port/Pin Select ............933
24.6.114 GPIO_MODEM_ROUTEEN - MODEM Pin Enable ..............934
24.6.115 GPIO_MODEM_ANT0ROUTE - ANT0 Port/Pin Select .............935
24.6.116 GPIO_MODEM_ANT1ROUTE - ANT1 Port/Pin Select .............936
24.6.117 GPIO_MODEM_ANTROLLOVERROUTE - ANTROLLOVER Port/Pin Select .....936
24.6.118 GPIO_MODEM_ANTRR0ROUTE - ANTRR0 Port/Pin Select...........937
24.6.119 GPIO_MODEM_ANTRR1ROUTE - ANTRR1 Port/Pin Select...........937
24.6.120 GPIO_MODEM_ANTRR2ROUTE - ANTRR2 Port/Pin Select...........938
24.6.121 GPIO_MODEM_ANTRR3ROUTE - ANTRR3 Port/Pin Select...........938
24.6.122 GPIO_MODEM_ANTRR4ROUTE - ANTRR4 Port/Pin Select...........939
24.6.123 GPIO_MODEM_ANTRR5ROUTE - ANTRR5 Port/Pin Select...........939
24.6.124 GPIO_MODEM_ANTSWENROUTE - ANTSWEN Port/Pin Select .........940
24.6.125 GPIO_MODEM_ANTSWUSROUTE - ANTSWUS Port/Pin Select .........940
24.6.126 GPIO_MODEM_ANTTRIGROUTE - ANTTRIG Port/Pin Select ..........941
24.6.127 GPIO_MODEM_ANTTRIGSTOPROUTE - ANTTRIGSTOP Port/Pin Select ......941
24.6.128 GPIO_MODEM_DCLKROUTE - DCLK Port/Pin Select .............942
24.6.129 GPIO_MODEM_DINROUTE - DIN Port/Pin Select ..............942
24.6.130 GPIO_MODEM_DOUTROUTE - DOUT Port/Pin Select ............943
24.6.131 GPIO_PCNT0_S0INROUTE - S0IN Port/Pin Select ..............943
24.6.132 GPIO_PCNT0_S1INROUTE - S1IN Port/Pin Select ..............944
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