SiRF SiRFatlasV Guide

Design Guide
SiRF Proprietary and Confidential
SiRFatlasV
Hardware Design Guide
January 2010
Document Number: CS-129512-UG
Issue 3
INTRODUCTION
This document serves as a hardware design guide for the SiRFatlasV™ SoC based Evaluation Board
(EVB) including boot configuration, power supply, and peripheral interfaces such as RAM, ROM, USB
and more. For details about theschematics, contact SiRF field applicationengineers (FAE).

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Table of Contents
Introduction ..........................................................................................................................i
SiRFatlasV Feature List .....................................................................................................1
Computing Cores............................................................................................................. 1
Memory Subsystem.......................................................................................................... 1
Advanced Autonomous GPS.............................................................................................. 1
Display, Graphics, and Multimedia...................................................................................... 1
Peripherals and Interfaces................................................................................................. 1
Power Integration.................................................................................................... 1
Audio Integration.................................................................................................... 1
NAND Flash Storage............................................................................................... 2
SD/MMC/MMC+ Controller....................................................................................... 2
USB Connectivity.................................................................................................... 2
Packaging.............................................................................................................. 2
Temperature Range.......................................................................................................... 2
SiRFatlasV SystemBlock Diagram..................................................................................3
Boot Configuration.............................................................................................................4
Power Supply ......................................................................................................................5
Power Pins...................................................................................................................... 5
Decoupling CAP and Placement on the PCB Board............................................................... 6
Power Consumption......................................................................................................... 6
Power-On Sequence......................................................................................................... 6
On-Chip PMU.......................................................................................................................6
Modac...................................................................................................................................7
UART.....................................................................................................................................7
I2C….. ....................................................................................................................................7
USP…....................................................................................................................................8
NAND ....................................................................................................................................8
DRAM....................................................................................................................................8

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USB…...................................................................................................................................8
PCB Layout..................................................................................................................... 8
TSC/ADC ..............................................................................................................................9
Add ESD devices to the Touch Screen Interface (TSI) for ESD protection................................. 9
PCB Layout..................................................................................................................... 9
SD/MMC..............................................................................................................................10
PCB Layout....................................................................................................................11
LCD…..................................................................................................................................11
PCB Layout....................................................................................................................11
Crystal ................................................................................................................................11
PCB Layout....................................................................................................................12
GPIO....................................................................................................................................12
Reset Button Connection................................................................................................12
Avoid I/O Leakage During SoC Power-Off....................................................................14

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List of Tables
Table 1: Mode Configuration Pins................................................................................................. 5
Table 2: PowerPins................................................................................................................... 6
Table 3: On-Chip PMU Specifications and Applications.................................................................... 7
Table 4: Reset Behavior.............................................................................................................13
Table 5: Reset Behavior when Working as a Reset Button..............................................................14
List of Figures
Figure 1: SiRFatlasV System Block Diagram.................................................................................. 3
Figure 2: USB DP/DNRoute........................................................................................................ 8
Figure 3: USB Layout Rule.......................................................................................................... 9
Figure 4: ADCPowerSupply and Reference Decoupling................................................................10
Figure 5: SD0 Power Circuit .......................................................................................................11
Figure 6: 24MHz Crystal Circuit...................................................................................................11
Figure 7: 32.768KHz Crystal Circuit.............................................................................................12
Figure 8: P-MOS and N-MOS in I/OPad.......................................................................................14
Figure 9: Random RTC Reset orOnKey 15s Issue........................................................................15
Figure 10: Workaround for Random RTC Reset or OnKey 15s Issue...............................................16

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SiRFatlasV FEATURE LIST
Computing Cores
500 MHz ARM11 with 16KB D-cacheand I-cache, 16KB D-TCM and I-TCM
250 MHz Enhanced DSP for GPS
Low Poweradvanced 65nm process
MemorySubsystem
64-bit 250MHz system bus with 16 DMA channels
1.8V 16-bit Mobile-DDRsupport
1.8V 16-bit DDR2 support
Advanced Autonomous GPS
64 channels
-161 dBm sensitivity
SiRF Always-Fix technology
Able to acquire and track Galileosignals on all channels
Display, Graphics, and Multimedia
Capable ofsupporting up to 800x480 at 16 bits color
Support RGB565 or16bit CPU I/F TFT LCD panel
Hardware VPP (Video post processor)for de-interlace, scalar,colorspace conversion
Two hardware overlay layers
Peripherals and Interfaces
Power Integration
Two switching DC/DC forcore (700mA)and DRAM (500mA)
One high PSRRand low noise 150mA LDO for I/O and peripheral
One high PSRRand low noise 100mA LDO for analog power
One high PSRRand low noise 10mA LDO for PLL
One high PSRRand low noise 50mA LDO for RF
Audio Integration
One mono differential audio output with 93db SNR and 70db THD (“A” weighted)
One stereo audio output with 93db SNR and 70db THD (“A” weighted) Connectivity
One dedicated AC97/I2S interface
Two dedicated UART ports
Two USP ports forPCM, DSP, I2S, SPI, UARTmode
Two I2C ports
12-bit ADC with 4-wire touch screen controller and 3 channel analog input, stream measurement
mode for lowcost audio input

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NAND Flash Storage
8-bit NAND Flash interface with 12/24bit configurable BCHHW ECCsupport
Supports direct boot from SLC orMLCNAND
Support SLC512B, 2KB, 4KB pagesize
Support MLC 2KB, 4KB, 8KB page size
SD/MMC/MMC+ Controller
SDIO support forWiFi, DVB-T/DVB-H/T--DMB/S-DMB
Supports direct boot from SD/MMC+ Managed NAND
Two 8-bit SD1.01/SD 2.1/MMC4.3 ports
Two 4-bit SD1.01/SD2.1/MMC4.3 ports
USB Connectivity
One USB 2.0 High Speed interfaces with on chipPHY
Can be Host, Device orOTG
Transfer up to 480Mbps
Packaging
10mmx 13mm 285 ball TFBGA with 0.65mm pitch
Temperature Range
-20°C ~ +70°C extended commercial grade

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SiRFatlasV SYSTEM BLOCK DIAGRAM
Figure 1: SiRFatlasV System Block Diagram

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BOOT CONFIGURATION
SiRFatlasV supports many types of boot media including NANDFlash and SD cards. The boot mode can
be set through the modeconfiguration pins according tothe table below.
NOTE –Set the pins with pull-up or pull-down resistors (10 kOhm to 100kOhm), do not leave these pins
set to float.
Working Mode
X_TEST_MODE[5:4]
Sub-Mode
X_TEST_MODE[3:2]
Feature 1
X_TEST_MODE[1]
Feature 0
X_TEST_MODE[0]
2'B00: Normal
2'B01: NormalWith ARM JTAG
2'B10: Function ATE
2'B00: Embedded ROM
NANDBoot (SLC)
1'b0: SLC
1'b0: 2KB page
1'b1: 4KB page
1'b1: LBA-Nand
1'bx: 2KB page
2'B01: NANDBoot(SLC)
1'bx: Don't Care
1'b0: 512B page
1'b1: 2KB page
2'B10: Embedded ROM
NANDBoot (MLC)
1'b0: ECC12bit per
1KB
1'b0: 2KB page
1'b1: 4KB page
1'b1: ECC24bit per
1KB
1'b0: 4KB page
1'b1: 8KB page
2'B11: Embedded ROM
SD/MMC Boot
-
-
2'B11: TESTMODE
2'B00: Scan Mode
2’b00: INTEST_AC_DC
2’b01: EXTEST_AC_DC
2’b10: Reserved
2’b11: Reserved
2'B01: Reserved
-
-
2'B10: CHIP TEST1
1’b0: Boundary
Scan
1’b0: NANDTree
1’b1: BSD
1’b1: Macro Test0
1’b0: BIST
1’b1: Efuse
(x_reset_b = 1'b0)
2'B11: CHIP TEST2
1’b0: Macro Test1
1’b0: USB PHY
StandAlone TEST
1’b1: TSC/PLL
TEST

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Working Mode
X_TEST_MODE[5:4]
Sub-Mode
X_TEST_MODE[3:2]
Feature 1
X_TEST_MODE[1]
Feature 0
X_TEST_MODE[0]
1’b1: Macro Test2
1’b0: MEM PHY
TEST
1’b1: Reserved
Table 1: Mode Configuration Pins
The following lists theconfigurationrules for different boot modes:
For SD/MMC boot mode, use the SD0 port.
For SLC NAND Flash/MLC andSD boot media, use UART1 to download the Nboot image. This
means that UART1 must be used as the debug port for the MLC/SD boot mode.
POWER SUPPLY
Power Pins
Pin Name
Typical Voltage (V)
Description
VDDIO_L
3.3/3.0/2.8/1.8
LCD related I/O pads power
VDDIO_N
3.3/3.0/2.8/1.8
NAND flash related I/O pads power
VDDIO
3.3/3.0/2.8
I/O pads power
VDDIO_MEM
1.8/2.5
The pad power ofthe memory interface
VDD_CORE
1.2
Main core digital power
GND
-
Main digital GND
VDDIO_RTC
3.3
RTC pad power
VDD_RTC
-
Internal LDO output, connect to bypass
cap
VDD_PLL0/1
1.2
PLL pad power
VSS_PLL0/1
-
PLL GND
VDDIO_OSC
3.3
OSC Pad power
VSSIO_OSC
-
OSC PAD GND
VDD_USB
1.2
USBcore digital power
VDDA_USB
3.3
USB analog power
VSSA_USB
-
USB GND
VDD_TSC
1.2
TSC core digital power
VSS_TSC
-
TSC core GND

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Pin Name
Typical Voltage (V)
Description
VDDA_TSC
3.3
TSC analog power
VSSA_TSC
-
TSC GND
VDDIO_DAC
3.3
MoDAC PAD power
VSSIO_DAC
-
MoDAC PAD GND
Table 2: Power Pins
Decoupling CAP and Placement on the PCB Board
For VDD_CORE (1.2V), six 1uF/0402/MLCC need to be placed under the CPU.
Six 220nF/0402/MLCC forVDDIO_MEM
Three 220nF/0402/MLCC for VDDIO
One 220nF/0402/MLCCfor VDDIO_N
One 220nF/0402/MLCC for VDDIO_L
One 220nF/0402/MLCC for VDDIO_DAC
For more details on the placement, contact SiRF field application engineers for the sample PCB layout.
Power Consumption
For power andcurrent budget, referto: CS-130805-DS SiRFatlasV Datasheet.
Power-On Sequence
The SiRFatlasV system power on sequence should follow the sequence in the CS-130805-DS
SiRFatlasV Datasheet.
The power on reset has two important valid reset time values:
RTC power on reset: X_RTC_RST_B should keep thelogic low after the 32KHz crystal isstable
SOC logic hardware reset: X_RESET_B shouldkeep the logic low after the 24MHz crystal is stable
Refer to the SiRFatlasV Datasheet to view the power on reset time’s requirement.
ON-CHIPPMU
The on-chip powermanagement unit (PMU)covers two DCDCconverters (dcdc1, dcdc2), and four to five
LDOs.
NOTE –There are two versions ofthe PMU forSiRFatlasV: thefirst versionhas four LDOs (LDO1~4),
and thesecond version has five LDOs.

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Specand Configuration
Application
DCDC1
1.8v/2.5v, 500mA
Memory powersupply
DCDC2
1.2v, 700mA
CPU core powersupply
USBcore
TSC core power supply
LDO1
3.3V, 100mA
TSC
ADC
USB analog power
LDO2
3.3V, 150mA
VDDIO
VDDIO_N
VDDIO_L
VDDIO_DAC
VDDIO_OSC
LDO3
1.2V, 10mA
PLL pad power supply
LDO4
3.3v,50mA
GPS power supply
LDO5
3.3V
VDDIO_RTC
Table 3: On-Chip PMU Specificationsand Applications
MODAC
Refer to CS-130255-UG SiRFatlasV Audio Hardware Design Guide for the Modac design.
UART
There are two UARTs on the SiRFatlasV chip, but only UART0 has the DMA function. Use UART0 to
transmit large amounts ofdata at high speed.
UART0 has ahardware flowcontrol function.
UART1 must be used as the debug port.
I2C
Add pull-up resistors to all I2C pins.
If there are many I2C devices on one bus, do not release the bus without powering on some of the
devices, otherwise the bus will hang. In this scenario, use GPIO to simulate the I2C bus.

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USP
All USP ports can support the DMA function which allows users to transmit large amounts of data at high
speed.
USP ports cansimulate UART functions but do notsupport odd/even parity.
USP ports can simulate PCM or I2S (DSP mode), in this case X_TFS_0,1 itself can be used as a frame
sync pin.
NAND
Add a pull-up resistor on the pin X_DF_WP_B since it is open drain.
DRAM
Refer to CS-129773-UG SiRFatlasV DDR2/mDDR Hardware Design Guide.
USB
Pay attention to the following when designing the USB module:
Add ESD devices to the DP/DN and ID pins.
Add an 820-Ohm resistor in series with the pin x_usb_vbus to prevent overvoltage.
PCB Layout
The USB 2.0 specification requires that the USB DP/DNtraces maintain a 90 Ohm differential impedance
(see paragraph 7.1.1.3 in USB specification Rev 2.0 for more details). A continuous ground plane is
required directly beneath the DP/DNtraces and extending at least 5 times the spacing width to eitherside
of the DP/DNlines. Maintain the differential impedanceclose to 90 Ohm.
For different dielectric thicknesses, copper weight or board stack-ups, the trace width and spacing will
need to be recalculated. Keep the DP and DM lines symmetrical both in shape and length. Single-ended
impedance is not as critical as the differential impedance, a range of 42 Ohm to 78 Ohm is acceptable
(while the common mode impedance must be within the range of 21 Ohm to39 Ohm).
Figure 2: USB DP/DN Route

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In order to minimize crosstalk, make sure that signal traces are routed close to the two USB differential
signals. The minimum recommended spacing is 3xa for low-speed non-periodic signals, and 7xa for
high-speed periodic signals. Acontinuous ground plane belowthe DP/DN lines is required.
Figure 3: USB Layout Rule
TSC/ADC
Add ESD devices to the Touch Screen Interface (TSI) for ESD protection.
PCB Layout
Due to the analog nature of this block, routing should be done carefully and according to the following
rules:
Keep all analog net routing as small as possible.
Shield allcritical analog nets using the Analog Ground (AGND), especially single-ended nets. Pay
attention to the routing ofthe input lines. Any noisecoupling will be treated as an input signal,
thereby reducing the dynamic range ofthe ADC.
Keep all analog, reference and powersupply lines as wide as possible. Respect themaximum
wire resistance values mentionedin theRouting Constraints section whenthere is a need to
increase the line width or to use several metal layers.
Use as many vias as possible when changing between metal layers.
Power supply decoupling should follow the figure below. The capacitors should be good quality ceramic
and that they must be placed as close to thechip as possible.

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Figure 4: ADC Power Supply and Reference Decoupling
SD/MMC
Add an external pull-up resistor to all data and command signals when using an SD/MMC card or an
iNAND/moviNANDcard. Use SD0 but not SD2 as the boot media.
For MMC/moviNAND, the pull-up resistorshould be:
50 kOhm~ 100 kOhm for the DATA net
4.7 kOhm ~ 100 kOhm for the CMD net
For SD/iNAND, the pull-up resistors to all data and commandsignals should be 10 kOhm ~ 100 kOhm.
Add a quick discharging circuit by pulling the SD0's power lowto GND with a 1 kOhm resistor when SD0
is in power-down state (see R307to Q303 in Figure 5.) The reason for doingthis is:
The iNANDmay not reboot normally if it did not discharge after power-off.

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Figure 5: SD0Power Circuit
NOTE –An alternative way for quick discharging is to use an IC (such as AAT4280IGU-3-T1) instead of
the circuit shown above.
PCB Layout
Route all signals with equal length.
LCD
Add anEMI filterto all nets.
PCB Layout
All nets should be routed as equal length.
CRYSTAL
The following figures are recommendedcircuits for the externalcrystal clock input.
Figure 6: 24MHz Crystal Circuit

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Figure 7: 32.768KHz Crystal Circuit
Crystal part number:
24 MHz,E3SB24.0000F16D23, HOSONIC.
32.768 KHz, 12.5pF, FC-135, EPSON.
PCB Layout
The crystal oscillator is sensitive to stray capacitance and noise from other signals. It can also interfere
with other signals and cause EMI noise. Therefore the load capacitors, crystal and parallel resistors
should be placedclose to each other. The ground under the circuit should remain intact.
GPIO
If a pinis set toGPIO, then GPIO type and settings should be checked. The following settings should be
avoided:
If a GPIO isset as output, then ensure that theoutput value does not conflict with peripherals
during running mode for better powerconsumption management.
RESET BUTTON CONNECTION
SiRFatlasV has several reset function pins:
X_RTC_RST_B
This is a reset signal used to reset all RTC domain logic and power on/off control logic. After the
VDDIO_RTC first powers on, X_RTC_RST_B should be active to guarantee that the RTC logic is
reset and the power on/off control logic enters the RTC_COLDBOOT state. When the system is
running, any time X_RTC_RST_B is active, the RTC logic is reset, causing X_system_en and
X_dram_en tooutput low, and all SoC power except the RTC power willshutdown.
X_RESET_B
This is a hardware logic reset that resets all SoC logic except the RTC domain logic and power
on/off control logic. After the IO power is supplied, X_RESET_B should beactive to guarantee the
SoC logic is reset. While the system is running, any time X_RESET_B is active, all SoC logic
except the RTC logic and poweron/offcontrol logic will bereset

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Warm_RST_B(X_GPIO[8])
This pins default is GPIO<8> and is configured by the software as a warm reset, when input is
low, SoC logic will finish all warm reset procedures, DRAM will beset in self-refresh, and most of
the SoC logic will bereset except theRTC logic and power on/off control logic.
On_Key 15second reset
When a user presses the On_key continuously for up to 15 seconds, the SoC will reset similar to
X-RTC_RST_B
The following table describes the behavior of various types of reset.
Module
X_RTC_RST_B
On_Key 15s
X_RESET_B
Warm-reset
Power on/off control logic
Yes
Yes
No
No
GPSRTC
Power-off
Power-off
Yes
No
SYSRTC
Yes
Yes
No
No
RISC Core
Power-off
Power-off
Yes
Yes
RISC Interface
Power-off
Power-off
Yes
Yes
Interrupt Controller
Power-off
Power-off
Yes
Yes
CLKC
Power-off
Power-off
Yes
Yes
Timer
Power-off
Power-off
Yes
Yes
Resetcontroller
Power-off
Power-off
Yes
No
GPIO
Power-off
Power-off
Yes
Yes
SystemArbiter
Power-off
Power-off
Yes
Yes
RISC CP14 Registers
Power-off
Power-off
Yes
No
OtherSoClogic blocks
Power-off
Power-off
Yes
Yes
Table 4: Reset Behavior
NOTE –“Power-off”means theSoC logic will be powered off through x_system_en and x_dram_en as
“low”; “Yes”means the SoC power is supplied, the logic module is reset.
For details about the resets, refer to CS-130805-DS SiRFatlasV Datasheet.
If the GPS device has a reset button, it is recommended to use warm-reset or X_REST_B to connect to
this reset button. The following table shows the behavior when these four types of reset work as the reset
button.

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Behavior
X_RTC_RST_
B
On_Key 15s
X_RESET_B
Warm-
Reset
Power off logic through x_system_en
and x_dram_en
Yes
Yes
No
No
RTC time loss
Yes
Yes
No
No
SoC logic is reset whensystem running
Power-off
Power-off
Yes
Yes
SoC logic is reset whensystem is in
deep-sleep or hibernation
Power-off
Power-off
No
No
Reboot whensystem is running
No (press
On_key again)
No (press
On_key again)
Yes
Yes
Reboot when thesystem is in deep-sleep
or hibernation
No (press
On_key again)
No (press
On_key again)
No
No
Table 5: Reset Behaviorwhen Workingasa Reset Button
AVOID I/O LEAKAGE DURING SOCPOWER-OFF
The SiRFatlasVSoC has an ESD protection circuit between the I/O pad’s power and theI/O pad, when
the I/O pad is not powered there is an external source to drive this pad “high”or “toggle”, therefore there
may be leakage from theexternalsourceto the I/O power, andthis may result in system instability.
Figure 8: P-MOS and N-MOS in I/O Pad

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This issue happens during the four typicalcases of I/O power loss:
When thesystem enters deep-sleep or hibernation mode
Before the SoC goes into deep-sleep mode or hibernation mode, the software needs to shutdown
peripherals’power to avoid the peripherals driving the SoC I/O pads and thus resulting in I/O
leakage when the I/O power is disabled.
When thesystem is running, the user randomly presses the On-Key for 15s or X_RTC_RST_B
These two reset issues happen randomly by end users but are not controlled by software. It may
result inserioussystem instability. For example:
Figure 9: Random RTC Reset or On Key 15sIssue
When the system is running and the random RTC reset or On Key 15s issue happens, x_system_en and
x_dram_en will output low to disable most of the LDO and buck inside the PMU. However because the
software has no time to control the GPIO to disable the RF LDO, the RF LDO will keep working and the
RF chip will still be powered on. Thus the RF chip keeps driving signals to to the SoC’s I/O pad through
the GPS BB signal pads and the pad’s internal ESD circuit, leakage will go to the I/O VDD. Althoughthe
I/O LDO is disabled, this leakage causes the I/O VDD to have a 1.xV~2.xV floating voltage, therefore the
RF LDO’s enable signal and LCD backlight boost’s enable signal will also have a 1.xV~2.xV level signal.
The voltage may be above the RF LDO and LCD boost enable signal threshold, so thesetwo regulators
keep working.
The I/O leakage due to the RF LDO issue is a dead-loop. The LCD backlight boost will result in a white-
screen and an uncomfortable user experience. Especially, when the system goes into this dead-loop
status, the end usercan only remove the batteryto recover the system.
To solve this problem, reset the SoC logic before the SoC’s I/O and core power loss. Assume that on the
hardware design, the default status of the peripheral’s enable signals such as RF power enable and LCD
backlight enable, after system power-on and reset is “disabled”, when the random RTC reset or On key
15s issue happens, x_system_en or x_dram_en goes to low to disable most of the SoC regulators. If,
before the SoC I/O and core power are fully discharged, there is a way to pull X_RESET_B to low rapidly,

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then the peripheral enable control signals will be reset to “disabled”before the I/O and Core power are
discharged, then the I/O leakage dead-loop will be destroyed, and the system will become stable.
The following is a work around circuit to solve this problem.
Figure 10:Workaround for Random RTC Reset or On Key 15s Issue
When a random RTC reset or On key issue happens, x_system_en is pulled low, so x_reset_b will also
be pulled low quickly via thediode between x_reset_b andx_system_en. Before the Core and I/O power
are really discharged the SoC logic is reset and the I/Os which control the enabled peripherals will go to
the default reset status. The hardware designshould guarantee these control signals are set to “disable”
at the default reset stage, check the SiRFatlasV Datasheet pin list to find every I/O pad’s reset status,
then based on the peripheral’s enable/disable level, add external pull-up or pull-down resisters to make
sure all these enable signals are in “disable” status at the default resetstage
NOTE –RC delay of X_RESET_B is about 20ms andRC delay of X_RTC_RST_B is about 880ms.
System is in deep-sleep or hibernation mode, with peripheral power on and drive signalto SoC
When the system goes into deep-sleep or hibernation mode, x_system_en is pulled low, and most
of the SoC’s power is disabled. However there is still a chance that some external modules are
powered on and can drive the output signals high or toggle to the SoC pads. For example, the
debug module or external TMC or Radar module uses an external adaptor for power and has a
UART connection between the GPS device and the module. In these cases, there may be I/O
leakage from the powered module to the power-off SoC’s I/O VDD. This leakage may result in
potential system instability.
To solve the problem:
–Use the above work around method to ensure that the peripherals are disabled before the
SoC I/O and core power are discharged.
X_SYSTEM_EN
Discharge if power off
D103
MA2S728
1 2
R139
51K 1%
C127
2.2uF
X_SYSTEM_EN
C101
1uF/10V
X_RESET_B
X_RESET_B X_RTC_RST_B
R140
510K 1%
1 2
VDDIO_RTC
R166 NC
C158
100nF
C159
100nF
D101
MA2S728
1 2
S101
1 2
VDDIO_RTC
Warm RESET
R160
10K
D102
MA2S728
1 2
X_ON_KEY_B
VDDIO_RTC
S102
1 2
X_RTC_RST_B
X_GPIO8
R165 0R
RTC RESET