SiRF SiRFatlasV Guide

Design Guide
SiRF Proprietary and Confidential
SiRFatlasV
Audio Hardware Design Guide
January 2010
Document Number: CS-130255-UG
Issue 2
INTRODUCTION
This document serves as a hardware design guide for SiRFatlasVTM audio, including the input and output
paths.

SiRFatlasV
Audio Hardware Design Guide
January, 2010 SiRF Design Guide – Proprietary and Confidential 2
Table of Contents
Introduction ................................................................................................................... 1
Audio Output Path......................................................................................................... 3
Audio Output Path......................................................................................................... 3
DigDAC Overview .........................................................................................................................3
Application Information..................................................................................................................4
Speaker.............................................................................................................................. 4
Headphone......................................................................................................................... 6
Audio Input Path............................................................................................................ 8
Pre-amplifier ................................................................................................................................. 8
SAR ADC...................................................................................................................................... 8
Application Information..................................................................................................................9
Setting the AGC Threshold (R5 and R7) .............................................................................9
Input Capacitor (C4) ........................................................................................................... 9
Power Supply .....................................................................................................................9
RC Buffer ......................................................................................................................... 10
PCB Layout ...................................................................................................................... 10
Performance and Measurement .................................................................................................. 10
Terminology................................................................................................................. 11
List of Figures
Figure 1: DigDAC Block Diagram............................................................................................................. 3
Figure 2: Speaker Circuit ......................................................................................................................... 4
Figure 3: Frequency Response of RC Filter .............................................................................................5
Figure 4: Headphone Circuit ....................................................................................................................6
Figure 5: Frequency Response of Headphone RC Filter .......................................................................... 7
Figure 6: Input Audio Chain .....................................................................................................................8
Figure 7: Pre-amplifier Circuit ..................................................................................................................9
Figure 8: A-weighted Filter Frequency Response................................................................................... 11

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AUDIO OUTPUT PATH
The SiRFatlasV audio output path is built using pure digital IP DigDAC.
DigDAC Overview
DigDAC is a digital Virtual Component. The DigDAC architecture uses an entirely digital approach to
convert digital source input to a PWM signal output. This virtual component features a flexible clock
management system in order to eliminate external audio PLL requirements. It is also optimized for
operation with external amplifiers (analog line out), requiring low out-of-band energy emissions.
Figure 1: DigDAC Block Diagram

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Application Information
Speaker
Performance
SNR = 81dB
THD = 75dB (0.017%)
Output voltage full-scale swing (differential) = 970mV rms
NOTE －The performance has been tested after the RC filter. The test points are TP1 and TP2 as
illustrated in Figure 1.
Test Condition:
Test equipment: Audio precision ATS-2
ATS-2 setting: A-weighted filter; 10Hz~20kHz low-pass filter
DigDAC setting: Volume = 0dB (0x79h)
When testing the SNR, set the input signal to 0to get the noise floor of the headphone output.
Sample rate: 48K/s
Speaker Circuit Design
Figure 2: Speaker Circuit

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RC filter
R97, R100 and C114 form the low pass differential filter, the filter is mainly used to remove the
high frequency switching signal from the DigDAC outputs. The filter should be put as close as
possible to the SoC pad, and be placed symmetrically. PWMRP and PWMRN are differential
signals; to keep the pair symmetrical, the value of the resistors (R97 and R100) should be within
1% precision.
Figure 3 is the frequency response of the filter, and the cut frequency is about 34 kHz.
Figure 3: Frequency Response of RC Filter
Ideally the low-pass filter should have infinite rejection at 20 kHz, but for DigDAC, the cost-
sensitive applications do not, and cannot, use an exotic high-order low pass filter. Therefore the
design uses a one-order RC filter, and it has been verified to be good enough for the application.
Audio amplifier
The audio amplifier amplifies low-power audio signals (signals composed primarily of frequencies
between 20 Hz to 20 kHz, the human range of hearing) to a level suitable for driving loud speakers
and is the final stage in a typical audio playback chain.
Key design parameters for audio amplifiers are frequency response, gain, noise (SNR), and
distortion (THD). These are interdependent; increasing gain often leads to undesirable increases
in noise and distortion. All kinds of audio amplifiers can be used in the application, Class AB,
Class D, etc. In the reference design, a Class D amplifier LM4671 is used. Refer to the
specifications of LM4671 for detailed application information.
PCB design recommendations
Audio traces (PWMRP, PWMRN, etc.) are differential, it is necessary for the positive and negative
paths to be the same in length and always be paired together. The differential pair should be
symmetrical, and it should be laid out and tightly surrounded by ground.
For the audio amplifier, follow the design guide specifications.

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Headphone
Performance
SNR = 83dB
THD = 70dB (0.03%)
Prms@32 Ohm load = 2mW
Test Condition:
Test equipment: audio precision ATS-2
ATS-2 setting: A-weighted filter; 10Hz~20kHz low-pass filter
Auxiliary equipment: Switching amplifier measurement filter AUX-0025, CAB-XBR interconnect
cable kit
DigDAC setting: R/L channel volume = 0dB (0x79h)
When testing the SNR, set the input signal to 0 to get the noise floor of the headphone output.
Sample Rate: 48K/s
Headphone Circuit Design
Figure 4: Headphone Circuit

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Low pass filter
R21 and C13 (R18 and C7) form the low pass filter, the filter is mainly used to suppress EMI
caused by the 400kHz digital signals HEADPHONE_L and HEADPHONE_R. the filter should be
placed as close as possible to the SoC pad.
Figure 5 shows the frequency response of the filter, where the cut frequency is about 106MHz.
Figure 5: Frequency Response of Headphone RC Filter
The resistors (R21 and R18) are not only part of the low pass filter, but are also used to limit the
current, because the drive strength of HEADPHONE_L and HEADPHONE_R (SoC pad) is only
20mA. To maintain the L/R channel’s balance, the precision of the resistor should be within 1%,
and the capacitor should be within 5%.
Voltage divider
R80 and R79 (R77 and R78) form the 1/2 VIO (I/O voltage) divider, which is used for POP noise
suppression.
DC blocking capacitor
C9 (C6) is a DC blocking capacitor, it can be 10uF to 220uF, the capacitor and headphone load
form the high pass filter, the cut frequency is 1/2*pi*C*Rload. Small value capacitors will degrade
the low end frequency response of the headphones.
Discharge resistor
R13 (R11) is a resistor to discharge the DC blocking capacitor. It is used to discharge C9 (C6)
when the system enters sleep mode or powers down.
PCB design recommendations
All the audio traces (HEADPHONE_L, HEADPHONE_R, HPL, HPR, and so on) should be 10mil in
width, and tightly surrounded by ground. The left channel and right channel should be separated
by ground, but kept apart enough to avoid crosstalk.

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AUDIO INPUT PATH
By using an external pre-amplifier and an internal SAR ADC, the SiRFatlasV system forms an audio input
path which interfaces with a single ended microphone. Figure 6 is the audio input path diagram.
Figure 6: Input Audio Chain
Pre-amplifier
The input audio path uses the Maxim MAX9814 as a PGA. The MAX9814 is a low-cost, high-quality
microphone amplifier with automatic gain control (AGC) and low noise microphone bias. The device
features a low-noise preamplifier, variable gain amplifier (VGA), output amplifier, microphone-bias-voltage
generator and AGC control circuitry. For more information about MAX9814, refer to the following link:
http://datasheets.maxim-ic.com/en/ds/MAX9814.pdf
SAR ADC
The ADC is composed of a CMOS 3.3V 12-bit analog-to-digital converter (ADC) with 16-to-1 analog mux,
and level-shifter, switch cell for ADC interface. It converts the analog input signal into 12-bit binary digital
codes at a maximum conversion rate of 1MSPS with a 5MHz clock.
Pins X_AUX0 to X_AUX2 can be ADC input for audio input path.

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Application Information
Figure 7 shows the detailed circuitry of the input audio path.
Figure 7: Pre-amplifier Circuit
Setting the AGC Threshold (R5 and R7)
To set the output-voltage threshold at which the microphone output is clamped, an external resistor-
divider must be connected from the MICBIAS to ground with the output of the resistor-divider applied to
TH. The voltage Vth determines the peak output-voltage threshold at which the output becomes clamped.
The maximum signal swing at the output is then limited to two times Vth and remains at that level until the
amplitude of the input signal is reduced. To disable AGC, connect TH to MICBIAS.
In Figure 7, Vth = 0.54*MICBIAS.
Input Capacitor (C4)
The input AC-coupling capacitor (Cin) and the input resistance (Rin) to the microphone amplifier form a
high-pass filter that removes any DC bias from an input signal Cin prevents any DC components from the
input-signal source from appearing at the amplifier outputs. The -3dB point of the high-pass filter, assuming
zero source impedance due to the input signal source, is given by:
F-3dB = 1/(2*Pi* Rin*Cin)
The input impedance of MAX9814 is 100kOhm.
Power Supply
The MAX9814 and ADC should share the same (PMU_LDO1) power source.

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RC Buffer
The transient loading from the ADC sampling circuits generally causes the amplifier to operate in a
nonlinear mode and exhibit ringing and/or oscillation when driving the switched-capacitor directly. A
mechanism is required which isolates the amplifier from the transient switched-capacitor loading of SAR
ADC.
The addition of the series resistor (R8) and the load capacitor (C5) between the pre-amplifier and the
ADC meet several of the required goals. In this configuration, the instantaneous current for the sampling
capacitor is provided by C5 while the average current is supplied by the operational amplifier (MAX9814).
This greatly reduces the transient current seen by the pre-amplifier and the likelihood that the amplifier
will ring or overshoot. The resistor isolates the amplifier from the transient currents and also provides the
stability required to drive the large capacitive load presented by C5. In addition, the combination of R1 and
CL provide the required single-pole anti-alias filter. Set the R8 value to 50kOhm and C5 to 180pF.
PCB Layout
Keep the analog trace (MIC_IN, X_AUX0, etc.) especially MIC_IN signal far from high speed /
high current switching signals, it’s better to add a ground shield for these traces.
Make X_AUX0 as short as possible.
Put R8 and C5 close to SiRFatlasV.
Put power decoupling capacitors (C1 and C2) as close as possible to the power pin.
In systems where analog and digital grounds are available, connect the MAX9814 to an analog
ground.
Performance and Measurement
Performance:
–THD +N = 50dB@ 1kHz, FS-1dB
–THD = 59dB@ 1kHz, FS-1dB
Follow the test steps to verify the performance.
1. Feed a pure Sine wave to the Mic input, the amplitude of the Sine wave is 12mV (Vp).
Generate the Sine wave by using the Audio Precision ATS-2 analog output or other credible
equipment.
2. Record the waveform for 15 seconds.
3. By using a high quality audio player (SNR > 85dB), play the recorded file and feed the output
wave into audio analysis equipment to obtain the performance data.

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TERMINOLOGY
SNR is defined as the ratio of the full scale (0dB) signal level to the idle channel noise level:
SNR = Signal Level (full scale) – Signal Level (idle input)
THD is defined as the ratio of the sum of the powers of all harmonic components to the power of
the fundamental frequency.
A-weighting filter is commonly used to emphasize frequencies around 3–6 kHz where the human
ear is most sensitive, while attenuating very high and very low frequencies to which the ear is
insensitive. The aim is to ensure that measured loudness corresponds well with subjectively
perceived loudness. A-weighting is only really valid for relatively quiet sounds and for pure tones
as it is based on the 40-phon Fletcher-Munson equal-loudness contour. The B and C curves were
intended for louder sounds (though they are less used) while the D curve is used in assessing
loud aircraft noise
Figure 8: A-weighted Filter Frequency Response
Jitter is the dynamic deviation of event instants in a stream or signal from their ideal positions in
time, excluding modulation components below 10Hz.

January, 2010 SiRF Design Guide – Proprietary and Confidential Part number: CS-130255-UGP2
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