SiRF SiRFatlasV Guide

Design Guide
SiRF Proprietary and Confidential
SiRFatlasV
Power Supply
January 2010
Document Number: CS-200241-DD
Issue 3
INTRODUCTION
This document describes the guidelines for designing the SiRFatlasV™ power supply system, including
the schematics and PCB layout guide.

SiRFatlasV
Power Supply Design Guide
January, 2010 SiRF Design Guide – Proprietary and Confidential i
Table of Contents
Introduction .................................................................................................................... i
SiRFatlasV Package Definition .................................................................................... 1
SiRFatlasV Power Related Pins ................................................................................... 2
Power System................................................................................................................ 5
SiRFatlasV Power Related Schematic ......................................................................... 6
Decoupling Capacitors For the Power Input Pad ....................................................... 6
PCB Layout Examples .................................................................................................. 7
Top Layer Inductor, Capacitors Placement ....................................................................................8
Power Layer Partition.................................................................................................................... 9
VDD_CORE Plane on Layer 3..................................................................................................... 10
Signal Fan out Pattern and Bypass Capacitors for CPU Power on Bottom Layer ......................... 11

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Power Supply Design Guide
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List of Tables
Table 1: Power Pin List............................................................................................................................3
Table 2: Ground Pin List ..........................................................................................................................4
Table 3: SiRFatlasV Electrical Characteristics..........................................................................................5
Table 4: Switching DC/DC, LDOs, Comparator, and Reset Circuit Specification ....................................... 6
List of Figures
Figure 1: SiRFatlasV Package Definition................................................................................................. 1
Figure 2: SiRFatlasV Based System PCB Layer Definition....................................................................... 7
Figure 3: Top Layer Inductor, Capacitors Placement................................................................................8
Figure 4: Power Layer Partition................................................................................................................9
Figure 5: VDD_CORE Plane on Layer 3 ................................................................................................ 10
Figure 6: Signal Fan Out Pattern and Bypass Capacitors for CPU Power on Bottom Layer .................... 11
Figure 7: Placement of Decoupling Capacitors for VDD_CORE ............................................................ 12
Figure 8: Placement of Decoupling Capacitors for VDDIO_MEM............................................................ 12
Figure 9: Placement of Decoupling Capacitors for VDDIO, VDDIO_N, VDDIO_L.................................... 13
Figure 10: Placement of Decoupling Capacitors for VDDIO_DAC........................................................... 13
Figure 11: Increase Trace Width in Top Layer........................................................................................ 14
Figure 12: Increase Trace Width in Bottom Layer................................................................................... 14
Figure 13: Route DDR2’s Vref Trace in the Same Layer with the DDR2 Chip ......................................... 15

SiRFatlasV
Power Supply Design Guide
January, 2010 SiRF Design Guide – Proprietary and Confidential 1
SiRFatlasV PACKAGE DEFINITION
Figure 1: SiRFatlasV Package Definition

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Power Supply Design Guide
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SiRFatlasV POWER RELATED PINS
Pin Name Pin Number Description
VDD_Core
E10, E11, F11,
H8, J8, K6, L8,
M7, N11, P11
Core power.
VDDIO_N E8 I/O power (NAND interface).
VDDIO_L F8 I/O power (LCD interface).
VDDIO E6, E7, N6, P6 I/O power.
VDDIO_MEM
F10, G9, H11,
J9, K11, L10,
M9
Memory I/O power.
VDD_PLL0/1 M1, M2 PLL power
VDD_RTC R12 Digital power output for RTC. Bypass capacitor needed
VDDIO_RTC U15 I/O power for RTC and power input of LDO for RTC digital power.
VDDIO_OSC L3 Crystal oscillator power.
VDD_USB J5 USB PHY core power.
VDDA_USB H1 Analog power for USB.
VDD_TSC P12 Digital power for internal touch screen controller.
VDDA3V3_TSC N13 Analog power for touch screen controller.
VREF_ADC P14 Reference voltage for the ADC
VDDIO_DAC G6 MoDAC power
VINDCDC1_2 W8 Power input for switching DCDC1 and DCDC2.
VINLDO1_2 W12, V12 Power input for LDO1 and LDO2; Power for internal switching
DC/DC and LDOs
VINLDO3_4 W3 Power input for LDO3 and LDO4
L1 W9 Switch pin for DCDC1, connect to inductor
PGND1 W10GND for DCDC1
FB_DCDC1 W11Input to adjust output voltage of DCDC1 through external resistor
divider
EN_DCDC1 V11 Enable control of DCDC1, active high
L2 W7 Switch pin for DCDC2, connect to inductor
PGND2 W6 GND for DCDC2
DEFDCDC2 W5 Input to adjust output voltage of DCDC2 through external resistor
divider

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Pin Name Pin Number Description
VDCDC2 V8 Feedback voltage sense input, directly connect to the output of
DCDC2
EN_DCDC2 W13Enable control of DCDC2, active high
VLDO1 V15 Power output of LDO1
FB1 V14 LDO1 feedback input for the external voltage divider
EN_LDO1 U12 Enable control of LDO1, active high
VLDO2 W4 Power output of LDO2
FB2 V4 LDO2 feedback input for the external voltage divider
EN_LDO2 W14Enable control of LDO2, active high
VLDO3 V1 Power output of LDO3
FB3 V2 LDO3 feedback input for the external voltage divider
EN_LDO3 V7 Enable control of LDO3, active high
VLDO4 W1 Power output of LDO4
FB4 W2 LDO4 feedback input for the external voltage divider
EN_LDO4 V5 Enable control of LDO4, active high
Mode V13
Select between Power Safe Mode and forced PWM Mode for
DCDC1 and DCDC2. In Power Safe Mode, PFM is used at light
loads, PWM for higher loads. If PIN is set to high level, forced PWM
Mode is selected. If Pin has low level, then the device operates in
Power Safe Mode
BP W15Input for bypass capacitor for internal reference, bypass capacitor
needed
THRESHOLD U5 Voltage comparator input, connect to external resistor divider
HYSTERESIS U4 Input for hysteresis on threshold, connect to external resistor divider
COMPO V3 Voltage comparator output, open-drain output, active low
Table 1: Power Pin List

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Pin Name Pin Num Description
VSS
E9, F6, F7, F9,
G8, G10, G11,
H6, H7, H9,
H10, J6, J7,
J10, J11, K7,
K8, K9, K10, L6,
L7, L9, L11, M6,
M8, M10, M11,
N7, N8, N9,
N10, P8, P9,
R8, R9, T7, T8,
T9, T10, U7, U8,
U9, V9
The main digital ground domain.
VSS_PLL0/1 N1, N2 Analog ground for PLL.
VSSIO_OSC M3 I/O ground for oscillator
VSS_TSC R13 Digital ground for internal touch screen controller.
VSSA_TSC N12 Analog ground for the Touch Screen Controller.
VSSA_USB J2 Analog ground for USB PHY
VSSIO_DAC G7 MoDAC ground
Table 2: Ground Pin List

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POWER SYSTEM
Table 3 lists several power inputs for the SoC die:
Domain Power Voltage (V) Ripple and Noise Tolerance
Core VDD_Core 1.2 ±0.06 -
VDD_RTC 1.0± 0.1 -
RTC
VDDIO_RTC 3.3V (2.66~3.63) -
PLL VDD_PLL0, VDD_PLL1 1.2 ± 0.06 ± 50mV
MEM VDDIO_MEM 1.8 ± 0.1 -
VDD_TSC 1.2 ±0.06 -
VDDA3V3_TSC 3.3 ± 0.33 ± 50mV
TSC
VREF_ADC 2.0~VDDA3V3_TSC -
VDDA3V3_USB 3.3 ± 0.33 ± 50mV
USB
VDD_USB 1.2 ±0.06
VDDIO 3.3V(2.66~3.63) -
VDDIO_OSC 3.3V(2.66~3.63)
VDDIO_L 3.3V(1.62~3.63)
I/O
VDDIO_N 3.3V(1.62~3.63)
Table 3: SiRFatlasV Electrical Characteristics
In order to decrease system BOM and PCB size, SiRFatlasV integrates switching DC/DC and LDOs
through SIP with a PMU die. The first generation PMU die integrates two switching DC/DC, four LDOs
and one voltage comparator, and the second generation PMU die will add an additional LDO for RTC
domain power and a reset circuit for the RTC domain logic’s reset.

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The table below lists the switching DC/DC, LDOs, comparator, and reset circuit specifications.
DCDC1 DCDC2 LDO1 LDO2 LDO3 LDO4 LDO5 VC POR
Iout 500mA 700mA 100mA 150mA 10mA 50mA 10mA
Vout
Control
Can be
adjusted
by
outside
resistors
Can be
adjusted
by
outside
resistors
Can be
adjusted
by
outside
resistors.
2nd
version,
fix 3.3V
Can be
adjusted
by
outside
resistors
Can be
adjusted
by
outside
resistors.
2nd
version,
fix 1.2V
Can be
adjusted
by
outside
resistors
Fix
3.3V
Vout
Range 0.9~3.3V 0.9~3.3V 2.5~3.3V 2.5~3.3V 2.5~3.3V 2.5~3.3V 3.3V
On/Off
Control
By
Enable
Pin
By
Enable
Pin
By
Enable
Pin
By
Enable
Pin
By
Enable
Pin
By
Enable
Pin
Alwa
ys
On
PSRR
60db
(10KHz@
30mA)
60db
(10KHz
@30mA)
60db
(10KHz
@30mA)
60db
(10KHz
@30mA)
Line
Reg 3mV 3mV 3mV 3mV 3mV
Load
Reg 25mV 25mV 25mV 25mV 25mV
Noise
40~80uVr
ms
(100Hz~1
00KHz@
75mA)
40~80uV
rms
(100Hz~
100KHz
@75mA)
40~80uV
rms
(100Hz~
100KHz
@75mA)
40~80uV
rms
(100Hz~
100KHz
@75mA)
Usage DRAM Core
Analog
(USB/
TSC/ADC
/MoDAC)
I/O (Pad,
Flash,
LCD,
periphera
l)
PLL RF RTC
Thresh-
old set
by
outside
resisters
with
hystere-
sis
control
For boot-
up
system
low
power
detect
RTC
power
rising up
to 3.0V,
400mS
later RTC
reset
goes to
logic 1.
RTC
power
dropping
to 2.5V,
RTC
reset
goes to
logic 0 at
once.
Table 4: Switching DC/DC, LDOs, Comparator, and Reset Circuit Specification
SIRFATLASV POWER RELATED SCHEMATIC
Contact a SiRF FAE for the SiRFatlasV typical mini application system schematic.
DECOUPLING CAPACITORS FOR THE POWER INPUT PAD
Refer to the mini application system, the following decoupling capacitors are recommended for the design:
Six 1uF/0402/MLCC for the VDD_CORE (1.2V) should be placed under the CPU
Six 220nF/0402/MLCC for the VDDIO_MEM

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Three 220nF/0402/MLCC for the VDDIO
One 220nF/0402/MLCC for the VDDIO_N
One 220nF/0402/MLCC for the VDDIO_L
One 220nF/0402/MLCC for the VDDIO_DAC
PCB LAYOUT EXAMPLES
The SiRFatlasV package and ball-map definition is targeted for the 6-layer PCB layout, with a 16-bit
DRAM interface and optimized high-speed signal integrity design. It has the following features:
Removes serial resistors from the DRAM interface.
Decreases the power/audio function integration.
Makes the PCB layout easier.
Reduces the PCB size.
Figure 2: SiRFatlasV Based System PCB Layer Definition

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Power Supply Design Guide
January, 2010 SiRF Design Guide – Proprietary and Confidential 8
Top Layer Inductor, Capacitors Placement
Figure 3: Top Layer Inductor, Capacitors Placement
By defining the switching DCDC and LDO’s output on the outer side of the BGA package, it is easy to put
inductors and bypass capacitors close to these regulators’ output ball.

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Power Layer Partition
Figure 4: Power Layer Partition
The Power layer partition has the following features:
The VDDIO ball assignment is located on the left side of the SoC package.
VDD_MEM is on the right side of the SoC package.
VDD_CORE is in the middle of the SoC package.
It is easy to divide the power layer into three main power domains:
VDDIO
VDD_CORE
VDD_MEM

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Power Supply Design Guide
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VDD_CORE Plane on Layer 3
Figure 5: VDD_CORE Plane on Layer 3

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Signal Fan out Pattern and Bypass Capacitors for CPU Power on Bottom Layer
Figure 6: Signal Fan Out Pattern and Bypass Capacitors for CPU Power on Bottom Layer
In many cases when designing a 6-layer PCB, the signals can only be routed on three signal routing
layers. The SoC ball-map definition has already taken this into account. In the SoC area, signals can be
routed out to the top and two inner layers, and then they are transferred to the two inner layers to connect
the peripherals.
Most grounds and three main SoC power modules, such as VDDIO, VDD_CORE and VDD_MEM, are
located in the middle area of the SoC package. In order to achieve better power quality, bypass
capacitors are needed for these powers. As in this example, there is space to put 18 bypass capacitors
close to the power balls, so the power noise can be controlled through the bypass capacitors.

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Power Supply Design Guide
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The six pins highlighted by yellow circles in the following picture represent the placement of the
decoupling capacitors on the bottom side for VDD_CORE.
Figure 7: Placement of Decoupling Capacitors for VDD_CORE
The six pins highlighted by yellow circles in the following figure represent the placement of decoupling
capacitors for VDDIO_MEM.
Figure 8: Placement of Decoupling Capacitors for VDDIO_MEM

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Power Supply Design Guide
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The five pins highlighted by yellow circles in the following figure represent the placement of decoupling
capacitors for VDDIO, VDDIO_N, and VDDIO_L.
Figure 9: Placement of Decoupling Capacitors for VDDIO, VDDIO_N, VDDIO_L
The pin highlighted by a yellow circle in the following figure represents the placement of decoupling
capacitors for VDDIO_DAC.
Figure 10:Placement of Decoupling Capacitors for VDDIO_DAC

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Power Supply Design Guide
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In order to achieve good power performance, increasing the width of some power traces and adding more
power vias is recommended.
Figure 11: Increase Trace Width in Top Layer
Figure 12: Increase Trace Width in Bottom Layer
Add more decoupling capacitors near the DDR2’s pin pad and increase the trace width. At the same time,
route DDR2’s Vref trace in the same layer with the DDR2 chip.

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Power Supply Design Guide
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Figure 13: Route DDR2’s Vref Trace in the Same Layer with the DDR2 Chip

January, 2010 SiRF Design Guide – Proprietary and Confidential Part number: CS-200241-DDP3
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