Skyworks Si5360 User manual

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Si5360 Reference Manual
Description
The Si5360 is an 18-output, any-frequency, any-output
clock generator with ultra-low jitter (55 fs RMS at
156.25MHz) providing capabilities to address high-
performance applications such as 112G and 224G Ser-
Des and Coherent Optics.
The Si5360 uses MultiSynth™ fractional divider 
technology to achieve high performance clock 
frequency plans. Programming is made easy with 
Skyworks ClockBuilder Pro™ software and application
programming interface. This manual is intended to
provide system, signal integrity, and software 
engineers the necessary technical information to 
successfully use the Si5360 in end applications.
Related Documents
• Si5360 Data Sheet
• UG514: Si536x Evaluation Board User's Guide
• AN1357: Si536x Schematic Design and Board 
Layout Guidelines
• AN1360: Serial Communications and API 
Programming Guide for Si536x, Si540x, 
and Si55xx Devices
• AN1367: Si55xx/Si540x/Si536x Frequency-on-the-
Fly Guide
• Recommended XTAL, XO, VCXO, TCXO, and OCXO
Reference Manual for Si55xx, Si540x, and Si536x
Products

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1. Introduction to the Si5360 and ClockBuilder Pro
The Si5360 is an 18 output clock generator with ultra-low jitter output clocks suitable for a wide range of applica-
tions. The Si5360 can be quickly and easily configured using ClockBuilder Pro factory pre-programming to build a
custom plan, or can be programmed using a serial interface during operation.
ClockBuilder Pro software is used to create a frequency plan and custom programmed or custom blank orderable
part number (OPN) for the Si5360 Clock Generator. During operation, the Device API embedded on the clock
devices may be used to dynamically adjust or poll the Si5360 parameters. To learn more about configuration set-
tings of the Si5360, open a ClockBuilder Pro Sample Plan and explore.
Figure 1. ClockBuilder Pro Wizard Front Panel showing Sample Plans
This reference manual provides information on the Si5360 hardware capabilities. ClockBuilder Pro and
the Device API are discussed further at the end of this document. The full documentation for the Device
API depends on the part number and is available by link from ClockBuilder Pro.
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2. Functional Description
The Si5360 can use an external crystal, an oscillator or a clock as an input. At the output, a crosspoint
switch connects any generated clock frequencies to any of the outputs which can include connecting one
generated frequency to multiple outputs. The integer Q dividers are capable of ultra-low jitter perfor-
mance (55 fs RMS at 156.25 MHz) and additional integer division may be used at individual outputs to
determine the final output frequency. MultiSynth dividers NA and NB provide fractional frequencies for
a very flexible frequency plan.
The frequency configuration of the Si5360 is programmable through the device serial interface and can
also be stored in non-volatile memory. The combination of flexible dividers allows the generation of
virtually any output frequency on any of the outputs. All divider values for a specific frequency plan are
easily determined using ClockBuilder Pro.
2.1. Block Diagram and Dividers
The block diagram below shows the location of the input integer dividers (INT), the PLL loop divider (M),
the high performance output integer dividers (Q), fractional dividers (NA, NB) and the final output integer
dividers (R).
Figure 2. Si5360 Block Diagram
For a flexible frequency plan, the divide ratios are automatically selected in ClockBuilder Pro. The divider type
(NA, NB or Q) is selected by the user. Selecting the integer divider Q provides ultra-low jitter on integer clock out-
puts. Dividers NA and NB can provide fractional output frequencies. For the Si5360 to deliver the lowest jitter per-
formance, the output clocks must be integer-ratio related to the input clock, i.e., Fout = Fin * M / Q, where
feedback M and Q are integer dividers.
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A summary of the output dividers is provided here:
• Output Q Divider: Q17-Q0
- Integer Only Divide Value
- Open loop divider taps directly off VCO
• Output N Divider: NA, NB
- MultiSynth Divider, Integer or Fractional Divide Value
• Output Divider: R17-R0
- Integer Only Divide Value
2.2. Reset and Initialization
Once power is applied, the Si5360 begins an initialization period where it downloads default firmware
and configuration data from internal non-volatile memory (NVM) and performs initialization tasks. Once
this initialization period is complete, communicating with the device through the serial interface is
possible. Output clocks are generated after the initialization is complete.
There are two types of resets available. A hard reset is functionally similar to a device power-up. All
device settings will be restored to the values stored in NVM, and all circuits will be restored to their initial
state including the serial interface. A hard reset is initiated using the RST pin or using the ClockBuilder
Pro API command RESTART. A soft reset bypasses the NVM download. A soft reset can be initiated using
the API command GLOBAL_SOFT_RESET in Clock Builder Pro. The time from a power on reset to the time
the API is ready is specified in the data sheet.
Other frequency plans can be loaded into the device RAM during system operation via the serial interface
from external CPU/FPGA, the frequency plan will be volatile after power cycle/hard reset.
For details on possible API reset capabilities, see the latest API documentation available from Clock-
Builder Pro.
Figure 3. Si5360 Power-Up and Initialization Sequence Showing Hard and Soft Reset
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3. Dynamic Frequency Changes
Using a ClockBuilder Pro configuration, the Si5360 will have clock output at start up. After start up, dynamic fre-
quency changes can be made using either the Digitally-Controlled Oscillator (DCO) function for small changes, or
the Frequency-On-The-Fly (FOTF) function for larger changes.
3.1. Digitally-Controlled Oscillator (DCO) Functionality
For small changes in output frequency, the PLL in the Si5360 can be frequency controlled glitch-free in pre-defined
steps ranging from 1 ppt to several ppm using the DCO function. The DCO function has some limitations and the
user is advised to carefully review their configuration settings in the DCO Report, and to read the operating limita-
tions described in section 3.1.4. Limitations.
Using the DCO function it is possible to modify either the fractional MultiSynth dividers NA, NB or the PLL feed-
back divider M or all of the dividers. Modifying the PLL feedback M divider will change the frequency of all clock
outputs at once whereas modifying the NA or NB dividers will change only clock outputs using those specific
dividers. The DCO Report, available during DCO configuration with ClockBuilder Pro, shows what dividers are con-
figured to which control command.
For dividers NA and NB, the FINC_DCO/FDEC_DCO command is available by either GPIO assignment or API and
uses a fixed step size to operate on divider(s) selected in the ClockBuilder Pro configuration. The PLL M divider,
when set for FINC/FDEC control is only available to the API control and not the GPIO control.
The VARIABLE_OFFSET_DCO command available in the API is available to all dividers configured in ClockBuilder
Pro.
3.1.1. Using the Frequency Increment/Decrement DCO Function
The incremental DCO command FINC_DCO/FDEC_DCO is designed to control a specific divider with a preconfig-
ured step size change. Using the DCO configuration page of ClockBuilder Pro, the settings for the step size and
specific divider(s) enabled for the FINC_DCO/FDEC_DCO are entered.
Note that DCO control of the M divider changes all clock outputs. For this reason, if the M divider is selected for
control by FINC_DCO/ FDEC_DCO then dividers NA and NB cannot be enabled for this control at the same time.
Applying the FINC_DCO/FDEC_DCO command applies a frequency change equal to the specified step change.
Subsequent entry of the FINC_DCO/FDEC_DCO commands will increase or decrease the frequency by the same
amount. In other words, the output frequency changes are cumulative.
For NA and NB, the FINC_DCO/FDEC_DCO command may be configured to GPIO pins in ClockBuilder Pro. The
command may also be issued during operation using the ClockBuilder Pro API. For details of the Step Size and
which dividers are available to the FINC_DCO/FDEC_DCO command, review the DCO Report available at the DCO
page of ClockBuilder Pro.
3.1.2. Using the Variable DCO
The command VARIABLE_OFFSET_DCO is available through the ClockBuilder Pro API. For details of the step size
and dividers available to this command, see the DCO report available from the bottom of the DCO page in 
ClockBuilder Pro or look at the Design Report.
In ClockBuilder Pro's evaluation board graphical user interface (EVB GUI), the API invocation restricts the variable
command to a single divider. However, the command is not restricted generally and all dividers that have been
configured in ClockBuilder Pro may be controlled by the user as described in the Si5360 API documentation.

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3.1.3. Summary
A brief summary of the commands used to make a DCO frequency adjustment is shown in the table below.
3.1.4. Limitations
To prevent glitches and unexpected clock output, the DCO should apply only an upper limit of only 2 ppm per fre-
quency change step size. The Si5360 has a high-bandwidth PLL and can tolerate higher than 2 ppm DCO steps. It is
important to verify that the performance suits the application.
The FINC_DCO/FDEC_DCO command increments or decrements the output frequency by one step on each call to
the command. In this case, limiting the configuration step size to below 2 ppm is sufficient. However, because the
VARIABLE_OFFSET_DCO can be used to apply multiples of the configuration step size, the user must consider the
product of the step size and the number of steps.
As previously stated, when configured for FINC/FDEC control, the PLL M divider is available to API control not
GPIO.
3.2. Frequency-On-The-Fly
For large frequency changes, the Frequency-On-The-Fly (FOTF) may be used. The FOTF function enables the
Si5360 to change to a subset of clock outputs while leaving others unchanged. For more information on FOTF
operation, see AN1367: Si55xx/Si540x/Si536x Frequency-on-the-Fly Guide.
Table 1. DCO Command Summary
Command
(Command Control) Comment
FINC_DCO (GPIO or API) Increments one or more dividers by a single frequency step defined by the ClockBuilder Pro configuration. This com-
mand may be applied by API or by configured GPIO pins. Uses Desired Step Size setting configured in ClockBuilder Pro.
FDEC_DCO (GPIO or API) Decrements one or more dividers by a single frequency step defined by the ClockBuilder Pro configuration. This com-
mand may be applied by API or by configured GPIO pins. Uses Desired Step Size setting configured in ClockBuilder Pro.
VARIABLE_OFFSET_DCO
(API only)
Applies a positive or negative frequency change as an offset to the original frequency plan value. The offset value and
the divider(s) affected are specified in a single API command.This command may be applied by API only. This command
uses the Desired Step Size setting which is configured in ClockBuilder Pro.

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4. Clock Inputs and Selection
Clock inputs on the Si5360 can be provided through either a crystal input on XA/XB, an external oscillator on
XO_IN/XO_INb pins or on any one of the four input buffers IN0-IN3. Using XO or XTAL results the highest perfor-
mance clocks since there is no jitter attenuating functionality in this device. The Si5360 supports frequency plans
based on a single input; to change the input clock selection, a new ClockBuilder Pro plan must be loaded. Please
refer to Si5360 datasheet for input specification on XTAL/XO and INx.
NOTE: The Si5360 does not provide a holdover function.
Figure 4. XTAL, XO and input clocks on the Si5360
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4.1. Crystal Input
For an ultra low phase noise input for the PLL, an external standard non-pullable crystal (XTAL) on the XA/XB pins
of the Si5360 is recommended. Please refer to Si5360 datasheet on recommended XTAL range for best jitter per-
formance. Recommended XTALs are listed in the Si55xx, Si540x, and Si536x Recommended XTAL, XO, VCXO, TCXO,
and OCXO Reference Manual. Note that the Si5360 includes 8 pF internal crystal loading capacitors which elimi-
nates the need for external capacitors and has the benefit of reduced external noise coupling.
4.2. External Oscillator Input
The Si5360 accepts a crystal oscillator XO input on the XO_IN/XO_INb pins. This input accommodates both single-
ended CMOS as well as differential XOs. Because there is no jitter attenuation in the Si5360 clock generator
device, it is recommended to use a low jitter XO. Additionally, it is important to ensure the power supply for the
XO is well filtered to minimize power supply noise. Recommended XOs are listed in the Si55xx, Si540x, and Si536x
Recommended XTAL, XO, VCXO, TCXO, and OCXO Reference Manual.
4.3. Other Clock Inputs
Each of the four input buffers IN0-IN3 may be independently configured as differential or CMOS single-ended
inputs. In addition, inputs IN2 and IN3 can be configured as two single-ended CMOS inputs, which creates the pos-
sibility of six CMOS inputs. Single-ended and differential input termination should be completed as described in
AN1357: Si5360/61/62/63 Schematic Design and Board Layout Guidelines. For input selection, user may config ref-
erence (XAXB/XO) or inputs as the clock source for the Clock Generator, config a power on default source. In sys-
tem input clock selection is performed using the MANUAL_INPUT_SELECT API vis the serial interface.
4.3.1. Differential Inputs
An input buffer configured in “differential” mode supports differential formats such as LVDS, ac-coupled LVPECL,
HCSL, and CML. The input clock must have a nominally 40 to 60% duty cycle and be ac-coupled since the input
buffer is biased internally. Because VDDIN is common to all of the input buffers, all CMOS inputs signals must have
the same CMOS swing.
4.3.2. CMOS Inputs
All CMOS input buffers are powered by the VDDIN pin. The voltage of the VDDIN pin determines the logic 
threshold of the CMOS inputs. If a 3.3 V CMOS is being given to the input buffer, then VDDIN should be set to 
3.3 V to ensure that the input buffer is able to properly detect the logic high and low levels of the CMOS signal. If
there is a mix of 1.8 V and 3.3 V CMOS inputs, it is recommended to use VDDIN = 1.8 V and add a resistive divider
to attenuate the 3.3 V CMOS input down to 1.8 V.
As previously stated, all inputs can be configured as single-ended CMOS inputs. Additionally, inputs IN2/IN3 can
each be configured as two single-ended inputs, creating six independent input clocks IN2, IN2b, IN3, IN3b, in 
addition to IN0 and IN1.
4.3.3. Unused Inputs
For termination of any unused inputs, please refer to AN1367: Si5360/61/62/63 Schematic Design and Board Lay-
out Guidelines for guidance.

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5. Output Clocks
The Si5360 supports up to 18 differential output clocks. Each output may be independently configured to support
any one of multiple signal formats including LVDS, S-LVDS, ac-coupled LVPECL, HCSL, LVCMOS, CML. In addition, a
custom differential output format supports a programmable amplitude from 200 to 800 mVpp single-ended.
As well as differential outputs, any of the 18 outputs can be configured in LVCMOS to provide up to 36 single-
ended outputs. ClockBuilder Pro software is used to configure the output clock format supporting any combina-
tion of differential and single-ended outputs.
5.1. Output Crosspoint Switch
Each of the output drivers of the Si5360 will derive its clock through an output crosspoint switch. The output 
crosspoint switch from the integer Q-dividers support programmable delay adjustments. While typically, the value
of the output R divider is set to 1 for all clocks derived from Q output dividers, the actual value of the R divider will
be chosen optimally by ClockBuilder Pro and will be displayed in the design report.
Figure 5. Si5360 Output Driver Crosspoint
5.2. Output Signal Format and Terminations
To preserve the signal integrity of the output clocks, it is important to use the proper termination network. For
information on termination, see AN1357: Si5360/61/62 Schematic Design and Board Layout Guidelines.
As discussed previously, the Si5360 supports both differential and single-ended CMOS outputs.
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5.2.1. Differential Output Terminations
A differential output may be configured as LVDS, S-LVDS, ac-coupled LVPECL, CML, or HCSL. Note that the conven-
tional LVPECL terminations that rely on biasing the driver by drawing dc current from the driver should not be
used. For all clock output formats, refer to the terminations described in AN1367: Si5360/61/62/63 Schematic
Design and Board Layout Guidelines.
5.2.2. LVCMOS Output Terminations
As described in AN1367: Si5360/61/62/63 Schematic Design and Board Layout Guidelines, LVCMOS terminations
require a resistance value of Rs placed close to the LVCMOS output driver.
5.2.3. Slew Rate Limited (SRL) CMOS Outputs
On the Si5360, clock outputs OUT16/16b and OUT17/17b may be configured as SRL CMOS outputs, with a lower
slew rate than conventional LVCMOS outputs. Because of the lower slew rate of SRL CMOS, these outputs create
less crosstalk than conventional CMOS outputs and are used when CMOS output is required in jitter-critical appli-
cations. The slew rate is programmable in ClockBuilder Pro.
5.2.4. Output Settings for LVCMOS and SRL CMOS
The swing of LVCMOS and SRL CMOS outputs is rail-to-rail and is determined by the voltage of the corresponding
VDDO pin of the LVCMOS or SRL CMOS output. The slew rate of OUT16/OUT17 is configurable in ClockBuilder Pro.
Each output driver configured as LVCMOS or SRL CMOS has two outputs, OUTx and OUTxb. Each of the two out-
puts may be independently configured as enabled or disabled. Additionally, the polarity of each of the two out-
puts may be independently configured as a non-inverted or inverted output. As mentioned previously, to reduce
coupled noise it is recommended to leave an unused CMOS output pin enabled and inverted from its correspond-
ing pair to mimic a differential output.
5.3. Output Enable/Disable
Each output clock driver of the Si5360 may be enabled/disabled through either programmable GPIO pins or the
API command OUTPUT_ENABLA. There is flexibility in the Si5360 output enable and care should be taken to
understand the various settings.
Using the GPIO to control output enable functions, one or two pins (OE0b and OE1b) may be set as control pins.
The user may assign individual outputs under the OE0b control group and/or the OE1b control group. Please refer
to Figure 6. OE0/OE1 determine which group outputs are enabled at any point in time. The pins may be config-
ured active low or active high. Active low is indicated by adding a "b" at the end of the function name, for example
"OEb" as displayed in ClockBuilder Pro.

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Figure 6. GPI Controlled Output Enable Settings (Output Enable Page)
Figure 7. GPIO settings for Enable Output Group
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Using the API to control output enable functions is possible only if GPIO output enable controls are not assigned in
ClockBuilder Pro. For more information on using the API command OUTPUT_ENABLE, see the API documentation
available in ClockBuilder Pro.
An option of Instant Output Enable (Instant OE) and Instant Output Disable (Instant OD) is possible for clocks
which have a disabled state output of high impedance. Runt pulses can occur on enabled or disabled clocks using
the Instant OE/OD function. To avoid runt pulses, use the regular OE operation rather than instant.
NOTE: Where the output mode is selected as “clock disabled” and the GPIO output enable controls are also
applied, the GPIO takes precedence and the startup mode disabled is ignored.
NOTE: If pins of unused output clocks 6 or 11 are used as GPI pins OE0b, OE1b then their voltage maximum must
equal the associated power supply voltage: OUT6 on VDDO3, OUT11 on VDDO5.

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5.4. State of Disabled Output
The output driver behavior of disabled (stopped) clocks is defined in ClockBuilder Pro. Options include:
1. Stop High (non-inverted clocks get pulled to logic high, inverted clocks get pulled to logic low)
2. Stop Low (inverted clocks get pulled to logic low, inverted clocks get pulled to logic high)
3. Hi-Z (both sides of differential output driver will be floating)
4. Hi-Z with pullup (<2MHz, CMOS outputs only. Non-inverted clocks get pulled to logic high, inverted clocks
get pulled to logic low.)
5. Hi-Z with pulldown (<2MHz, CMOS outputs only, inverted clocks get pulled to logic high, non-inverted
clocks get pulled to logic low.)
Differential outputs, when disabled, will maintain the output common-mode voltage even while the output is not
toggling. This minimizes disturbances when disabling and enabling clock outputs. The high/low voltages are
defined by the selected output format's high/low logic levels.
Clocks will always stop without glitches or runt pulses unless the instant output enable/disable feature is enabled
for the particular output.
Figure 8. Disabled Output Example: LVDS with Stop Low Setting
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5.5. Output-to-Output Skew Control
Within limits, ClockBuilder Pro will align all clock output to a common clock edge. Static offset values entered in
ClockBuilder Pro are relative to this common clock edge and are therefore labeled output-to-output offset or
skew. Output-to-output delay, offset, skew and dynamic phase adjustment in this context all refer to the same
concept of controlling the delayed arrival of one clock edge relative to another clock edge.
In addition to output skew control as a configuration setting in ClockBuilder Pro, groupings of Q divider clock out-
puts can be adjusted during operation with Dynamic Phase Adjust.
5.5.1. Output Skew Control
At startup or device reset, each integer output Q divider will reset to preset static skew configured in ClockBuilder
Pro. Skew control allows clock outputs from the Q dividers to be phase adjusted in steps of 1/fvco (or 1/(4*fvco)
when the fine adjust is enabled). The exact skew adjustment and step sizes are reported on the Output Skew Con-
trol tab in ClockBuilder Pro. A summary of the skew settings is available from a link at the bottom of the tab.
5.5.2. Dynamic Phase Adjust
During operation, output skew can be controlled dynamically by API command. The parameter settings for API
control are found on the ClockBuilder Pro tab Dynamic Phase Adjust (DPA) Outputs. There are four independently
controlled output groups which can control all available Q clock outputs.
The device API commands, OUTPUT_PHINC and OUTPUT_PHDEC, increase or decrease group skew and are
described in more detail in the API documentation available from ClockBuilder Pro.

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6. Status and Alarms
The Si5360 has monitors for the PLL and input/output clocks.
For the PLL, a LOS flag indicates a loss of input signal to the PLL. This LOS flag at the PLL input is available both by
GPIO and by API status polling using the command REFERENCE_STATUS.
For the output clocks, the API command OUTPUTS_AVAILABLE reports if the PLL is locked and providing valid out-
put clocks. If the PLL is not locked, the outputs are squelched and the OUTPUTS_AVAILABLE flag will indicate a
negative result.
For more information on the API commands for REFERENCE_STATUS and the OUTPUTS_AVAILABLE see the 
ClockBuilder Pro API documentation.
Figure 9. Si5360 PLL Status and Alarms
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7. General Purpose Input/Output (GPIO)
The Si5360 has dedicated GPIO pins which may be programmed for several available functions. A list of functions
is described in the Si5360 data sheet.
7.1. GPIO General Settings
In the Si5360, the GPIO is flexible to include possible unused serial port pins and unused outputs.
The table below shows how the dedicated serial interface pins may be configured for SPI 4-Wire, SPI 3-Wire, or
I2C modes. In 3-wire SPI mode or I2C mode with A1 address pin unused, GPIO3 can be used for other GPIO func-
tions. Similarly, in I2C mode with A0 address pin unused, it may also be used for other GPIO. The default behavior
of a GPI pin that has been configured in ClockBuilder Pro, but is left floating in hardware, is specified in the data
sheet.
The device’s dedicated GPIO pins (GPIO0, GPIO1, GPIO2) may be assigned functions according to the table below.
The logic levels of each of the GPIO pins as well as the serial interface pins are determined by the VDDIO setting
which is set in ClockBuilder Pro. For proper operation, the operating voltage of the VDDIO pin must match the
configured VDDIO level setting. The VDDIO level is selectable from 1.8 V, 2.5 V, and 3.3 V. The VDDIO set voltage
value also determines the logic levels of the SPI/I2C serial interface pins. In Low Power Mode, the VDDIO must be
set to 1.8 V. All pins have a weak pull-up or pull-down resistor to set a default state when not externally driven.
The default state of the GPI is always de-asserted except for OEx which is by default asserted to enable the out-
puts. The internal resistance of the pull resistor is 20 kΩtypical. GPIO selectable status outputs (GPO) are push-
pull and do not require any external pull-up or pull-down resistors.
Please see the Si5360 data sheet for a list of GPIO functions and default pull-up or pull-down states.
7.2. Unused Outputs as GPIs
If outputs OUT6/6b and/or OUT11/11b are unused, they may be used as general purpose input (GPI) pins. Since
each driver consists of an inverted and non-inverted output, each unused output may serve as two independent
GPI pins, allowing up to four additional programmable GPI pins. The logical threshold of the unused outputs being
used as GPIs is set by the corresponding VDDOx voltage.
Table 2. GPIO Pin Settings for the Serial Interface
Pin Pin Name Mode: SPI 4-Wire Mode: SPI 3 Wire Mode: I2C
56 GPIO3 SDO GPIO3 A1/GPIO3
52 SDA/SDIO SDI SDIO SDA
53 SCLK SCLK SCLK SCLK
55 A0/CSb CSb CSb A0/GPIO
Table 3. GPIO Generic Settings
Pin Pin Name
16 GPIO0
18 GPIO1
19 GPIO2

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8. Serial Interface
Configuration and operation of the Si5360 is controlled by using the API to communicate via the primary I2C or SPI
serial interface. The ClockBuilder Pro serial port interface mode is stored in NVM for automatic configuration on
startup or reset (as described in 2.2. Reset and Initialization) and is associated with the orderable part number 
(discussed in 10. Custom Programmed vs Custom Blank Parts).
The logic levels of the serial interface and GPIO are set by the choice of VDDIO. The VDDIO voltage levels may be
nominal 1.8 V, 2.5 V, or 3.3 V. The selection should match the logic level voltage in the end system.
NOTE: In low power mode VDDIO must be set to 1.8 V.
8.1. I2C Interface
See AN1360: Serial Communications and API Programming Guide for Si536x, Si540x, and Si55xx Devices for
instructions on using the Device API.
When in I2C mode, the serial interface operates in slave mode with 7-bit addressing and can operate in Standard-
Mode (100 kbps) or Fast-Mode (400 kbps). The I2C bus consists of a bidirectional serial data line (SDA) and a serial
clock input (SCL) as shown in the figure below. Both the SDA and SCL pins must be connected to a supply via an
external pull-up (4.7 kΩ) as recommended by the I2C specification. Two address select bits (A0, A1) are provided.
This allows up to four Si5360 devices on the same I2C bus.
Figure 10. I2C Configuration
The 7-bit slave device address of the device consists of a 5 fixed bit address configured in ClockBuilder Pro plus
two pins which are selectable for the last two bits. An example is shown in the following figure.
NOTE: the Si5360 is not fail-safe upon loss of power. Applications that require fail-safe operation should isolate
the device from a shared I2C bus.
Table 4. OUTx Pins as GPIs
VDDOx OUTx
VDDO3 OUT6/6b
VDDO5 OUT11/11b
SDA
SCLK
Clock IC
VDDI2C
(VDDIO)
To I
2
C Bus
or Host
A0
A1
LSBs of I
2
C
Address
I
2
C
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Figure 11. 7-bit I2C Slave Address Bit-Configuration
8.1.1. I2C Operation
To begin a transaction, the host controller pulls the SDA low while SCL is high. This triggers the I2C START event.
The host controller sends the 7-bit slave address followed by a read/write bit (1 = read and 0 = write). If this
address matches the device address configured for the Si5360, then it will send an acknowledgment by pulling the
SDA line low during the ACK cycle.
Now, if the host controller needs to perform a write operation, then it continues sending data on the SDA line and
if a read operation is performed, then the Si5360 device sends its data on the SDA line. Any number of data bytes
may be transferred in single transaction. There are nine cycles per byte: eight data bits followed by one acknowl-
edge cycle.
To end the transaction, the host controller will release the SDA pin while SCL is high, which triggers the I2C STOP
event. Most I2C transactions are burst transactions that transfer multiple data bytes between the start and stop
events.
The following waveforms show the basic I2C transaction waveforms for a single data byte:
Figure 12. I2C Command Write Transaction
Figure 13. I2C Reply Read Transaction
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The Si5360 is programmed using Device API Command and Reply opcodes. Again, see AN1360: Serial Communica-
tions and API Programming Guide for Si536x, Si540x, and Si55xx Devices for instructions on using the Device API.
The I2C interface uses the Device API command (also called the register address in other I2C devices) 0x0FF0. This
command address should be written with a little endian (LE) bit order. for both the command and reply opcodes.
The API commands are dependent on the firmware version and are available from ClockBuilder Pro.
8.1.2. I2C Write
The host can send a Device API command by sending the Device API command opcode 0x0FF0 (see LE note above
and diagram below).
Note that the host controller can send a command only when the CTS bit is low and when an I2C STOP event is
received at the end of the transaction, the CTS bit will be automatically cleared. The following figure shows how a
Device API command is sent using I2C.
Figure 14. I2C Command Write Operation
8.1.3. I2C Read
The host controller reads the response from the Si5360 device by reading from the MCU portal address: 0x0FF0.
This address should be written with a little endian (LE) bit order. Note the Read Command is the same command
value as the Write Command above. Send the LSB first then the MSB as shown in the Command Write Operation
figure.
Initially when the CTS bit is low, the MCU will return only the Status byte which is the first byte in the Reply. This
byte contains the CTS bit (i.e., bit 7). All the following bytes will return 0.
Now, if CTS is high, it implies that the device's reply is ready and the rest of the bytes that follow the Status byte
will give the requested data to read by the host. The following figure shows how an MCU reply is received using
I2C.
Figure 15. I2C Reply Read Operation
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8.2. SPI Interface
See AN1360: Serial Communications and API Programming Guide for Si536x, Si540x, and Si55xx Devices for
instructions on using the Device API.
The primary SPI serial interface can be operated in either 4-wire or 3-wire mode. This is selected in ClockBuilder
Pro while creating the OPN. Device configuration and status monitoring must always be done using the primary
interface. The 4-wire interface consists of a clock input (SCLK), a chip select input (CS), serial data input (SDI), and
serial data output (SDO). The 3-wire interface combines the SDI and SDO signals into a single, bidirectional data
pin (SDIO). Both 4-wire and 3-wire interface connections are shown in the figure below. There is also a secondary
readback SPI 3-wire interface. When enabled, CSb2/GPIO0, SDIO2/GPIO1, and SCLK2/GPIO2 pins will be dedi-
cated to the secondary 3-wire SPI interface for phase readback operation and other low latency operations.
NOTE: The secondary interface is not a replacement for the primary SPI interface.
Figure 16. SPI Interface Connections
When operating in the 4-wire mode, separate SDI and SDO pins are used. For the 3-wire mode, the SPI port will
use the SDI pin as a bidirectional data pin and the SDO pin will remain unused and can be left unconnected. The
host controller lowers the CSb at the beginning of a transaction, sends the command and then the data burst.
After sending all the data bytes, the host will raise the CSb pin, which will terminate the transaction. The timing
diagrams for the SPI command status read and command write with both the SPI modes are shown in the follow-
ing figures.
NOTE: For all SPI communication, the chip select bar (CSb) line must be high for the minimum time period
between commands. When chip select goes high, it indicates the termination of the command. The SCLK can be
turned off between commands, particularly if there are very long delays between commands.
To SPI
Host
SDI
SDO
Clock IC
SCLK
CSb
SPI 4-Wire
CSb
SDIO
SCLK
SPI 3-Wire
To SPI
Host
Clock IC
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