Skyworks Si8281v2-EVB User manual

USER GUIDE
Skyworks Solutions, Inc. • Phone [949] 231-3000 • [email protected] • www.skyworksinc.com
206571B • Skyworks Proprietary Information • Products and Product Information are Subject to Change without Notice
June 2, 2023
1
UG519: Si8281v2-EVB User Guide
Key Features
• Si8281 ISODrivers for 4 A or higher gate drive with
current booster daughter cards
• Sockets for TO-247 package SiC FETs or IGBTs
• Capable of double pulse test
• DESAT short circuit and many other performance
evaluations
Description
The Si8281v2-EVB is a versatile platform that 
demonstrates the capabilities of the Si8281 SiC 
FET-Ready ISODriver with Safety Features and 
integrated dc/dc converter for driving SiC FET or IGBT
power switching devices. It includes two switch device
sockets, with the high-side switch device connected in
the off-state to function as a diode. This setup enables
the low-side SiC/IGBT switching device to work with an
external inductor to support double pulse testing and
switching loss measurements. The EVB can also be
used to test the Si8281 gate driver capabilities, such as
output current and DSAT protection circuits, by placing
a SiC or IGBT switch in the low-side socket and 
exercising the onboard Si8281 low-side driver.
The output current of the Si828x is rated at 4 A, which is sufficient to drive most discrete SiC FETs and IGBTs. 
However, for applications that require a higher gate drive current, customized external bipolar transistor-based
current booster circuits can be used with the Si828x gate drivers. These current booster circuits are located on a
small daughter card (DC) that comes with the kit, and they can be used to drive high-power SiC/IGBT switching
devices.
The Si8281v2-EVB (Evaluation Board) is equipped with solder bump jumpers that facilitate testing of the Si8281
gate driver with or without the included but optional external current booster circuit. This allows users to assess
the performance of the gate driver with or without the booster circuit and determine if the booster circuit is 
necessary for their specific application. Also, the EVB can accommodate switching devices in 3- and 4-pin TO-247
packages; however, switching devices (Q1 and Q2) are not included in the kit. The user may acquire switching
devices that are appropriate for their specific application.
The Si8281 gate drivers are powered by an integrated dc-dc converter that drives an external transformer to 
generate +15 V and –4 V biasing voltages. This integrated dc-dc converter enables the Si8281 isolated full-feature
gate driver to provide a compact solution for medium and high-power switching applications.

UG519: Si8281v2-EVB User Guide
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1. Schematics
Figure 1. Si8281 Gate Driver Circuit
TP6VSSX TP5VMID
VMID
VSSX
GNDB
TP8VMID
TP14
IN+
TP4VDDX
TP15
IN-
CONN TRBLK 2
J1 1
2
TP11
/RST
D5
GREEN
VDDA
TP12
/FLT
D7
GREEN
VDDB
TP13
RDY
D8
GREEN
VSSB
R9
10K
D25
5.6V
TRANSF
Transformer
3-4
1-2
8
6-7
5
R13
0
C7
10uF
C8
0.1uF
R19
0
VDDAF
R8
10K
D21
3.0V
NI
R78
50
TP23VSSB
VDDA TP20
DSAT
ISOLATION
U2
Si8281CD-IS Si8281
VDDA
4
VH 15
CLMP 13
VSW
2
GNDP
1
NC 18 VDDP
3
DSAT 17
VSNS 20
/RST
6
/FLT
7
VDDB 16 GNDA
5
RDY
8
COMP 19
VL 14
IN+
9
IN-
10
VMID 12
VSSB 11
D20
US1M-13-F
C49
10uF
R3 100K C10 1.5nF
VDDBin
R2 8.66K
R1
145K
C3
10uF
C5
10uF
C22
1uF
C4
0.1uF
C6
0.1uF
VH
VL
C33
22pF
CLMP
C34
22pF
VSSBin
VH R27 2.2K
D9
1N4148W
GNDA
S1
/RST
C16
100pF
GNDA
VSSB
D1
MBR1H100SF
D2
MBR1H100SF
R5
100
C2
100pF
R21
10K
TP28
GNDA
R25 2K
C24
0.01uF
R26 13.0K
GNDA
bottom side
VDDAF
J16
SMA
INPUT
VDDX
VSSX
VMID
AlLTERNATIVE DRIVER SUPPLIES
3x5mm
J3
1
VSSX
2
VMID
3
VDDX
D24
10V
GNDA
VDDA
C32
22pF
C31
22pF
R36
0NI
R35
50
1. For VDDB/VSSB = 15/-3.5, use JP12 position 1
2. For VDDB/VSSB = 17/-4.5, use JP12 position 2
3. To operate with Vout positive only:
a. Remove R13
b. Install R19 = 0 Ohm
c. Change divider Vout = (R1/R2 + 1) x 1.05V
D26
24V
VSSBin
R6
1.0
GNDB
VDDA
TP9
GNDA
VMID
JP9
DSAT Dis
HEADER 1x3
SPDSAT
DSAT
GNDB
R22
10K
R23
0
GNDA
C12
2.2uF
C13
0.1uF
close to part
TP7
VDDA
JS6
JS7
R76
165K
JP12
+15V
HEADER 1x3
+17V
VDDB
VDDAF
TP2
GNDA
R4 100
C15
0.1uF
C14
2.2uF
TP21
D+2Vd
R77 0
R24
10K
GNDA
C9
0.1uF
D3
US1M-13-F
VDDB
VMID
VMID
VMID
SFM-108-01-L-D
SOCKET 8x2
Socket, 8x2, 0.05in pitch, Gold Plated. PTH
J24
P1 1 P2
2
P3 3 P4
4
P5 5 P6
6
P7 7 P8
8
P9 9 P10
10
P11 11 P12
12
P13 13 P14
14
P15 15 P16
16
VMID
VMID
VH
VL
M_CLMP
GATE
GATE
GATE
GATE
VDDB
VDDB
VSSB
VSSB
IN+/IN- have weak internal pull down (4uA).
Signal sources should be placed as close as possible to
IN+/IN- inputs to minimize noise coupling.
IN+/IN- should be terminated directly to VDDA/GNDA
accordingly if not used.
VDDB VSSB
VDDX
VDDBin
VSSBin
J22
1
2
3
DSAT
GNDB
JS1
C18
1uF
VSSX
GNDB
J23
1
2
3
D18
RED
/FLT
JS2
R56
3K
C17
1uF
R55
3K
TP22VDDB
D17
GREEN
RDY
VDDA
D21/R77 are colocate
GNDA
GNDA
DRAIN
VH
VL
CLMP
VSSB
VMID

UG519: Si8281v2-EVB User Guide
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Figure 2. High Power SiC Circuit
Figure 3. Current Booster Daughter Card Schematic
J34
J35
R69
200K
R70
200K
R68
200K
R71
200K
R72
200K
R65
200K
R64
200K
R63
200K
R66
200K
R67
200K
VSSBin
TIN LINK
TP16
DCRAIL
TP17
DRAIN
D22
MBR1H100SF
TP18
HVCAP
D23
MBR1H100SF
VDDBin
VDDBin
TP19 DCRAIL_GND
VSSBin
R75
0
DCRAIL_GND
J25MMCXVG-2
GNDB
J13
MMCX
VGS
TPV13 TPV14
Boost Circuit
Boost
VMID
VH
VL
M_CLMP
GATE
VDDB
VSSB
TP25GNDB
TP26
GNDB
TP27
VGS
TP24VG-2
J33
Q1(mutually exclusive):
Populate J30 for 4 pin SiC (default)
Populate J31, J33 for 3 pin SiC
TP29
Src_K-Q2
TP30
Drain-Q1
TP31
Src_K-Q1
bottom side, RA, south edge
C50
270pF
NI
DRAIN
bottom side, red to center,
route to south edge, trim to fit.
C52
10µF
C51
10µF
DCRAIL_GND
DCRAIL
R46
0.200
2W
GNDB
J12
SMA
IDRV
C43
220nF
J30
J26
J27
J28
BNC
DRAIN_SRC-Q2 NI
R73 0.001NI
J29
Resistor value and power rating for R10, R11,
R12 are depended on switching frequency and
gate loading of the IGBT/MOSFET device
HEAT SINK
HS1 CR101-50-AE
NI
2 1
TP3
Drain-Q2
VL
R10 2.0
TPV12
CLMP
CLMP
GNDB
VMID
HS
CLIP
HW1
CLA-TO-21E
NI
Use
BERGQUIST SIL-PAD 900S Thermal Material Electrical nsulator between
Heat Sink and MOSFET
J31
VMID
GNDB
DRAIN
At TPV13 & TPV14:
TPV9070 (0.070 hole), for #14 wire;
0.250 apart for BNC sense resistor
R5810
DCRAIL
D19
MBRA340T3G
R60
100
Q10
MMBT2907A
R61
12
200A currents
30A currents
4A currents
DCRAIL_GND
C44
270pF
Soft-Shutdown Circuit
J20
BNC
DRAIN_SRC-Q1
NI
R11 2.0
4A currents
4A currents
Q1
SiC-FET
G1
D2
S4K
S3
G5
9.5x9.7mm
J18
DRAIN
9.5x9.7mm
J19
DCRAIL_GND
Snubber
Q2
SiC-FET
G1
D2
S4K
S3
G5
9.5x9.7mm
J17
DCRAIL
R59
10.0
VH
VL
CLMP
VH
DRAIN
VSSBin
VH
VL
CLMP
VH
VL
CLMP
9.5x9.7mm
J21
HVCAP
J32
RSS
5.1
TPV1
VMID
TPV2
VDDB
TPV3
VH
TPV5
VL/VO
TPV6
M_CLMP
TPV7
VSSB
TPV4
GATE
Q1A
ZXTN19060CG
Q1B
PHPT60415NY
Q1C
MJD44H11
DPAKSOT-669SOT-223SOT-89
Q2A
FZT951
Q2B
PHPT60415PY
Q2C
MJD45H11
Alternate NPN Packages, overlay where possible
Alternate PNP Packages, overlay where possible
J1
HEADER 8x2
0102
0304
0506
0708
0910
1112
1314
1516
VMID
VMID
GATE
GATE
VDDB
VSSB
VDDB
VSSB
VMID
VMID
VMID
VH
VL/VO
GATE
M_CLMP
GATE
D1
MBR0580S1
D2
1N4148W
VH
RB4
100
VL/VO
R1
10
R2
20
Q1
ZXTN2010ZTA
Q2
ZXTP2012ZTA
CP
CN
Q3
ZXTP2027FTA
RB3 100
BGATE
VSSB
M_CLMP
VDDB
30A peak current
RH
1.0
RL
1.0
VSSB
VDDB
C1
10uF
VMID
C2
0.1uF
C5
10uF
C6
0.1uF
C3
10uF
C4
0.1uF
D3
MBR0580S1
Q4
ZXTP2027FTA

UG519: Si8281v2-EVB User Guide
Skyworks Solutions, Inc. • Phone [949] 231-3000 • sale[email protected] • www.skyworksinc.com
206571B • Skyworks Proprietary Information • Products and Product Information are Subject to Change without Notice
4June 2, 2023
2. Power Up
The Si8281v2-EVB can be operated with a 5 V power supply that has a minimum current capability of 0.5 A. This is
because the Si8281 integrated dc-dc controller can work with an external transformer to generate all the neces-
sary voltages to power the gate driver and the gate of the SiC/IGBT devices.
To power up the Si8281v2-EVB, you should first ensure that the jumpers are connected according to the factory
default jumper positions as described in Table 2.1. Then, connect the +5 V supply to the terminal block J1 by
applying +5 V to Pin 1 (VDDA) and returning GND to Pin 2.
The Si8281v2-EVB should be powered up with the indications shown in Table 2.
Table 1. Default Jumper Positions (Set at Factory)
Jumper Number Purpose
J22 Pins 1 and 2 Connecting p/s VDDB to Si8281
J23 Pins 1 and 2 Connecting p/s VSSB to Si8281
JP9 Pins 2 and 3 DESAT disable
JP12 Pins 1 and 2 Setup for VDDB = 15 V, VSSB = –3.5 V
J1 Pin 1 to 5 V, Pin 2 to GND
Table 2. Si8281v2-EVB Power-Up Indications
Test Passing Criteria Associated Components
Check voltage, TP7-TP2 ~5 V D25, J1
Check +5 V p/s current (J13) < 110 mA Si8281, T1, D1, D2
Green LED D5 VDDA Illuminated J1, D25, R24
Green LED D7, VDDB Illuminated T1, Si8281, D1, R26
Green LED D8, VSSB Illuminated T1, Si8281, D2, R25
Green LED D17, RDY Illuminated Si8281, T1, D1, D2
Check voltage on VDDB to VMID at TP5 to TP22 +15 V T1, D1, C3, C4, Si8281
Check voltage on VSSB to VMID at TP5 to TP523 –3.5 V T1, D2, C5, C6, Si8281

UG519: Si8281v2-EVB User Guide
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5June 2, 2023
3. Testing Si828x Gate Driver with Capacitive Load
The Si8281 gate driver and the current booster Daughter Cards offer a wide range of gate currents to drive all SiCs
and IGBTs to their optimum levels. The Si8281v2-EVB supports a test apparatus that is illustrated in the circuit 
diagrams shown in Figure 4 and Figure 5, which can be used to measure the gate driver output current.
The current booster Daughter Card can be easily connected to the Si8281v2-EVB through the J24 connector. 
The solder bump jumpers SB1 (J27) and SB2 (J32, J34, J35, J26) provide flexibility in testing the Si8281 gate driver
either directly or through the current booster circuit.
The gate resistors (Rg) and the configuration of the current booster circuits are used to set the Si8281 gate current
drive levels, enabling circuit tuning for specific SiC and IGBT gate current requirements. This feature allows users
to optimize the performance of the gate driver and current booster circuits to meet the needs of their specific
applications.
Figure 4. Gate Driver Output Current Test Circuit
Figure 5. Connections for Si8281 Gate Current Testing with a Capacitive Load
Rg
+
-
I
Sense
R
46
C
43
IN+
Si828x
SB1
SB2
Current
Booster
5V
GND
J1
PWM
Signal
Ch4: VGS-Q1
J13 MMCX or
TP27-TP26
Diff-Probe SMA
Ch3: I
sense

UG519: Si8281v2-EVB User Guide
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3.1. Setup for Testing with Capacitive Load
The Si8281v2-EVB is equipped with jumpers and solder bumps (PCB trace jumpers) that allow for selective 
connection of the capacitive load to either the Si8281 or the current booster daughter cards’ output for gate 
current testing. Table 3 provides the appropriate jumper connections for each specific test.
Perform the following simple steps to conduct gate current testing:
1. Connect jumpers, solder bumpers, the booster daughter card, and instrumentation as described in Table 3.
2. Connect function generator to J16: 50 output impedance, single 5 Vp-p square wave pulse (6 µs).
3. Set up the 5 V/div scope probe to view the VGS gate signal at J13 or TP27–TP26.
4. Set up the oscilloscope to trigger on the rising edge of the VGS (item #3) signal.
5. Setup a voltage scope probe to ISense current with 200 mV/A scaling.
6. Power up the 5 V power supply connected to J1.
7. Send one PWM pulse from the function generator and observe the waveforms on the oscilloscope.
Table 3. Connections for Gate Current Testing
Testing Configuration Si8281 Direct Drive Si8281 with Current Booster DC
JP9 2–3 2–3
J26 Close Open
J27 Open Close
J29 Close Close
J30 Open Open
J31 Open Open
J32 Close Open
J33 Open Open
J34 Close Open
J35 Close Open
J24 Open Plug into the Current Booster Daughter Card
J1 P/S: Pin 1 to 5 V, Pin 2 to GND P/S: Pin 1 to 5 V, Pin 2 to GND
J16 PWM signal PWM signal
J12 (MMCX) or TP26-TP27 VGate Scope Probe VGate Scope Probe
J12 SMA Voltage Probe for ISense SMA Voltage Probe for ISense

UG519: Si8281v2-EVB User Guide
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7June 2, 2023
3.2. Test Results
Figure 6 illustrates the Si8281 output current waveform when tested with a C43, 220 nF capacitive load and a 0 
gate resistor. It is noteworthy that the Si8281 is capable of sourcing 2.6 A and sinking 5.6 A of current.
Figure 6. Gate Output Current from Si8281 and Rg = 0 
I
IGATE
VGATE
2.6A
-5.6A

UG519: Si8281v2-EVB User Guide
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8June 2, 2023
Figure 7. Gate Output Current from Si8281 with Booster Daughter Card and Rg = 0 
Figure 7 illustrates that the Si8281 can generate up to +15 A of sourcing current and –19 A of sinking current when
operating with the current booster to drive a C43, 220 nF capacitive load. The values of R1 and R2 on the booster
daughter card (as shown in Figure 3) can be adjusted to accommodate applications that require higher gate
current levels than 15 A. R1 should be set to a minimum of 1 for higher output currents, while R2 should be set
to a maximum of 40 for increased current output.
3.3. Additional Advice
To optimize gate currents for specific SiC FET or IGBT, designers can use the Si828x external circuits, which provide
flexible controls. The output current capability is determined by the values of RH, RL, R1, R2, and the gain value
of the Q1 and Q2 transistors. Before changing the Q1 and Q2 transistors, designers should explore changing the
values of RH, RL, R1, and R2 since transistors with higher gain are more expensive.
For more information on the latest Si828x current booster circuit, please review the Skyworks application note,
“AN1288: Si828x External Enhancement Circuits”.
I
IGATE
VGATE
15A
-19A

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9June 2, 2023
4. Double Pulse Testing and Switching Loss
Figure 8 illustrates a simplified double pulse test circuit for the Si8281. During the on period of Q1, current flows
from the bypass capacitor CRAIL (+RAIL) through the inductor Lo, Q1, and back to the ground terminal of CRAIL.
When Q1 turns off, the current in the inductor is maintained through the body diode of Q2. The current is then
ramped up again in the next switching cycle through Q1. The switching loss can be calculated as the integral of
Q1's VDS multiplied by IDS during the switching transitions. This circuit allows for multiple switching cycles,
enabling measurement of Q1 switching loss at different IDS current levels.
Figure 8. Si8281 Double Pulse Test Circuit
Si8281
VH
VL
M_CLMP
+ RAIL
RH
RL
Q1
-VSSB
100
DSAT
Q2
Q1
off
VDS_Q1
I
DS
Q1 on
+
-
Lo
C
Rail

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4.1. Connections for Double Pulse Switching Loss Testing
Table 4 provides a jumper map and instrumentation connections for double pulse switching loss testing. Note that
this test involves high voltage, and extreme caution must be observed. Contact could result in severe shock or
death.
Perform the following steps to conduct a double pulse test:
1. Install Q1 and Q2 and the corresponding solder bumps:
a. Three pins SiC/IGBT package: short J31, J33; open J30.
b. Four-pins SiC package: open J31, J33; short J30.
2. Use bus wire to short J17 through J21 (parallel C51 and C52 for higher current handling capability).
3. Connect an air-core inductor between J17 (DCRAIL) and J18 (DRAIN).
4. Connect the DC-Rail power supply (100 mA minimum current rating) to J21 (+) through J19 (–), and set the 
output to the appropriate voltage level.
5. Connect jumpers, solder bumpers, booster daughter card, and instrumentation as described in Table 4.
Table 4. Connections for Double Pulse Switching Loss Testing
Testing Configuration Si8281 Direct Drive Si8281 with Current Booster DC
JP9 1–2 1–2
J24 Open Plug into the Current Booster Daughter Card
J26 Close Open
J27 Open Close
J29 Open Open
J30 See below (three vs. four pins SiC) See below (three vs. four pins SiC)
J31 See below (three vs. four pins SiC) See below (three vs. four pins SiC)
J32 Close Open
J33 See below (three vs. four pins SiC) See below (three vs. four pins SiC)
J34 Close Open
J35 Close Open
J1 P/S: Pin 1 to 5 V, Pin 2 to GND P/S: Pin 1 to 5 V, Pin 2 to GND
J16 PWM signal PWM signal
Ch4: IsoVu or HV Diff. probe VGate: J12 (MMCX) or TP26-TP27 VGate: J12 (MMCX) or TP26-TP27
Ch2: HV Differential Probe VDS from TP30(+) to TP31(–) VDS from TP30(+) to TP31(–)
Ch3: T&M Research SDN-414-01 R73: ISense R73: ISense

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6. Set up the function generator connected to SMA J16: 50 output impedance, five pulses 5 Vpp 
square wave.
7. Connect the isolated scope probe (IsoVu) to the J13. If the IsoVu probe is unavailable, use an HV differential
voltage scope probe across TP27 (+) through TP26 (–) the Q1 VGS. Set up the oscilloscope trigger to VGS
(Ch4).
8. Connect a voltage scope probe (HV differential) from the oscilloscope Ch2 to TP30 (+) through TP31 (–). 
Set up oscilloscope Ch2 to the appropriate voltage level for Q1 VDS.
9. Connect a coaxial cable from oscilloscope Ch3 to the T&M Research SDN-414-01 BNC connector. Set up Ch3
for 0.01 V per Ampere scale.
10.Set up the oscilloscope's math function to ∫(Ch2 × Ch3) to calculate the VDS X IDS switching loss.
11.Power up the 12 V power supply (connected to J1).
12.Power up the DC-Rail power supply (see Step 4).
13.Send PWM pulses from the function generator and observe the waveforms on the oscilloscope.
Figure 9. Double Pulse Test Connections for Si8281v2-EVB
+ Rail
- Rail
+
Ra
-
R
a
5V
GND
J1
PWM
Signal
Ch4: V
GS
-Q1
J13 MMCX or
TP27-TP26
Diff-Probe
SDN-414-01
Ch3: I
DS
To the Inductor
TP30-TP32
Diff-Probe
Ch2: V
DS

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4.2. Switching Loss Test Results
In Figure 9, the connections for the double pulse test with the Si8281 and the current booster daughter card are
depicted. The switching loss data presented in this section were obtained under specific test conditions, which
include:
1. Q1 and Q2: Wolfspeed C3M0016120K SiC in the 4-pin TO-247 package.
2. Rg = 1 (gate resistor).
3. Lo: 24 µH air core inductor.
4. VDS = 800 V.
5. With and without a current booster daughter card.
6. Five pulses of 300 kHz PWM signal to ramp IDS from 0 A to ~ 250 A.
Figure 10 shows the double pulse switching waveforms for the above test conditions.
Figure 10. Double Pulse Switching Waveforms (without Current Booster)
VDS
IDS
Vgate

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Figure 11. Turn On Switching Waveforms at IDS = 120 A (without Current Booster)
Figure 12. Turn On Switching Waveforms at IDS =120 A (with Current Booster)
VDS
IDS
Vgate
Switching
loss
VDS
IDS
Vgate
Switching
loss

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The oscilloscope math function was used to calculate the switching loss from VDS and IDS waveforms by setting it
to ∫(Ch2 × Ch3). Once the cursor is placed on the math waveform across the switching transitions duration, the
switching loss is calculated and displayed on the table at the top right of the scope image. Figure 11 and Figure 12
show that the turn-on switching loss of C3M0016120K is 2.53 mJ and 1.61 mJ, respectively, at IDS = 120 A, with a
36% reduction in turn-on switching loss when using an external current booster. Additionally, Figure 13 and 
Figure 14 provide switching loss data for C3M0016120K with and without the external current booster, while 
Figure 15 compares the switching loss for Si8281-C3M0016120K with and without the external current booster
circuits.
Figure 13. Switching Loss Si8281 (C3M0016120K with Current Booster Daughter Card)

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Figure 14. Switching Loss Si8281 (C3M0016120K without Current Booster Daughter Card)

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Figure 15. Switching Loss Comparison Si8281 (C3M0016120K with/without Current Booster Daughter Card)
4.3. Observations
In Figure 15, it is shown that when the C3M0016120K is operated directly with the Si8281 (without the current
booster circuit), the switching loss is similar to the switching loss data in the Wolfspeed data sheet. However,
when the C3M0016120K is operated with the Si8281 and its external current booster circuit, the switching loss is
significantly lower.

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5. DESAT Short Circuit Test
Figure 16 depicts the setup for conducting the DESAT (desaturation) test on the Si8281 and the switching device
under short circuit conditions. The Q2 Drain and Source terminals are intentionally shorted to create a 
low-impedance path between the Q1 Drain terminal and the power +RAIL. This causes a high-voltage, 
high-current, short-circuit condition when Q1 is turned on. It is imperative that the Si8281's DESAT feature detects
this condition and turns off Q1 within its safe duration before permanent damage occurs. For most Silicon Carbide
power devices, the short-circuit response time should be less than 1 µs.
Figure 16. Si8281 DESAT Test Circuit
Si828x
VH
VL
M_CLMP
+ RAIL
RH
RL
Q1
-VSSB
100
DSAT
Q2
C
Rail
VH
RI
-VSSB

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Figure 16 shows the DESAT test setup for the Si8281 with external components for detection, soft shutdown 
duration, and overall DESAT response time. The following resistors provide DESAT timing adjustments for the
Si828x:
• Detection resistor: RI
The installed value of RI on the Si8281v2-EVB is 2.2 k, which sets the DESAT detection time. Lowering the
value of RI decreases the detection time (minimum value is 1 k). If RI is removed from the DESAT circuit (J9),
the internal current source of the Si8281 sets the detection time to its maximum level.
• Soft Shutdown Resistor: RSS
The Si8281 provides a fixed DESAT soft shutdown duration with its internal RSS of 50 . However, this 
duration may not be suitable for all applications as it could either lengthen the response time or cause high
voltage spikes during fault shutdown. To optimize the soft shutdown duration, an external bipolar transistor is
used to adjust the RSS values and provide programmability. This allows designers to fine-tune the design for
DESAT response time and voltage spike level to achieve optimal performance.
The above adjustments determine the DESAT response time, which is the duration required for IDS current to go
from ~ 0 A back down to ~ 0 A in a short circuit event. The DESAT response time should be less than 3 µs for IGBTs
and less than 1 µs for SiC FETs for robust protection.

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5.1. Connections for DESAT Short Circuit Test
Table 5 provides jumper map and instrumentation connections for a Si828x DESAT short circuit test. Note that this
test involves high voltage, and extreme caution must be observed. Contact could result in severe shock or death.
Perform the following steps to conduct a DESAT short circuit test:
1. Install Q1 and Q2 and the corresponding solder bumps.
a. Three pin SiC/IGBT package: short J22, J31, J32; open J23.
b. Four pin SiC package: open J22, J31, J32; short J23.
2. Solder a bus wire across the Drain to Source terminals of Q2 (TP3-TP29).
3. Use a bus wire to short J21-J17 (parallel C51 and C52 for higher current handling capability).
4. Connect the DC-Rail power supply (100 mA minimum current capability) to J17 (+) - J19 (-) and set the 
output to the appropriate voltage level.
5. Connect jumpers, solder bumpers, booster daughter card, and instrumentation as described in Table 5.
Table 5. Connections for Si828x DESAT Short Circuit Test
Testing Configuration Si8281 Direct Drive Si8281 with Current Booster DC
JP9 Connect Pin 1 to Pin 2 Connect Pin 1 to Pin 2
J24 Open Plug into the Current Booster Daughter Card
J26 Close Open
J27 Open Close
J29 Open Open
J30 See below (three vs. four pins SiC) See below (three vs. four pins SiC)
J31 See below (three vs. four pins SiC) See below (three vs. four pins SiC)
J32 Close Open
J33 See below (three vs. four pins SiC) See below (three vs. four pins SiC)
J34 Close Open
J35 Close Open
J1 P/S: Pin 1 to 5 V, Pin 2 to GND P/S: Pin 1 to 5 V, Pin 2 to GND
J16 PWM signal PWM signal
Ch4: IsoVu or HV Diff. probe VGate: J12 (MMCX) or TP26-TP27 VGate: J12 (MMCX) or TP26-TP27
Ch2: HV Differential Probe VDS from TP30(+) to TP31(–) VDS from TP30(+) to TP31(–)
Ch3: T&M Research SDN-414-01 R73: ISense R73: ISense

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6. Set up the function generator connected to SMA J16: 50 output impedance, single pulse 5 Vpp square
wave.
7. Set up the oscilloscope trigger to VGS (Ch4), set scope Ch3 to invert and to 0.01 V per Ampere scale.
8. Setup the voltage scale of the oscilloscope ch2 to the appropriate VDS voltage level.
9. Power up the 12 V power supply that connected to J1.
10.Power up the DC-Rail power supply (see Step 4).
11.Send a single PWM pulse from the function generator and observe the waveforms on the oscilloscope.
Figure 17. Physical Connections for Si8281 DESAT Test Circuit
+ Rail
- Rail
+
R
a
-
R
a
5V
GND
J1
PWM
Signal
Ch4: VGS-Q1
J13 MMCX or
TP27-TP26
Diff-Probe SDN-414-01
Ch3: IDS
TP30-TP32
Diff-Probe
Ch2: VDS Q2 Short