SOLOMON SYSTECH SSD1331 Instruction manual

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1331 Rev 1.2 P 1/68 Nov 2007 Copyright ©2007 Solomon Systech Limited
Advance Information
96RGB x 64 Dot Matrix
OLED/PLED Segment/Common Driver with Controller
SSD1331

Solomon Systech Nov 2007 P 2/68 Rev 1.2 SSD1331
CONTENTS
CONTENTS.........................................................................................................................................................2
1GERENAL INFORMATION .....................................................................................................................6
2FEATURES..............................................................................................................................................6
3ORDERING INFORMATION ...................................................................................................................6
4BLOCK DIAGRAM ..................................................................................................................................7
5SSD1331Z GOLD BUMP DIE PAD ASSIGNMENT................................................................................8
6PIN DESCRIPTION................................................................................................................................12
7FUNCTIONAL BLOCK DESCRIPTIONS..............................................................................................15
7.1 MCU INTERFACE SELECTION .................................................................................................................15
7.1.1 6800-series Parallel Interface ...................................................................................................... 15
7.1.2 8080-series Parallel Interface ...................................................................................................... 16
7.1.3 Serial Interface.............................................................................................................................17
7.2 COMMAND DECODER.............................................................................................................................18
7.3 OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR ............................................................................18
7.3.1 Oscillator ......................................................................................................................................18
7.3.2 FR synchronization ...................................................................................................................... 19
7.4 RESET CIRCUIT ..................................................................................................................................... 19
7.5 GRAPHIC DISPLAY DATA RAM (GDDRAM)............................................................................................20
7.5.1 GDDRAM structure ...................................................................................................................... 20
7.5.2 Data bus to RAM mapping under different input mode ...............................................................20
7.5.3 RAM mapping and Different color depth mode............................................................................21
7.6 GRAY SCALE DECODER .........................................................................................................................21
7.7 SEG /COM DRIVING BLOCK.................................................................................................................. 23
7.8 COMMON AND SEGMENT DRIVERS..........................................................................................................24
7.9 POWER ON AND OFF SEQUENCE...........................................................................................................27
8COMMAND TABLE...............................................................................................................................28
8.1 DATA READ /WRITE ..............................................................................................................................34
9COMMAND DESCRIPTIONS................................................................................................................35
9.1 FUNDAMENTAL COMMAND......................................................................................................................35
9.1.1 Set Column Address (15h)........................................................................................................... 35
9.1.2 Set Row Address (75h)................................................................................................................ 35
9.1.3 Set Contrast for Color A, B, C (81h, 82h, 83h) ...........................................................................36
9.1.4 Master Current Control (87h)....................................................................................................... 36
9.1.5 Set Second Pre-charge Speed for Color A, B, C (8Ah)...............................................................37
9.1.6 Set Re-map & Data Format (A0h) ............................................................................................... 37
9.1.7 Set Display Start Line (A1h)......................................................................................................... 42
9.1.8 Set Display Offset (A2h) .............................................................................................................. 42
9.1.9 Set Display Mode (A4h ~ A7h) ....................................................................................................45
9.1.10 Set Multiplex Ratio (A8h) ............................................................................................................. 45
9.1.11 Dim mode setting (ABh)............................................................................................................... 45
9.1.12 Set Master Configuration (ADh)................................................................................................... 45
9.1.13 Set Display ON/OFF (ACh / AEh / AFh) ...................................................................................... 45
9.1.14 Power Save Mode (B0h).............................................................................................................. 46
9.1.15 Phase 1 and 2 Period Adjustment (B1h) .....................................................................................46
9.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (B3h) .......................................................46
9.1.17 Set Gray Scale Table (B8h) ......................................................................................................... 46
9.1.18 Enable Linear Gray Scale Table (B9h) ........................................................................................47
9.1.19 Set Pre-charge voltage (BBh) ...................................................................................................... 47
9.1.20 Set VCOMH Voltage (BEh)..............................................................................................................47
9.1.21 NOP (BCh, BDh, E3h) ................................................................................................................. 47
9.1.22 Set Command Lock (FDh) ........................................................................................................... 47
9.2 GRAPHIC ACCELERATION COMMAND SET DESCRIPTION.......................................................... 48
9.2.1 Draw Line (21h) ........................................................................................................................... 48
9.2.2 Draw Rectangle (22h) .................................................................................................................. 48

SSD1331 Rev 1.2 P 3/68 Nov 2007 Solomon Systech
9.2.3 Copy (23h) ................................................................................................................................... 49
9.2.4 Dim Window (24h) ....................................................................................................................... 49
9.2.5 Clear Window (25h) ..................................................................................................................... 50
9.2.6 Fill Enable/Disable (26h).............................................................................................................. 50
9.2.7 Continuous Horizontal & Vertical Scrolling Setup (27h) .............................................................. 51
9.2.8 Deactivate scrolling (2Eh) ............................................................................................................ 51
9.2.9 Activate scrolling (2Fh) ................................................................................................................ 51
10 MAXIMUM RATINGS.............................................................................................................................52
11 DC CHARACTERISTICS.......................................................................................................................53
12 AC CHARACTERISTICS.......................................................................................................................54
13 APPLICATION EXAMPLE ....................................................................................................................58
14 PACKAGE OPTIONS............................................................................................................................59
14.1 SSD1331Z DIE TRAY INFORMATION................................................................................................... 59
14.2 SSD1331U1R1 COF PACKAGE DIMENSIONS..............................................................................60
14.3 SSD1331U1R1 COF PACKAGE PIN ASSIGNMENT......................................................................62
14.4 SSD1331U3R1 COF PACKAGE DIMENSIONS..............................................................................64
14.5 SSD1331U3R1 COF PACKAGE PIN ASSIGNMENT......................................................................66

Solomon Systech Nov 2007 P 4/68 Rev 1.2 SSD1331
TABLES
Table 1 - Ordering Information ............................................................................................................................ 6
Table 2 - SSD1331Z Die Pad Coordinates.......................................................................................................... 9
Table 3 - Bus Interface selection .......................................................................................................................12
Table 4 - MCU interface assignment under different bus interface mode......................................................... 15
Table 5 - Control pins of 6800 interface ............................................................................................................15
Table 6 - Control pins of 8080 interface (Form 1) ............................................................................................. 16
Table 7 - Control pins of 8080 interface (Form 2) ............................................................................................. 16
Table 8 - Control pins of Serial interface ........................................................................................................... 17
Table 9 - Data bus usage under different bus width and color depth mode......................................................20
Table 10 - Command Table...............................................................................................................................28
Table 11 - Address increment table (Automatic) ...............................................................................................34
Table 12 - Illustration of different COM output settings ..................................................................................... 39
Table 13 - Example of Set Display Offset and Display Start Line with no Remap............................................43
Table 14 - Example of Set Display Offset and Display Start Line with Remap................................................. 44
Table 15 - Result of Change of Brightness by Dim Window Command............................................................49
Table 16 - Maximum Ratings.............................................................................................................................52
Table 17 - DC Characteristics ...........................................................................................................................53
Table 18 - AC Characteristics............................................................................................................................54
Table 19 - 6800-Series MPU Parallel Interface Timing Characteristics ............................................................55
Table 20 - 8080-Series MPU Parallel Interface Timing Characteristics ............................................................56
Table 21 - Serial Interface Timing Characteristics ............................................................................................ 57
Table 22 - SSD1331U1R1 pin assignment ....................................................................................................... 63
Table 23 - SSD1331U3R1 pin assignment ....................................................................................................... 67

SSD1331 Rev 1.2 P 5/68 Nov 2007 Solomon Systech
FIGURES
Figure 1 - SSD1331 Block Diagram .................................................................................................................... 7
Figure 2 - SSD1331Z Die Drawing ...................................................................................................................... 8
Figure 3 - SSD1331Z Alignment mark dimensions ........................................................................................... 11
Figure 4 - Display data read back procedure - insertion of dummy read .......................................................... 15
Figure 5 – Example of Write procedure in 8080 parallel interface mode ..........................................................16
Figure 6 – Example of Read procedure in 8080 parallel interface mode ..........................................................16
Figure 7 - Display data read back procedure - insertion of dummy read .......................................................... 17
Figure 8 - Write procedure in SPI mode ............................................................................................................17
Figure 9 - Oscillator Circuit ................................................................................................................................18
Figure 10 - 65k Color Depth Graphic Display Data RAM Structure ..................................................................20
Figure 11 - 256-color mode mapping ................................................................................................................ 21
Figure 12 - Relation between GDRAM content and gray scale table entry for three colors in 65K color mode21
Figure 13 - Illustration of relation between graphic display RAM value and gray scale control........................22
Figure 14 - IREF Current Setting by Resistor Value............................................................................................23
Figure 15 - ISEG current vs VCC setting at constant IREF, Contrast = FFh ...........................................................23
Figure 16 - Segment and Common Driver Block Diagram ................................................................................ 24
Figure 17 - Segment and Common Driver Signal Waveform ............................................................................ 25
Figure 18 - Gray Scale Control by PWM in Segment........................................................................................ 26
Figure 19 : The Power ON sequence ................................................................................................................ 27
Figure 20 : The Power OFF sequence ..............................................................................................................27
Figure 21 - Example of Column and Row Address Pointer Movement.............................................................35
Figure 22 - Effect of setting the second pre-charge under different speeds .....................................................37
Figure 23 - Address Pointer Movement of Horizontal Address Increment Mode..............................................37
Figure 24 - Address Pointer Movement of Vertical Address Increment Mode .................................................. 37
Figure 25 - Example of Column Address Mapping............................................................................................ 38
Figure 26 - COM Pins Hardware Configuration (MUX ratio: 64) ....................................................................... 40
Figure 27 – Transition between different modes ...............................................................................................45
Figure 28 - Typical Oscillator frequency adjustment by B3 command (VDD =2.7V) ..........................................46
Figure 29 - Example of gamma correction by gray scale table setting .............................................................47
Figure 30 – Typical Pre-charge voltage level setting by command BBh...........................................................47
Figure 31 - Example of Draw Line Command ................................................................................................... 48
Figure 32 - Example of Draw Rectangle Command.......................................................................................... 48
Figure 33 - Example of Copy Command ...........................................................................................................49
Figure 34 - Example of Copy + Clear = Move Command ................................................................................ 50
Figure 35 - Examples of Continuous Horizontal and Vertical Scrolling command setup .................................. 51
Figure 36 - 6800-series parallel interface characteristics.................................................................................. 55
Figure 37 - 8080-series parallel interface characteristics (Form 1)................................................................... 56
Figure 38 - 8080-series parallel interface characteristics (Form 2)................................................................... 56
Figure 39 - Serial interface characteristics ........................................................................................................ 57
Figure 40 - Application Example for SSD1331U1R1......................................................................................... 58
Figure 41 - Die Tray Information........................................................................................................................ 59
Figure 42 - SSD1331U1R1 outline drawing ...................................................................................................... 60
Figure 43 - SSD1331U1R1 pin assignment drawing......................................................................................... 62
Figure 44 - SSD1331U3R1 outline drawing ...................................................................................................... 64
Figure 45 - SSD1331U3R1 pin assignment drawing......................................................................................... 66

Solomon Systech Nov 2007 P 6/68 Rev 1.2 SSD1331
1 GERENAL INFORMATION
The SSD1331 is a single chip CMOS OLED/PLED driver with 288 segments and 64 commons output,
supporting up to 96RGB x 64 dot matrix display. This chip is designed for Common Cathode type
OLED/PLED panel.
The SSD1331 had embedded Graphic Display Data RAM (GDDRAM). It supports with 8, 9, 16 bits 8080 /
6800 parallel interface as well as serial peripheral interface. It has 256-step contrast and 65K color control.
To facilitate communication between lower operating voltages MCU, it has separate power for I/O interface
logic. SSD1331 is suitable for mobile phones, MP3, MP4 and other industrial devices.
2 FEATURES
Resolution: 96RGB x 64 dot matrix panel
65k color depth support by embedded 96x64x16 bit GDDRAM display buffer
Power supply:
oVDD = 2.4V to 3.5V for IC logic
oVCC = 8.0V to 18.0V for Panel driving
oVDDIO = 1.6V to VDD for MCU interface
Segment maximum source current: 200uA
Common maximum sink current: 60mA
256 step contrast control for the each color component plus 16 step master current control
Pin selectable MCU interface
o8/9/16 bits 6800-series parallel Interface
o8/9/16 bits 8080-series Parallel Interface
oSerial Peripheral Interface
Color swapping function (RGB <-> BGR)
Graphic Accelerating Command (GAC) set with Continuous Horizontal, Vertical and Diagonal
Scrolling
Programmable Frame Rate
Wide range of operating temperature: -40 to 85 °C
3 ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part Number SEG COM Package Form Reference Remark
SSD1331Z 96x3 64 COG Page 8, 59 •Min SEG pad pitch: 40.2 um
•Min COM pad pitch: 41.8 um
SSD1331U1R1 96x3 64 COF Page 60
•35mm film, 5 sprocket hole
•8 bit or SPI interface
•Output lead pitch: 0.06mm for SEG,
0.09mm for COM
SSD1331U3R1 96x3 64 COF Page 64
•35mm film, 4 sprocket hole
•8 bit or SPI interface
•Output lead pitch: 0.06mm for SEG,
0.09mm for COM

SSD1331 Rev 1.2 P 7/68 Nov 2007 Solomon Systech
4 BLOCK DIAGRAM
Figure 1 - SSD1331 Block Diagram
MCU Interface
GDDRAM
Gray Scale Decoder
Common Drivers Segment Drivers Common Drivers
SEG/COM Driving block
Oscillator
Display Timing
Generator
Command Decoder
(Even) (odd)
RES#
CS#
D/C#
E(RD#)
R/W #(WR#)
BS[3:0]
D[15:0]
V
CC
V
DD
V
DDIO
V
SS
V
LSS
CL
CLS
FR
I
REF
V
COMH
COM0
COM2
COM4
.
.
.
COM58
COM60
COM62
COM63
COM61
COM59
.
.
.
COM5
COM3
COM1
SC95
SB95
SA95
SC94
SB94
SA94
SC93
SB93
SA93
.
.
.
SC2
SB2
SA2
SC1
SB1
SA1
SC0
SB0
SA0
GPIO0
GPIO1
AV
DD

Solomon Systech Nov 2007 P 8/68 Rev 1.2 SSD1331
5 SSD1331Z GOLD BUMP DIE PAD ASSIGNMENT
Figure 2 - SSD1331Z Die Drawing
Pad 1
Die size 13.1mm x 1.58mm
Die height 457um
Min I/O pad pitch 76.2 um
Min SEG pad pitch 40.2 um
Min COM pad pitch 41.8 um
Bump height Nominal 15um
Bump size
Pad 1-163 50um x 72um
Pad164-195, 486-517 72um x 28um
Pad 196-485 28um x 72um
Alignment mark
+ shape (5446.0, -402.0) 75um x 75um
+ shape (-5446.0, -402.0) 75um x 75um
SSD1331Z
Pad 1,2,3,…->163
Gold Bumps face up
X
Y

SSD1331 Rev 1.2 P 9/68 Nov 2007 Solomon Systech
Table 2 - SSD1331Z Die Pad Coordinates
Pad no. PadName X-Axis Y-Axis Pad no. Pad Name X-Axis Y-Axis Pad no. Pad Name X-Axis Y-Axis
1 NC -6319.4 -712.5 81 BS2 -76.2 -712.5 161 NC 6167.0 -712.5
2 NC -6243.2 -712.5 82 VSS 0.0 -712.5 162 NC 6243.2 -712.5
3 NC -6167.0 -712.5 83 BS3 76.2 -712.5 163 NC 6319.4 -712.5
4 NC -6090.8 -712.5 84 VDDIO 152.4 -712.5 164 COM 31 6420.1 -647.9
5 NC -6014.6 -712.5 85 VDDIO 228.6 -712.5 165 COM 30 6420.1 -606.1
6 NC -5791.2 -712.5 86 IREF 304.8 -712.5 166 COM 29 6420.1 -564.3
7 VCC -5715.0 -712.5 87 VCC 381.0 -712.5 167 COM 28 6420.1 -522.5
8 VCC -5638.8 -712.5 88 VCC 457.2 -712.5 168 COM 27 6420.1 -480.7
9 VCC -5562.6 -712.5 89 VCC 533.4 -712.5 169 COM 26 6420.1 -438.9
10 VLSS -5486.4 -712.5 90 FR 609.6 -712.5 170 COM 25 6420.1 -397.1
11 VLSS -5410.2 -712.5 91 CL 685.8 -712.5 171 COM 24 6420.1 -355.3
12 VLSS -5334.0 -712.5 92 VSS 762.0 -712.5 172 COM 23 6420.1 -313.5
13 VLSS -5257.8 -712.5 93 CLS 838.2 -712.5 173 COM 22 6420.1 -271.7
14 VLSS -5181.6 -712.5 94 VDDIO 914.4 -712.5 174 COM 21 6420.1 -229.9
15 VLSS -5105.4 -712.5 95 VDDIO 990.6 -712.5 175 COM 20 6420.1 -188.1
16 VLSS -5029.2 -712.5 96 VDDIO 1066.8 -712.5 176 COM 19 6420.1 -146.3
17 VLSS -4953.0 -712.5 97 VDDIO 1143.0 -712.5 177 COM 18 6420.1 -104.5
18 VLSS -4876.8 -712.5 98 CSB 1219.2 -712.5 178 COM 17 6420.1 -62.7
19 VLSS -4800.6 -712.5 99 VSS 1295.4 -712.5 179 COM 16 6420.1 -20.9
20 VLSS -4724.4 -712.5 100 RESB 1371.6 -712.5 180 COM 15 6420.1 20.9
21 VLSS -4648.2 -712.5 101 VDDIO 1447.8 -712.5 181 COM 14 6420.1 62.7
22 VSS -4572.0 -712.5 102 VDDIO 1524.0 -712.5 182 COM 13 6420.1 104.5
23 VSS -4495.8 -712.5 103 DC 1600.2 -712.5 183 COM 12 6420.1 146.3
2 4 V S S - 4 4 19 . 6 - 7 12 . 5 10 4 V S S 16 7 6 . 4 - 7 12 . 5 18 4 C O M 11 6 4 2 0 . 1 18 8 . 1
25 BGGND -4343.4 -712.5 105 RW 1752.6 -712.5 185 COM 10 6420.1 229.9
26 VDD -4267.2 -712.5 106 E 1828.8 -712.5 186 COM 9 6420.1 271.7
27 VDD -4191.0 -712.5 107 VDDIO 1905.0 -712.5 187 COM 8 6420.1 313.5
28 VDD -4114.8 -712.5 108 VDD 1981.2 -712.5 188 COM 7 6420.1 355.3
29 VDDIO -4038.6 -712.5 109 VDD 2057.4 -712.5 189 COM 6 6420.1 397.1
30 VDDIO -3962.4 -712.5 110 VDD 2133.6 -712.5 190 COM 5 6420.1 438.9
31 VDDIO -3886.2 -712.5 111 D0 2209.8 -712.5 191 COM 4 6420.1 480.7
32 VCC -3810.0 -712.5 112 D1 2286.0 -712.5 192 COM 3 6420.1 522.5
33 VCC -3733.8 -712.5 113 D2 2362.2 -712.5 193 COM 2 6420.1 564.3
34 VCC -3657.6 -712.5 114 D3 2438.4 -712.5 194 COM 1 6420.1 606.1
35 VSSB -3581.4 -712.5 115 D4 2514.6 -712.5 195 COM 0 6420.1 647.9
36 VSSB -3505.2 -712.5 116 D5 2590.8 -712.5 196 VLSS 5908.5 643.6
37 VSSB -3429.0 -712.5 117 D6 2667.0 -712.5 197 SA 0 5828.1 643.6
38 GDR -3352.8 -712.5 118 D7 2743.2 -712.5 198 SB0 5787.9 643.6
39 GDR -3276.6 -712.5 119 D8 2819.4 -712.5 199 SC0 5747.7 643.6
40 GDR -3200.4 -712.5 120 D9 2895.6 -712.5 200 SA 1 5707.5 643.6
41 GDR -3124.2 -712.5 121 D10 2971.8 -712.5 201 SB 1 5667.3 643.6
42 GDR -3048.0 -712.5 122 D11 3048.0 -712.5 202 SC1 5627.1 643.6
43 GDR -2971.8 -712.5 123 D12 3124.2 -712.5 203 SA 2 5586.9 643.6
44 GDR -2895.6 -712.5 124 D13 3200.4 -712.5 204 SB 2 5546.7 643.6
45 VDDB -2819.4 -712.5 125 D14 3276.6 -712.5 205 SC2 5506.5 643.6
46 VDDB -2743.2 -712.5 126 D15 3352.8 -712.5 206 SA 3 5466.3 643.6
47 VDDB -2667.0 -712.5 127 VSS 3429.0 -712.5 207 SB 3 5426.1 643.6
48 VDDB -2590.8 -712.5 128 TR11 3505.2 -712.5 208 SC3 5385.9 643.6
49 VDDB -2514.6 -712.5 129 TR10 3581.4 -712.5 209 SA4 5345.7 643.6
50 VDD -2438.4 -712.5 130 TR9 3657.6 -712.5 210 SB 4 5305.5 643.6
51 VDDIO -2362.2 -712.5 131 TR8 3733.8 -712.5 211 SC4 5265.3 643.6
52 VDD -2286.0 -712.5 132 TR7 3810.0 -712.5 212 SA5 5225.1 643.6
53 VDD -2209.8 -712.5 133 TR6 3886.2 -712.5 213 SB5 5184.9 643.6
54 FB -2133.6 -712.5 134 VSS 3962.4 -712.5 214 SC5 5144.7 643.6
55 VBREF -2057.4 -712.5 135 TR5 4038.6 -712.5 215 SA6 5104.5 643.6
56 VSS -1981.2 -712.5 136 TR4 4114.8 -712.5 216 SB 6 5064.3 643.6
57 GPIO0 -1905.0 -712.5 137 TR3 4191.0 -712.5 217 SC6 5024.1 643.6
58 GPIO1 -1828.8 -712.5 138 TR2 4267.2 -712.5 218 SA 7 4983.9 643.6
59 VDDIO -1752.6 -712.5 139 TR1 4343.4 -712.5 219 SB7 4943.7 643.6
60 VCIR -1676.4 -712.5 140 TR0 4419.6 -712.5 220 SC7 4903.5 643.6
61 VCIR -1600.2 -712.5 141 VSS 4495.8 -712.5 221 SA8 4863.3 643.6
62 VCIR -1524.0 -712.5 142 VCOM H 4572.0 -712.5 222 SB8 4823.1 643.6
63 VCIR -1447.8 -712.5 143 VCOM H 4648.2 -712.5 223 SC8 4782.9 643.6
64 VCIR -1371.6 -712.5 144 VCOM H 4724.4 -712.5 224 SA9 4742.7 643.6
65 VDD -1295.4 -712.5 145 VDD 4800.6 -712.5 225 SB 9 4702.5 643.6
66 VDD -1219.2 -712.5 146 VDD 4876.8 -712.5 226 SC9 4662.3 643.6
67 VDD -1143.0 -712.5 147 VDDIO 4953.0 -712.5 227 SA10 4622.1 643.6
68 VDD -1066.8 -712.5 148 VDDIO 5029.2 -712.5 228 SB10 4581.9 643.6
69 AVDD -990.6 -712.5 149 VCC 5105.4 -712.5 229 SC10 4541.7 643.6
70 AVDD -914.4 -712.5 150 VCC 5181.6 -712.5 230 SA 11 4501.5 643.6
71 VDDIO -838.2 -712.5 151 VCC 5257.8 -712.5 231 SB11 4461.3 643.6
72 VDDIO -762.0 -712.5 152 VCC 5334.0 -712.5 232 SC11 4421.1 643.6
73 VDDIO -685.8 -712.5 153 VCC 5410.2 -712.5 233 SA12 4380.9 643.6
74 VDDIO -609.6 -712.5 154 VCC 5486.4 -712.5 234 SB 12 4340.7 643.6
75 VDDIO -533.4 -712.5 155 NC 5562.6 -712.5 235 SC12 4300.5 643.6
76 VDDIO -457.2 -712.5 156 VLSS 5638.8 -712.5 236 SA 13 4260.3 643.6
77 BS0 -381.0 -712.5 157 VLSS 5715.0 -712.5 237 SB13 4220.1 643.6
78 VSS -304.8 -712.5 158 NC 5791.2 -712.5 238 SC13 4179.9 643.6
79 BS1 -228.6 -712.5 159 NC 6014.6 -712.5 239 SA14 4139.7 643.6
80 VDDIO -152.4 -712.5 160 NC 6090.8 -712.5 240 SB14 4099.5 643.6

Solomon Systech Nov 2007 P 10/68 Rev 1.2 SSD1331
Pad no. Pad Name X-Axis Y-Axis Pad no. Pad Name X-Axis Y-Axis Pad no. P ad Name X-Axis Y-Axis
241 SC14 4059.3 643.6 321 SB41 843.3 643.6 401 SA 68 -2493.3 643.6
242 SA15 4019.1 643.6 322 SC41 803.1 643.6 402 SB 68 -2533.5 643.6
243 SB 15 3978.9 643.6 323 SA 42 762.9 643.6 403 SC68 -2573.7 643.6
244 SC15 3938.7 643.6 324 SB 42 722.7 643.6 404 SA 69 -2613.9 643.6
245 SA 16 3898.5 643.6 325 SC42 682.5 643.6 405 SB69 -2654.1 643.6
246 SB 16 3858.3 643.6 326 SA 43 642.3 643.6 406 SC69 -2694.3 643.6
247 SC16 3818.1 643.6 327 SB 43 602.1 643.6 407 SA 70 -2734.5 643.6
248 SA 17 3777.9 643.6 328 SC43 561.9 643.6 408 SB70 -2774.7 643.6
249 SB 17 3737.7 643.6 329 SA 44 521.7 643.6 409 SC70 -2814.9 643.6
250 SC17 3697.5 643.6 330 SB 44 481.5 643.6 410 SA 71 -2855.1 643.6
251 SA 18 3657.3 643.6 331 SC44 441.3 643.6 411 SB 71 -2895.3 643.6
252 SB 18 3617.1 643.6 332 SA 45 401.1 643.6 412 SC71 -2935.5 643.6
253 SC18 3576.9 643.6 333 SB 45 360.9 643.6 413 SA72 -2975.7 643.6
254 SA 19 3536.7 643.6 334 SC45 320.7 643.6 414 SB72 -3015.9 643.6
255 SB 19 3496.5 643.6 335 SA 46 280.5 643.6 415 SC72 -3056.1 643.6
256 SC19 3456.3 643.6 336 SB 46 240.3 643.6 416 SA73 -3096.3 643.6
257 SA 20 3416.1 643.6 337 SC46 200.1 643.6 417 SB73 -3136.5 643.6
258 SB 20 3375.9 643.6 338 SA 47 159.9 643.6 418 SC73 -3176.7 643.6
259 SC20 3335.7 643.6 339 SB 47 119.7 643.6 419 SA74 -3216.9 643.6
260 SA 21 3295.5 643.6 340 SC47 79.5 643.6 420 SB 74 -3257.1 643.6
261 SB 21 3255.3 643.6 341 SA48 -81.3 643.6 421 SC74 -3297.3 643.6
262 SC21 3215.1 643.6 342 SB 48 -121.5 643.6 422 SA 75 -3337.5 643.6
263 SA22 3174.9 643.6 343 SC48 -161.7 643.6 423 SB75 -3377.7 643.6
264 SB22 3134.7 643.6 344 SA49 -201.9 643.6 424 SC75 -3417.9 643.6
265 SC22 3094.5 643.6 345 SB 49 -242.1 643.6 425 SA76 -3458.1 643.6
266 SA23 3054.3 643.6 346 SC49 -282.3 643.6 426 SB 76 -3498.3 643.6
267 SB23 3014.1 643.6 347 SA 50 -322.5 643.6 427 SC76 -3538.5 643.6
268 SC23 2973.9 643.6 348 SB 50 -362.7 643.6 428 SA 77 -3578.7 643.6
269 SA24 2933.7 643.6 349 SC50 -402.9 643.6 429 SB 77 -3618.9 643.6
270 SB 24 2893.5 643.6 350 SA51 -443.1 643.6 430 SC77 -3659.1 643.6
271 SC24 2853.3 643.6 351 SB 51 -483.3 643.6 431 SA78 -3699.3 643.6
272 SA 25 2813.1 643.6 352 SC51 -523.5 643.6 432 SB78 -3739.5 643.6
273 SB25 2772.9 643.6 353 SA52 -563.7 643.6 433 SC78 -3779.7 643.6
274 SC25 2732.7 643.6 354 SB 52 -603.9 643.6 434 SA 79 -3819.9 643.6
275 SA 26 2692.5 643.6 355 SC52 -644.1 643.6 435 SB79 -3860.1 643.6
276 SB26 2652.3 643.6 356 SA53 -684.3 643.6 436 SC79 -3900.3 643.6
277 SC26 2612.1 643.6 357 SB 53 -724.5 643.6 437 SA80 -3940.5 643.6
278 SA27 2571.9 643.6 358 SC53 -764.7 643.6 438 SB 80 -3980.7 643.6
279 SB27 2531.7 643.6 359 SA54 -804.9 643.6 439 SC80 -4020.9 643.6
280 SC27 2491.5 643.6 360 SB 54 -845.1 643.6 440 SA 81 -4061.1 643.6
281 SA 28 2451.3 643.6 361 SC54 -885.3 643.6 441 SB81 -4101.3 643.6
282 SB28 2411.1 643.6 362 SA55 -925.5 643.6 442 SC81 -4141.5 643.6
283 SC28 2370.9 643.6 363 SB 55 -965.7 643.6 443 SA 82 -4181.7 643.6
284 SA 29 2330.7 643.6 364 SC55 -1005.9 643.6 444 SB 82 -4221.9 643.6
285 SB 29 2290.5 643.6 365 SA 56 -1046.1 643.6 445 SC82 -4262.1 643.6
286 SC29 2250.3 643.6 366 SB 56 -1086.3 643.6 446 SA 83 -4302.3 643.6
287 SA30 2210.1 643.6 367 SC56 -1126.5 643.6 447 SB 83 -4342.5 643.6
288 SB30 2169.9 643.6 368 SA57 -1166.7 643.6 448 SC83 -4382.7 643.6
289 SC30 2129.7 643.6 369 SB 57 -1206.9 643.6 449 SA 84 -4422.9 643.6
290 SA 31 2089.5 643.6 370 SC57 -1247.1 643.6 450 SB 84 -4463.1 643.6
291 SB 31 2049.3 643.6 371 SA58 -1287.3 643.6 451 SC84 -4503.3 643.6
292 SC31 2009.1 643.6 372 SB 58 -1327.5 643.6 452 SA 85 -4543.5 643.6
293 SA32 1968.9 643.6 373 SC58 -1367.7 643.6 453 SB 85 -4583.7 643.6
294 SB32 1928.7 643.6 374 SA59 -1407.9 643.6 454 SC85 -4623.9 643.6
295 SC32 1888.5 643.6 375 SB 59 -1448.1 643.6 455 SA 86 -4664.1 643.6
296 SA33 1848.3 643.6 376 SC59 -1488.3 643.6 456 SB 86 -4704.3 643.6
297 SB 33 1808.1 643.6 377 SA60 -1528.5 643.6 457 SC86 -4744.5 643.6
298 SC33 1767.9 643.6 378 SB 60 -1568.7 643.6 458 SA 87 -4784.7 643.6
299 SA34 1727.7 643.6 379 SC60 -1608.9 643.6 459 SB 87 -4824.9 643.6
300 SB 34 1687.5 643.6 380 SA61 -1649.1 643.6 460 SC87 -4865.1 643.6
301 SC34 1647.3 643.6 381 SB 61 -1689.3 643.6 461 SA 88 -4905.3 643.6
302 SA 35 1607.1 643.6 382 SC61 -1729.5 643.6 462 SB88 -4945.5 643.6
303 SB35 1566.9 643.6 383 SA62 -1769.7 643.6 463 SC88 -4985.7 643.6
304 SC35 1526.7 643.6 384 SB 62 -1809.9 643.6 464 SA 89 -5025.9 643.6
305 SA36 1486.5 643.6 385 SC62 -1850.1 643.6 465 SB 89 -5066.1 643.6
306 SB36 1446.3 643.6 386 SA63 -1890.3 643.6 466 SC89 -5106.3 643.6
307 SC36 1406.1 643.6 387 SB63 -1930.5 643.6 467 SA 90 -5146.5 643.6
308 SA37 1365.9 643.6 388 SC63 -1970.7 643.6 468 SB 90 -5186.7 643.6
309 SB37 1325.7 643.6 389 SA64 -2010.9 643.6 469 SC90 -5226.9 643.6
310 SC37 1285.5 643.6 390 SB 64 -2051.1 643.6 470 SA91 -5267.1 643.6
311 SA 38 1245.3 643.6 391 SC64 -2091.3 643.6 471 SB 91 -5307.3 643.6
312 SB38 1205.1 643.6 392 SA 65 -2131.5 643.6 472 SC91 -5347.5 643.6
313 SC38 1164.9 643.6 393 SB65 -2171.7 643.6 473 SA 92 -5387.7 643.6
314 SA39 1124.7 643.6 394 SC65 -2211.9 643.6 474 SB 92 -5427.9 643.6
315 SB39 1084.5 643.6 395 SA 66 -2252.1 643.6 475 SC92 -5468.1 643.6
316 SC39 1044.3 643.6 396 SB 66 -2292.3 643.6 476 SA 93 -5508.3 643.6
317 SA40 1004.1 643.6 397 SC66 -2332.5 643.6 477 SB 93 -5548.5 643.6
318 SB40 963.9 643.6 398 SA 67 -2372.7 643.6 478 SC93 -5588.7 643.6
319 SC40 923.7 643.6 399 SB 67 -2412.9 643.6 479 SA 94 -5628.9 643.6
320 SA 41 883.5 643.6 400 SC67 -2453.1 643.6 480 SB 94 -5669.1 643.6

SSD1331 Rev 1.2 P 11/68 Nov 2007 Solomon Systech
Figure 3 - SSD1331Z Alignment mark dimensions
Pad no. Pad Name X-Axis Y-Axis
481 SC94 -5709.3 643.6
482 SA95 -5749.5 643.6
483 SB95 -5789.7 643.6
484 SC95 -5829.9 643.6
485 VLSS -5910.3 643.6
486 COM 32 -6420.1 647.9
487 COM 33 -6420.1 606.1
488 COM 34 -6420.1 564.3
489 COM 35 -6420.1 522.5
490 COM 36 -6420.1 480.7
491 COM 37 -6420.1 438.9
492 COM 38 -6420.1 397.1
493 COM 39 -6420.1 355.3
494 COM 40 -6420.1 313.5
495 COM 41 -6420.1 271.7
496 COM 42 -6420.1 229.9
497 COM 43 -6420.1 188.1
498 COM 44 -6420.1 146.3
499 COM 45 -6420.1 104.5
500 COM 46 -6420.1 62.7
501 COM 47 -6420.1 20.9
502 COM 48 -6420.1 -20.9
503 COM 49 -6420.1 -62.7
504 COM 50 -6420.1 -104.5
505 COM 51 -6420.1 -146.3
506 COM 52 -6420.1 -188.1
507 COM 53 -6420.1 -229.9
508 COM 54 -6420.1 -271.7
509 COM 55 -6420.1 -313.5
510 COM 56 -6420.1 -355.3
511 COM 57 -6420.1 -397.1
512 COM 58 -6420.1 -438.9
513 COM 59 -6420.1 -480.7
514 COM 60 -6420.1 -522.5
515 COM 61 -6420.1 -564.3
516 COM 62 -6420.1 -606.1
517 COM 63 -6420.1 -647.9
+ shape
Unit in um

Solomon Systech Nov 2007 P 12/68 Rev 1.2 SSD1331
6 PIN DESCRIPTION
Pin Name Pin Type Description
VDD Power Power supply pin for core VDD
AVDD Power Analog power supply. It must be connected to VDD during operation.
VDDIO Power Power supply for interface logic level. It should be match with the MCU interface
voltage level.
VDDIO must always be equal or lower than VDD.
VCC Power Power supply for panel driving voltage. This is also the most positive power
voltage supply pin.
VSS Power Ground pin
VLSS Power Analog system ground pin.
VCOMH O COM signal deselected voltage level.
A capacitor should be connected between this pin and VSS.
BGGND Power Connect to Ground
VDDB Power Reserved pin. It should be connect to VDD externally.
VSSB Power Reserved pin. It should be connected to VSS externally.
GDR O Reserved pin. Keep NC (i.e. no connection).
FB I Reserved pin. Keep NC (i.e. no connection).
VBREF O Reserved pin. Keep NC (i.e. no connection).
GPIO0 I/O Reserved pin. Keep NC (i.e. no connection).
GPIO1 I/O Reserved pin. Keep NC (i.e. no connection).
VCIR O Reserved pin. Keep NC (i.e. no connection).
BS[3:0] I MCU bus interface selection pins.
Table 3 - Bus Interface selection
BS[3:0] Bus Interface Selection
0000 SPI
0100 8-bit 6800 parallel
0101 16-bit 6800 parallel
0110 8-bit 8080 parallel
0111 16-bit 8080 parallel
1100 9-bit 6800 parallel
1110 9-bit 8080 parallel
IREF I This pin is the segment output current reference pin.
A resistor should be connected between this pin and VSS to maintain the IREF
current at 10uA. Please refer to Figure 14 for the details formula of resistor
value.

SSD1331 Rev 1.2 P 13/68 Nov 2007 Solomon Systech
Pin Name Pin Type Description
FR O This pin outputs RAM write synchronization signal. Proper timing between MCU
data writing and frame display timing can be achieve to prevent tearing effect.
Keep NC if not used.
Refer to section 7.3.2 for details usage.
CL I This is external clock input pin.
When internal clock is enabled (i.e. HIGH in CLS pin), this pin is not used and
should be connected to VSS. When internal clock is disabled (i.e. LOW in CLS
pin), this pin is the external clock source input pin.
CLS I Internal clock selection pin.
When this pin is pulled high (i.e. connect to VDDIO), internal oscillator is enable
(normal operation).
When this pin is pulled low, an external clock signal should be connected to CL.
CS# I This pin is the chip select input connecting to the MCU.
RES# I This pin is reset signal input.
When the pin is low, initialization of the chip is executed.
Keep this pin high (i.e. connect to VDDIO) during normal operation.
D/C# I This pin is Data/Command control pin connecting to the MCU.
When the pin is pulled high (i.e. connect to VDDIO), the data at D[15:0]will be
interpreted as data.
When the pin is pulled low, the data at D[15:0] will be interpreted as command.
R/W# (WR#) I This pin is read / write control input pin connecting to the MCU interface.
When interfacing to a 6800-series microprocessor, this pin will be used as
Read/Write (R/W#) selection input. Read mode will be carried out when this pin
is pulled high (i.e. connect to VDDIO) and write mode when low.
When 8080 interface mode is selected, this pin will be the Write (WR#) input.
Data write operation is initiated when this pin is pulled low and the chip is
selected.
When serial interface is selected, this pin R/W#(WR#) must be connected to VSS.
E (RD#) I This pin is MCU interface input.
When interfacing to a 6800-series microprocessor, this pin will be used as the
Enable (E) signal. Read/write operation is initiated when this pin is pulled high
(i.e. connect to VDDIO) and the chip is selected.
When connecting to an 8080-microprocessor, this pin receives the Read (RD#)
signal. Read operation is initiated when this pin is pulled low and the chip is
selected.
When serial interface is selected, this pin E(RD#) must be connected to VSS.
D[15:0] I/O These pins are bi-directional data bus connecting to the MCU data bus.
Unused pins are recommended to tie low. (Except for D2 pin in serial mode)
Refer to Section 7.1 for different bus interface connection.
SA[95:0]
SB[95:0]
SC[95:0]
O These pins provide the OLED segment driving signals. These pins are in high
impedance state when display is OFF by command Set Display OFF.
These 288 segment pins are divided into 3 groups, SA, SB and SC. Each group
can have different color settings for color A, B and C.

Solomon Systech Nov 2007 P 14/68 Rev 1.2 SSD1331
Pin Name Pin Type Description
COM[63:0] I/O These pins provide the Common switch signals to the OLED panel. These pins
are in high impedance state when display is OFF by command Set Display OFF.
TR[11:0] I Testing reserved pins. These pins should be kept float.
NC NC Dummy pins. These pins should be kept float and should not be connected to
any other signal pins nor any electrical signal. Do not connect NC pins together.

SSD1331 Rev 1.2 P 15/68 Nov 2007 Solomon Systech
7 FUNCTIONAL BLOCK DESCRIPTIONS
7.1 MCU Interface Selection
SSD1331 MCU interface consist of 16 data pin and 5 control pins. The pin assignment at different interface
mode is summarized in Table 4. Different MCU mode can be set by hardware selection on BS[3:0] pins (refer
to Table 3 for BS pins setting)
Table 4 - MCU interface assignment under different bus interface mode
                    
     
     
     
     
     
     
   SCLK   
Tie LowTie Low
Tie Low
Tie Low



 


Tie Low
Tie Low 

7.1.1 6800-series Parallel Interface
A low in R/W# indicates WRITE operation and high in R/W# indicates READ operation.
A low in D/C# indicates COMMAND read/write and high in D/C# indicates DATA read/write.
The E input serves as data latch signal while CS# is low. Data is latched at the falling edge of E signal.
Table 5 - Control pins of 6800 interface
Function E R/W# CS# D/C#
Write command ↓LLL
Read status ↓HLL
Write data ↓LLH
Read data ↓HLH
Note
(1) ↓stands for falling edge of signal
(2) H stands for high in signal
(3) L stands for low in signal
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 4
Figure 4 - Display data read back procedure - insertion of dummy read
Nnn+1 n+2
R/W#
E
Databus
Write column
address Read 1st data
Dumm
y
read Read 2nd data Read 3rd data

Solomon Systech Nov 2007 P 16/68 Rev 1.2 SSD1331
7.1.2 8080-series Parallel Interface
A low in D/C# indicates COMMAND read/write and high in D/C# indicates DATA read/write.
A rising edge of RD# input serves as a data READ latch signal while CS# is kept low.
A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept low.
Figure 5 – Example of Write procedure in 8080 parallel interface mode
CS#
WR#
D[7:0]
D/C#
RD#
high
low
Figure 6 – Example of Read procedure in 8080 parallel interface mode
CS#
WR#
D[7:0]
D/C#
RD#
high
low
Table 6 - Control pins of 8080 interface (Form 1)
Function RD# WR# CS# D/C#
Write command H
↑
LL
Read status
↑
HLL
Write data H
↑
LH
Read data
↑
HLH
Note
(1) ↑stands for rising edge of signal
(2) H stands for high in signal
(3) L stands for low in signal
(4) Refer to Figure 37 for Form 1 8080-Series MPU Parallel Interface Timing Characteristics
Alternatively, E(RD#) and R/W#(WR#) can be keep stable while CS# is serve as the data/command latch
signal.
Table 7 - Control pins of 8080 interface (Form 2)
Function RD# WR# CS# D/C#
Write command H L
↑
L
Read status LH
↑
L
Write data H L
↑
H
Read data LH
↑
H
Note
(1) ↑stands for rising edge of signal
(2) H stands for high in signal
(3) L stands for low in signal
(4) Refer to Figure 38 for Form 2 8080-Series MPU Parallel Interface Timing Characteristics

SSD1331 Rev 1.2 P 17/68 Nov 2007 Solomon Systech
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 7.
Figure 7 - Display data read back procedure - insertion of dummy read
N n n+1 n+2
WR#
RD#
Databus
Write column
address Read 1st dataDummy read Read 2nd data Read 3rd data
7.1.3 Serial Interface
The serial interface consists of serial clock SCLK (D0), serial data SDIN (D1), D/C# and CS#. SCLK is shifted
into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6… D0. D/C# is sampled on
every eighth clock and the data byte in the shift register is written to the Display Data RAM or command
register in the same clock.
Under serial mode, only write operations are allowed.
Table 8 - Control pins of Serial interface
Function E R/W# CS# D/C#
Write command Tie low Tie low L L
Write data Tie low Tie low L H
Figure 8 - Write procedure in SPI mode
D7 D6 D5 D4 D3 D2 D1 D0
SCLK(D0)
SDIN(D1)
DB1 DB2 DBn
CS#
D/C#
SDIN/
SCLK

Solomon Systech Nov 2007 P 18/68 Rev 1.2 SSD1331
7.2 Command Decoder
This module determines whether the input should be interpreted as data or command based upon the input of
the D/C# pin.
If D/C# pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it is low, the inputs at D0-D15
are interpreted as a Command and it will be decoded and be written to the corresponding command register.
7.3 Oscillator Circuit and Display Time Generator
7.3.1 Oscillator
Divider
Internal
Oscillator
Fosc
M
U
X
CL
CLK DCLK
Display
Clock
CLS
Figure 9 - Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 9). The operation clock (CLK) can be
generated either from internal oscillator or external source CL pin by CLS pin. If CLS pin is high, internal
oscillator is selected. If CLS pin is low, external clock from CL pin will be used for CLK. The frequency of
internal oscillator FOSC can be programmed by command B3h (Set oscillator frequency).
The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D” can
be programmed from 1 to 16 by command B3h.
DCLK = FOSC / D
The frame frequency of display is determined by the following formula.
MuxofNo.KD F
Fosc
FRM ××
=
where
•D stands for clock divide ratio. It is set by command B3h A[3:0]. The divide ratio has the range from
1 to 16.
•K is the number of display clocks per row. The value is derived by
K = Phase 1 period + Phase 2 period + PW63 (longest current drive pulse width)
= 4 + 7 + 125 = 136 at reset
•Number of multiplex ratio is set by command A8h. The reset value is 64
•F
OSC is the oscillator frequency. It can be adjusted by command B3h A[7:4]

SSD1331 Rev 1.2 P 19/68 Nov 2007 Solomon Systech
7.3.2 FR synchronization
FR synchronization signal can be used to prevent tearing effect.
The starting time to write a new image to OLED driver is depended on the MCU writing speed. If MCU can
finish writing a frame image within one frame period, it is classified as fast write MCU. For MCU needs longer
writing time to complete(more than one frame but within two frames), it is a slow write one.
For fast write MCU: MCU should start to write new frame of ram data just after rising edge of FR pulse and
should be finished well before the rising edge of the next FR pulse.
For slow write MCU: MCU should start to write new frame ram data after the falling edge of the 1st FR pulse
and must be finished before the rising edge of the 3rd FR pulse.
7.4 Reset Circuit
When RES# input is pulled low, the chip is initialized with the following status:
1. Display is OFF
2. 64 MUX Display Mode
3. Display start line is set at display RAM address 0
4. Display offset set to 0
5. Normal segment and display data column address and row address mapping (SEG0 mapped to
address 00H and COM0 mapped to address 00H)
6. Column address counter is set at 0
7. Master contrast control register is set at 0FH
8. Individual contrast control registers of color A, B, and C are set at 80H
9. Shift register data clear in serial interface
10. Normal display mode (Equivalent to A4 command)
Fast write MCU
Slow write MCU
SSD1331 displaying memory updates to OLED screen
One frame
FR
100%
0%
Memory
Access
Process
Time

Solomon Systech Nov 2007 P 20/68 Rev 1.2 SSD1331
7.5 Graphic Display Data RAM (GDDRAM)
7.5.1 GDDRAM structure
The GDDRAM is a bit mapped static RAM holding the pattern to be displayed. The RAM size is 96 x 64 x
16bits.
For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software.
For vertical scrolling of the display, an internal register storing display start line can be set to control the
portion of the RAM data to be mapped to the display.
Each pixel has 16-bit data. Three sub-pixels for color A, B and C have 6 bits, 5 bits and 6 bits respectively.
The arrangement of data pixel in graphic display data RAM is shown below.
Figure 10 - 65k Color Depth Graphic Display Data RAM Structure
7.5.2 Data bus to RAM mapping under different input mode
Table 9 - Data bus usage under different bus width and color depth mode
Databus
Bus width Color Depth Input order D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
8 bits 256
XXXXXXXXC4 C3 C2 B5 B4 B3 A4 A3
8 bits 65k
format 1 1st XXXXXXXXC4 C3 C2 C1 C0 B5 B4 B3
2nd
XXXXXXXXB2 B1 B0 A4 A3 A2 A1 A0
8 bits 65k
format 2 1st XXXXXXXXXXC4 C3 C2 C1 C0 X
2nd
XXXXXXXXXXB5 B4 B3 B2 B1 B0
3rd
XXXXXXXXXXA4 A3 A2 A1 A0 X
16 bits 65k
C4 C3 C2 C1 C0 B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0
9 bits 65k 1st
XXXXXXXC4 C3 C2 C1 C0 X B5 B4 B3
2nd
XXXXXXXB2 B1 B0 A4 A3 A2 A1 A0 X
Normal :
Remap :
A
4B5 C4
A
4B5 C4
A
4B5 C4
A
4B5 C4
A
4B5 C4
A
4B5 C4
A
3B4 C3
A
3B4 C3
A
3B4 C3
A
3B4 C3
A
3B4 C3
A
3B4 C3
A
2B3 C2
A
2B3 C2
A
2B3 C2
A
2B3 C2
A
2B3 C2
A
2B3 C2
A
1B2 C1
A
1B2 C1
A
1B2 C1
A
1B2 C1
A
1B2 C1
A
1B2 C1
A
0B1 C0
A
0B1 C0
A
0B1 C0
A
0B1 C0
A
0B1 C0
A
0B1 C0
B0 B0 B0 B0 B0 B0 COM
Normal Remap OUTPU
T
063 565565565 565565565COM0
162 COM1
261 COM2
:::
61 2COM61
62 1COM62
63 0COM63
SA0 SB0 SC0 SA1 SB1 SC1 SA2 SB2 SC2 :SA93 SB93 SC93 SA94 SB94 SC94 SA95 SB95 SC95
:
:
Data
Format
Row
A
ddress
2
93
93
2
0
95
:
Column
A
ddress
SEG OUTPUT
195
0 94 1
94
no. of bits of data in this cell