Sony MDX-C7970 User manual

MICROFILM
SERVICE MANUAL
Model Name Using Similar Mechanism MDX-C7900/C7900R
Base Mechanism Type MG-164N-138
Optical Pick-Up Name KMS-241B/J1NP
US Model
Canadian Model
E Model
MDX-C7970
AEP Model
UK Model
MDX-C7970R
SPECIFICATIONS
MDX-C7970/C7970R
Photo: MDX-C7970R
FM/AM(MW/LW) MINIDISC PLAYER
– Continued on next page –
For RM-X4S (Remote Commander),
please refer to RM-X4S Service Manual
(9-925-698-∏) previously issued.

MDX-C7970/C7970R
4-8. SCHEMATIC DIAGRAM – SERVO Board (1/3) –
•See page 67 forWaveforms. •See page 63 for IC Block Diagrams.
– 37 – – 38 –
• Voltages and waveforms are dc with respect to ground
under no-signal conditions.
no mark :MD PLAY
∗: Impossible to measure
The components identified by mark !or dotted
line with mark !are critical for safety.
Replaceonly with partnumberspecified.
Lescomposantsidentifiésparune marque !sont
critiques pour la sécurité. Neles remplacer que
par une piéce portant le numéro spécifié.
(Page 39)

MDX-C7970/C7970R
– 39 –
4-9. SCHEMATIC DIAGRAM – SERVO Board (2/3) – • See page 67 forWaveforms. •See page 62 for IC Block Diagrams.
– 40 –
• Voltages and waveforms are dc with respect to ground
under no-signal conditions.
no mark :MD PLAY
∗: Impossible to measure
(Page 38) (Page 41)

MDX-C7970/C7970R
– 41 –
4-10. SCHEMATIC DIAGRAM – SERVO Board (3/3) – • See page 67 forWaveform.
– 42 –
• Voltages and waveforms are dc with respect to ground
under no-signal conditions.
no mark :MD PLAY
∗: Impossible to measure
(Page 40)
(Page 47)

MDX-C7970/C7970R
– 47 – – 48 –
4-13. SCHEMATIC DIAGRAM – MAIN Board (1/4) – • See page 67 for Waveforms. •See page 65 for IC Block Diagrams.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : FM
( ) : AM (MW)
[]:LW
〈〈 〉〉 : MD PLAY
(Page
42)
(Page 52)
(Page 53)
(Page 49)

MDX-C7970/C7970R
– 49 – – 50 –
4-14. SCHEMATIC DIAGRAM – MAIN Board (2/4) –
• Voltages are dc with respect to ground under no-signal
(detuned) conditions.
no mark : FM
(Page 48)
(Page 54)

MDX-C7970/C7970R
– 51 – – 52 –
4-15. SCHEMATIC DIAGRAM – MAIN Board (3/4) – • See page 67 for Waveforms. •See page 65 for IC Block Diagrams.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : FM
( ) : AM (MW)
[]:LW
(Page 48)
(Page 53)

MDX-C7970/C7970R
– 53 – – 54 –
• Voltages are dc with respect to ground under no-signal
(detuned) conditions.
no mark : FM
( ) : AM (MW)
[]:LW
〈〈 〉〉 : MD PLAY
4-16. SCHEMATIC DIAGRAM – MAIN Board (4/4) – • See page 66 for IC Block Diagrams.
(Page 52)
(Page 48)
(Page 49)
(Page 61)

MDX-C7970/C7970R
– 57 – – 58 –
4-18. SCHEMATIC DIAGRAM – DISPLAY Board – • See page 68 forWaveform.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : FM
(Page
61)

– 61 –
4-20. SCHEMATIC DIAGRAM – SUB Board –
MDX-C7970/C7970R
(Page 54) (Page 57)

– 62 –
• IC Block Diagrams
– SERVO Board –
IC101 PCM1718E/2K
IC301 CXD2652AR
INPUT
INTERFACE
DIGITAL
FILTER
5 LEVEL
DAC
LOWPASS
FILTER
CMOS
AMP
1
XTI
2
DGND
3
VDD
4
LRCIN
5
DIN
6
BCKIN
7
ZERO
8
D/C_R
9
VOUTR
10
AGND
NOISE SHAPER
5 LEVEL
DAC
LOWPASS
FILTER
CMOS
AMP
CLK
CONTROL
MODE
CONTROL
20 XTO
19 CLKO
18 MUTE
17 DM1
16 DM0
15 RSTB
14 FORMAT
13 D/C_L
12 VOUTL
11 VCC
100 99 98 97 96 95 94 93
EFMO DVSS TEST3 TEST2 TEST1 FGIN SPFD SPRD
92
SFDR
91
SRDR
90
FS4
89
FRDR
88
FFDR
87
DVDD
86
TFDR
85
TRDR
84
LDDR
83
APCREF
82
DTRF
81
CKRF
80
XLRF
79
F0CNT
78
ADFG
77
APC
76
DCHG
75 AUX2
74 TE
73 SE
72 AVSS
71 ADRB
70 ADRT
69 AVDD
68 ADIO
61 CLTV
60 FILO
59 FILI
58 PCO
57 PDO
55 RFI
56 AVSS
54 BIAS
53 AVDD
52 ASYI
51 ASYO
67 VC
66 AUX1
65 FE
64 ABCD
63 BOTM
62 PEAK
50
MVCI
49
D3
48
D2
47
D0
46
D1
45
XWE
44
XRAS
43
A09
42
XCAS
41
XOE
40
DVSS
39
A11
38
A08
37
A07
36
A06
35
A05
34
A04
33
A10
32
A00
31
A01
30
A02
29
A03
28
DVDD
26
XBCK
27
FS256
25
LRCK
24
DADT
23
ADDT
22
DOUT 21
DIN 20
DVSS 19
NC 18
XTSL 17
OSCO 16
OSCI 15
TX 14
XINT
13
RECP
12
DQSY
11
SQSY
10
XRST
9
SENS 8
SRDT 7
XLAT
6
SCLK 5
SWDT
4
MNT3 3
MNT2
2
MNT1 1
MNT0
PWM
GENERATOR
AUTO
SEQUENCER
SERVO
DSP
CPU I/F
MONITOR
CONTROL
SPINDLE
SERVO
EACH
BLOCK
EACH
BLOCK
DIGITAL
AUDIO
I/F
SAMPLING
RATE
CONVERTER
CLOCK
GENERATOR
SUBCODE
PROCESSOR
EACH
BLOCK
A/D
CONVERTER ANALOG
MUX
EFM/ACIRC
ENCODER/
DECODER
PLL
SHOCK RESISTANT
MEMORY CONTROLLER
ATRAC
ENCODER/DECODER
ADIP
DECODER
COMP
ADDRESS/DATA BUS A00 - A11, D0 - D3

– 63 –
IC302 CXA2523R
–1
–2
+
–
IVR BB
+
–
IVR AA
+
–
IVR CC
+
–
IVR DD
+
–
IVR +
–
EE EE'
EFB TESW
PTGR
48
MORFO
47
MORFI
46
RFO
45
OPN
44
OPO
43
ADDC
42
COMPP
41
COMPO
40
AGCI
39
RF AGC
38
RF
37
PEAK
36 BOTM
35 ABCD
34 FE
33 AUX
32 ADFG
31 ADAGC
30 ADIN
29 ADFM
28 SE
27 CSLED
26 TE
25 WBLADJ
24
VCC
23
3TADJ
22
EQADJ
21
VREF
20
F0CNT
19
XSTBY
18
XLAT
17
SCLK
16
SWDT
15
TEMPR
14
TEMPI
13
GND
12APCREF 11APC
10PD
9F
8E
7D
6C
5B
4A
3VC
VI CONV
BGR
VREF
SCRI - PARA
DECODE
+ –
+ –
AUXSW COMMAND
+
–
IVR
GSW IV
+
–
FF
FBAL
FF'
TG
SEA
–
+
–
+–1
–2
TG
TEA
WBL
3T
EQ
–
–
+
+
+
+
–
–
+
+
+
+
DET
ADIP
AGC
WBL
BPF22
BPFC
ABCDA
FEA
WBL
ATA
–
+
CVB
+ –
RFA1
–
–
–
–
1
2
–
–
–
1
2
GRVA
CFST
RFA2
GRV
HLPT
PTGR
–2
–1
–1
–2
BOTTOM
PEAK
RF AGC EQ
EQ
DET
P-P
WBL
3T WBL TEMP
PBH
–
+
USROP +
–USRC
3T
BPF3T
PEAK3T
1I
2J

– 64 –
IC303 BH6511FS-E2
IC305 BA6287F
IC307 MN41V4400TT-08S
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
12345678910 11 12 13 14 15 16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA– CAPA+ IN2R IN2F VM2 OUT2F PGND2 OUT2R VM12 OUT1R PGND1 OUT1F VM1 IN1F IN1R VDD
CHARGE
PUMP.
OSC
INTERFACE AMP
INTERFACE AMP
AMP INTERFACE
PREDRIVEPREDRIVE
PREDRIVEPREDRIVE
AMP
INTERFACE
AMPAMPAMP
VDD
PSB
AMP
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER DRIVER
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
1413
12
11
21
22
23
24
25
26
A0–A9
SENSE REFRESH AMP
INPUT/OUTPUT CONTROL SWITCH
(4) INPUT
BUFFER
(4) OUTPUT
BUFFER
CLOCK OSC
COLUMN DECODER
MEMORY CELL
(4194204 BIT)
A0–A9
ROW DECODER
GND
D4
D3
XCAS
XOE
NC
NC
NC
A8
A7
A6
A5
A4VDD
A3
A2
A1
A0
A9
NC
NC
NC
XRAS
XWE
D2
D1
ADDRESS BUFFER

– 65 –
– MAIN Board –
IC100 TDA7427AD
IC102 SAA6588T-118 (MDX-C7970R) IC250 NJM2360AM (TE2)
LP FM
LP HC
LP AM
VREF
DOUT3 DOUT4 DOUT5 DOUT6
OSCIN
OSCOUT
NC
SCL
SDA
IF AM
LP OUT
VDD2 GND-SIG NC FM IN AM IN GND-AM ADDR VDD1 HFREF
DOUT2
DOUT1/INLOCK
SSTOP IF FM
3 41 2 7 8 5 6 11 129 10
1516171819202122232425262728
13 14
TEST
LOGIC
PHASE
COM-
PARATOR
CHARGE
PUMP
SWITCH
LP1/LP2
INLOCK
DETECTOR
SWITCH
OUT 16 BIT
PROGRAMMABLE
COUNTER
SWITCH
SWM/DIR
SWITCH
SWM/DIR
PRE
COUNTER
SUPPLY &
POWER ON RESET
FM/AM
SWITCH
5 BIT
PROGRAMMABLE
COUNTER
11 BIT
PROGRAMMABLE
COUNTER
11 – 21 BIT
PROGRAMMABLE
COUNTER
IIC BUS
INTERFACE
FM/AM
SWITCH
REFERENCE
OSCILLATOR
14 BIT
PROGRAMMABLE
COUNTER
CONTROL
TIMER
PORT
EXTENSION
+ –
SCOUT
MRO
MPTH
TCON
OSCO
OSCI
VSSD
VDDD
DAVN
SDA
VREF
MPX
VSSA
VDDA
AFIN
MAD PSWN
SCL
2
16
15 11
1316 14 12
INTERFACE
REGISTER
SIGNAL QUALITY
DECODER
CLOCKED
COMPARATOR
POWER SUPPLY
& RESET
TEST
CONTROL OSCILLATOR
& CLOCK
PAUSE
DETECTOR
MULTI
PATH
DETECTOR 57kHz
8th ORDER
BAND-PASS FILTER
RDS/RDBS
DECODER
RDS/RDBS
DEMODULATOR
IIC BUS SLAVE
TRANSCEIVER
17
18
CIN
19
LVIN
20
87
DATA
CLOCK
DATA
CLOCK
44 5
9 10
34 5
+
–
1CS
3CT
4GND VREF
1.25V
2ES Q1 Q2 8CD
6V+
5 INVIN
7SI
QS
R
CT OSC
Ipk
COMP

– 66 –
IC300 TDA7462D013TR
IC600 BA8270F-E2 IC800 BA3918-V3
SE3L
SE3R
MUTE
SDA
SCL
PAUSE
OUT FL
OUT FR
OUT RL
OUT RR
SUBOUT+
SUBOUT–
VDD
GND
CREF
SE1L
SE1R
MD+
MD–
CDL+
CDL–
CDR–
CDR+
PDR
PDGND
PDL
SE2L
SE2R
INPUT
GAIN &
AUTO
ZERO
PAUSE
DETECT
INPUT MULTIPLEXER &
MIXING STAGE
REAR SIDE
SELECTOR FRONT SIDE
SELECTOR
LOUDNESS
CONTROL
CIRCUIT
INPUT
GAIN
BEEP
LOUDNESS
CONTROL
CIRCUIT
SOFT
MUTE
VOLUME
CONTROL
CIRCUIT
COMPANDER
TREBLE/
BASS
CONTROL
CIRCUIT
SUBWOOFER
OUT
FADER
SUBWOOFER
LP
IIC
BUS
DIGITAL CONTROL CIRCUIT
POWER
SUPPLY
FRONT
FADER
FRONT
FADER
REAR
FADER
REAR
FADER
VOICE BANDPASS
HP LP
SDA
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7 8
9
10
14
13
12
11
BUS ON
SWITCH
RESET
SWITCH
BATTERY
SWITCH
BUS ON
RST
BATT
CLK
VREF
DATA
GND
VCC
RST
BUS ON
CLK IN
BU IN
DATA IN
DATA OUT
+
–
+
–
+
–
+
–
OVER VOLTAGE
PROTECT
REGULATOR
12 3 45 6 7 8 9 10 1211
NC
MODE2 MODE1
STB
VDD
AMP
VCC ANT
COM
AM
FM
GND

– 67 –
• Waveforms
– SERVO Board –
1IC302 @§ (TE) (MD PLAY Mode)
2IC302 #¢ (FE) (MD PLAY Mode)
3IC302 #• (RF) (MD PLAY Mode)
4IC301 @∞ (LRCK) (MD PLAY Mode)
5IC301 @§ (XBCK) (MD PLAY Mode)
6IC501 #¡ (EXTAL) (MD PLAY Mode)
7IC304 3(IN) (MD PLAY Mode)
Approx.
0.5 Vp-p
2.7 Vp-p
0.1 µ s
Approx.
0.3 Vp-p
3.5 Vp-p
44 ns
1.2 Vp-p
3.5 Vp-p
23 µ s
4.5 Vp-p
356 µ s
– MAIN Board –
1IC100 9(OSC IN) (FM/AM (MW) Mode)
2IC102 5(OSC1) (FM Mode)
3IC250 2SWE (MD PLAY Mode)
4IC250 3TC (MD PLAY Mode)
5IC700 &¢ (XOA)
2.7 Vp-p
94 ns
2.8 Vp-p
224 ns
14.2 Vp-p
24 µ s
1.1 Vp-p
12 µ s
2.1 Vp-p
30 µ s

– 68 –
6IC700 (£ (X1)
– KEY Board –
1IC801 @º (OSC IN)
5.8 Vp-p
271 ns
2.8 Vp-p
3.5 µ s

– 69 –
4-21. IC PIN FUNCTION DESCRIPTION
•SERVO BOARD IC301 CXD2652AR
Pin No. Pin Name I/O Function
1 MNT0 O Focus OK signal output to the MD mechanism controller (IC501)
“H” is output when focus is on (“L”: NG)
2 MNT1 O Track jump detection signal output to the MD mechanism controller (IC501)
3 MNT2 O Busy monitor signal output to the MD mechanism controller (IC501)
4 MNT3 O Spindle servo lock status monitor signal output to the MD mechanism controller (IC501)
5 SWDT I Writing serial data signal input from the MD mechanism controller (IC501)
6 SCLK I Serial data transfer clock signal input from the MD mechanism controller (IC501)
7 XLAT I Serial data latch pulse signal input from the MD mechanism controller (IC501)
8 SRDT O (3) Reading serial data signal output to the MD mechanism controller (IC501)
9 SENS O (3) Internal status (SENSE) output to the MD mechanism controller (IC501)
10 XRST I Reset signal input from the MD mechanism controller (IC501) “L”: reset
11 SQSY O Subcode Q sync (SCOR) output to the MD mechanism controller (IC501)
“L” is output every 13.3 msec Almost all, “H” is output
12 DQSY O Digital In U-bit CD format subcode Q sync (SCOR) output terminal
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
13 RECP I Laser power selection signal input terminal
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
14 XINT O Interrupt status output to the MD mechanism controller (IC501)
15 TX I Recording data output enable signal input terminal
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
16 OSCI I System clock signal (512Fs=22.5792 MHz) input from the oscillator circuit
17 OSCO O System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
18 XTSL I Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19 RVDD — Power supply terminal (+3.3V) (digital system)
20 RVSS — Ground terminal (digital system)
21 DIN I Digital audio signal input terminal when recording mode Not used (fixed at “L”)
22 DOUT O Digital audio signal output terminal when playback mode Not used (open)
23 ADDT I Recording data input terminal Not used (fixed at “L”)
24 DADT O Playback data output to the PCM1718E (IC101)
25 LRCK O L/R sampling clock signal (44.1 kHz) output to the PCM1718E (IC101)
26 XBCK O Bit clock signal (2.8224 MHz) output to the PCM1718E (IC101)
27 FS256 O Clock signal (11.2896 MHz) output to the PCM1718E (IC101)
28 DVDD — Power supply terminal (+3.3V) (digital system)
29 to 32 A03 to A00 O Address signal output to the D-RAM (IC307)
33 A10 O Address signal output to the external D-RAM Not used (open)
34 to 38 A04 to A08 O Address signal output to the D-RAM (IC307)
39 A11 O Address signal output to the external D-RAM Not used (open)
40 DVSS — Ground terminal (digital system)
41 XOE O Output enable signal output to the D-RAM (IC307) “L” active
42 XCAS O Column address strobe signal output to the D-RAM (IC307) “L” active
43 A09 O Address signal output to the D-RAM (IC307)
44 XRAS O Row address strobe signal output to the D-RAM (IC307) “L” active
45 XWE O Write enable signal output to the D-RAM (IC307) “L” active
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)

– 70 –
Pin No. Pin Name I/O Function
46 D1 I/O
47 D0 I/O
48 D2 I/O
49 D3 I/O
50 MVCI I Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
51 ASYO O Playback EFM full-swing output terminal
52 ASYI I (A) Playback EFM asymmetry comparator voltage input terminal
53 AVDD — Power supply terminal (+3.3V) (analog system)
54 BIAS I (A) Playback EFM asymmetry circuit constant current input terminal
55 RFI I (A) Playback EFM RF signal input from the CXA2523R (IC302)
56 AVSS — Ground terminal (analog system)
57 PDO O (3) Phase comparison output for clock playback analog PLL of the playback EFM Not used (open)
58 PCO O (3) Phase comparison output for master clock of the recording/playback EFM master PLL
59 FILI I (A) Filter input for master clock of the recording/playback master PLL
60 FILO O (A) Filter output for master clock of the recording/playback master PLL
61 CLTV I (A) Internal VCO control voltage input of the recording/playback master PLL
62 PEAK I (A) Light amount signal (RF/ABCD) peak hold input from the CXA2523R (IC302)
63 BOTM I (A) Light amount signal (RF/ABCD) bottom hold input from the CXA2523R (IC302)
64 ABCD I (A) Light amount signal (ABCD) input from the CXA2523R (IC302)
65 FE I (A) Focus error signal input from the CXA2523R (IC302)
66 AUX1 I (A) Auxiliary signal (I
3 signal/temperature signal) input terminal Not used (fixed at “H”)
67 VC I (A) Middle point voltage (+1.65V) input from the CXA2523R (IC302)
68 ADIO O (A) Monitor output of the A/D converter input signal Not used (open)
69 AVDD — Power supply terminal (+3.3V) (analog system)
70 ADRT I (A) A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
71 ADRB I (A) A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
72 AVSS — Ground terminal (analog system)
73 SE I (A) Sled error signal input from the CXA2523R (IC302)
74 TE I (A) Tracking error signal input from the CXA2523R (IC302)
75 AUX2 I (A) Auxiliary signal input terminal Light amount signal input from the CXA2523R (IC302)
76 DCHG I (A) Connected to the +3.3V power supply
77 APC I (A) Error signal input for the laser automatic power control Not used (fixed at “L”)
78 ADFG I ADIP duplex FM signal (22.05 kHz ±1 kHz) input from the CXA2523R (IC302)
79 F0CNT O Filter f0 control signal output terminal Not used (open)
80 XLRF O Serial data latch pulse signal output terminal Not used (open)
81 CKRF O Serial data transfer clock signal output terminal Not used (open)
82 DTRF O Writing serial data output terminal Not used (open)
83 APCREF O Control signal output to the reference voltage generator circuit for the laser automatic power
control
84 LDDR O PWM signal output for the laser automatic power control Not used (open)
85 TRDR O Tracking servo drive PWM signal (–) output to the BH6511FS (IC303)
86 TFDR O Tracking servo drive PWM signal (+) output to the BH6511FS (IC303)
87 DVDD — Power supply terminal (+3.3V) (digital system)
88 FFDR O Focus servo drive PWM signal (+) output to the BH6511FS (IC303)
89 FRDR O Focus servo drive PWM signal (–) output to the BH6511FS (IC303)
90 FS4 O Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
91 SRDR O Sled servo drive PWM signal (–) output to the BH6511FS (IC303)
Two-way data bus with the D-RAM (IC307)

– 71 –
Pin No. Pin Name I/O Function
92 SFDR O Sled servo drive PWM signal (+) output to the BH6511FS (IC303)
93 SPRD O Spindle servo drive PWM signal (–) output to the BH6511FS (IC303)
94 SPFD O Spindle servo drive PWM signal (+) output to the BH6511FS (IC303)
95 FGIN I Not used (fixed at “L”)
96 TEST1 I
97 TEST2 I Input terminal for the test (fixed at “L”)
98 TEST3 I
99 DVSS — Ground terminal (digital system)
100 EFMO O EFM signal output terminal when recording mode Not used (open)
* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.