Sony CXD5602 User manual

CXD5602 User Manual
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CXD5602 User Manual

CXD5602 User Manual
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Contents
Contents.................................................................................................................................................................... 2
Figure Contents........................................................................................................................................................ 6
Table Contents....................................................................................................................................................... 10
1Introduction ................................................................................................................................................... 31
1.1 Introduction ............................................................................................................................................. 31
1.2 Notation................................................................................................................................................... 31
1.2.1 Notation of numerical value ............................................................................................................ 31
2CXD5602 Outline........................................................................................................................................... 33
2.1 Introduction ............................................................................................................................................. 33
2.2 Features.................................................................................................................................................... 33
2.3 Block Diagram......................................................................................................................................... 36
2.4 Architecture Overview............................................................................................................................. 37
2.5 CPU Processor......................................................................................................................................... 38
2.5.1 Application Processor...................................................................................................................... 38
2.5.2 System and I/O Processor................................................................................................................ 38
2.6 Memory Mapping.................................................................................................................................... 40
2.6.1 Memory Map of Each Block ........................................................................................................... 41
2.6.2 Main Memory.................................................................................................................................. 42
2.6.3 System Memory............................................................................................................................... 43
2.6.4 Backup Memory .............................................................................................................................. 43
2.7 Clock and Reset....................................................................................................................................... 43
2.7.1 Overview.......................................................................................................................................... 43
2.7.2 Clock Architecture........................................................................................................................... 46
2.8 Power Management................................................................................................................................. 48
2.8.1 Overview.......................................................................................................................................... 48
2.8.2 Power Domain ................................................................................................................................. 48
2.8.3 Power Supply States ........................................................................................................................ 51
3Function Details............................................................................................................................................. 53
3.1 I/O Configuration..................................................................................................................................... 53
3.1.1 Outline ............................................................................................................................................. 53
3.1.2 Function List.................................................................................................................................... 53
3.1.3 Switching between HOST I/F Select Function and SWD Function ................................................ 54
3.1.4 Pin Multiplexer................................................................................................................................ 55
3.2 General Purpose Input/Output (GPIO) .................................................................................................... 86
3.2.1 Outlines and Features....................................................................................................................... 86

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3.2.2 Function List.................................................................................................................................... 86
3.2.3 Function Specification Outlines....................................................................................................... 87
3.2.4 Detailed Function and Control Specification................................................................................... 89
3.3 Interrupt ................................................................................................................................................. 112
3.3.1 Overview and Features .................................................................................................................. 112
3.3.2 Register Descriptions..................................................................................................................... 113
3.4 PMU (Power Management Unit)........................................................................................................... 116
3.4.1 Features and Overview .................................................................................................................. 116
3.4.2 Register List................................................................................................................................... 126
3.4.3 Register Descriptions..................................................................................................................... 128
3.4.4 Power Supply Control Flow .......................................................................................................... 140
3.4.5 Power Supply Control Example .................................................................................................... 154
3.5 Clock and Reset (Clock Reset Generator)............................................................................................. 158
3.5.1 Overview........................................................................................................................................ 158
3.5.2 Clock Scheme for CRG ................................................................................................................. 158
3.5.3 Analog Circuits.............................................................................................................................. 160
3.5.4 Clock Setting Confirmation........................................................................................................... 163
3.5.5 Power Domain Reset ..................................................................................................................... 166
3.5.6 Reset by WDT ............................................................................................................................... 167
3.6 RTC ....................................................................................................................................................... 170
3.6.1 Outlines and Features..................................................................................................................... 170
3.6.2 Clock Input .................................................................................................................................... 171
3.6.3 Function List.................................................................................................................................. 172
3.6.4 Function Block Diagrams.............................................................................................................. 172
3.6.5 Detailed Function and Control Specification................................................................................. 175
3.7 I2C ......................................................................................................................................................... 212
3.7.1 Features and Overview .................................................................................................................. 212
3.7.2 I2C0, I2C1 ..................................................................................................................................... 213
3.7.3 I2C2 ............................................................................................................................................... 216
3.7.4 I2C4 ............................................................................................................................................... 218
3.8 DMAC................................................................................................................................................... 220
3.8.1 Overview and Features .................................................................................................................. 220
3.8.2 Function Descriptions.................................................................................................................... 220
3.8.3 SDMAC......................................................................................................................................... 222
3.8.4 HDMAC ........................................................................................................................................ 225
3.8.5 SYDMAC...................................................................................................................................... 227
3.8.6 SYSUBDMAC .............................................................................................................................. 228
3.8.7 ADMAC ........................................................................................................................................ 229
3.8.8 IDMAC.......................................................................................................................................... 231

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3.9 SCU (Sensor Control Unit).................................................................................................................... 243
3.9.1 SCU Overview and Features.......................................................................................................... 243
3.9.2 SCU Block Diagram...................................................................................................................... 245
3.9.3 Memory Map ................................................................................................................................. 246
3.9.4 Clock Control................................................................................................................................. 249
3.9.5 Power Supply Control.................................................................................................................... 255
3.9.6 Interrupt ......................................................................................................................................... 255
3.9.7 MATH_PROC processing............................................................................................................. 260
3.9.8 FIFO............................................................................................................................................... 270
3.9.9 Sequencers..................................................................................................................................... 276
3.9.10 DMA.............................................................................................................................................. 298
3.9.11 PWM.............................................................................................................................................. 300
3.9.12 SCU Register Details..................................................................................................................... 311
3.9.13 SCU Control Sequence.................................................................................................................. 812
3.9.14 Error Handling............................................................................................................................... 856
3.9.15 Restrictions.................................................................................................................................... 857
3.10 SPI ......................................................................................................................................................... 873
3.10.1 Features and Overview .................................................................................................................. 873
3.10.2 SPI0 ............................................................................................................................................... 874
3.10.3 SPI3 ............................................................................................................................................... 878
3.10.4 SPI4 ............................................................................................................................................... 880
3.10.5 SPI5 ............................................................................................................................................... 882
3.11 UART .................................................................................................................................................... 884
3.11.1 Overview and Features .................................................................................................................. 884
3.11.2 UART1 .......................................................................................................................................... 885
3.11.3 UART2 .......................................................................................................................................... 886
3.12 GNSS..................................................................................................................................................... 889
3.13 APP........................................................................................................................................................ 891
3.13.1 Function Overview ........................................................................................................................ 891
3.13.2 Power Supply Control.................................................................................................................... 894
3.13.3 Clock Reset Control....................................................................................................................... 895
3.13.4 Description of APP_DSP Function................................................................................................ 906
3.14 SYSIOP Clock and Reset Control......................................................................................................... 931
3.14.1 Function Overiew .......................................................................................................................... 931
3.14.2 Power Supply Control.................................................................................................................... 934
3.14.3 Clock and Reset Control................................................................................................................ 935
3.15 Audio Codec.......................................................................................................................................... 953
3.16 SDIO...................................................................................................................................................... 954
3.17 eMMC.................................................................................................................................................... 954

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3.18 USB ....................................................................................................................................................... 954
3.19 CIS I/F ................................................................................................................................................... 955
3.20 2D Graphics........................................................................................................................................... 955
3.21 ADC....................................................................................................................................................... 956
3.21.1 ADC Overview .............................................................................................................................. 956
3.21.2 ADC Block Diagram ..................................................................................................................... 957
3.21.3 Memory Map ................................................................................................................................. 957
3.21.4 Power Supply Control.................................................................................................................... 958
3.21.5 Clock Control................................................................................................................................. 959
3.21.6 Reset Control................................................................................................................................. 962
3.21.7 Interrupt ......................................................................................................................................... 962
3.21.8 FIFO writing Process..................................................................................................................... 962
3.21.9 Gain Control .................................................................................................................................. 963
3.21.10 Performance Estimation............................................................................................................. 965
3.21.11 Synchronization Function with PWM ....................................................................................... 966
3.21.12 ADC Control Register Details................................................................................................... 966
3.21.13 ADC Control Sequence ........................................................................................................... 1002
3.21.14 Restrictions.............................................................................................................................. 1002
3.21.15 Error Handling......................................................................................................................... 1003
4Appendix..................................................................................................................................................... 1004
4.1 Words and Terms................................................................................................................................. 1004
4.1.1 Words and Terms Used in This User Manual.............................................................................. 1004
4.2 Reference............................................................................................................................................. 1006
Revision History................................................................................................................................................. 1007

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Figure Contents
Figure Block Diagram-1 CXD5602 Block Diagram............................................................................................... 36
Figure Memory Mapping-2 Memory Map of the SYSIOP, GNSS, and APP ......................................................... 40
Figure Clock and Reset-3 Clock Diagram............................................................................................................... 47
Figure Power Management-4 Power Domain Layers.............................................................................................. 48
Figure Power Management-5 CXD5602 Power Domain........................................................................................ 49
Figure Power Management-6 Changes of Power Supply States.............................................................................. 52
Figure I/O Configuration-7 Switching between HOST I/F Function and SWD Function....................................... 54
Figure I/O Configuration-8 Visualized Function inside IOCELL Controlled by IOCELL Control Register ......... 66
Figure I/O Configuration-9 Examples of Assigning Roles to the Pin (P1r_02)...................................................... 70
Figure I/O Configuration-10 PMIC_INT Signal Routes (MODE=1)...................................................................... 72
Figure I/O Configuration-11 PMIC_INT Signal Routes (MODE=2 Open Drain).................................................. 73
Figure I/O Configuration-12 RTC_IRQ_OUT Signal Routes (MODE=2 Open Drain).......................................... 74
Figure I/O Configuration-13 SDIO CLK Input Schematic...................................................................................... 82
Figure I/O Configuration-14 SDIO WP/CD Input Control Register Schematic...................................................... 83
Figure General Purpose Input/Output (GPIO)-15 GPIO Overview Block Diagram............................................... 87
Figure General Purpose Input/Output (GPIO)-16 Diagram of GPIO Event Detect Block...................................... 88
Figure General Purpose Input/Output (GPIO)-17 Output Signal Route in the I/O Function Controlled by GPIO
Parameter............................................................................................................................................................. 91
Figure General Purpose Input/Output (GPIO)-18 Input Signal Route in the I/O Function Controlled by GPIO
Parameter............................................................................................................................................................. 92
Figure General Purpose Input/Output (GPIO)-19 GPIO Pin Selection................................................................... 93
Figure General Purpose Input/Output (GPIO)-20 External Interrupt Selection ...................................................... 97
Figure General Purpose Input/Output (GPIO)-21 Event Detection Control.......................................................... 100
Figure General Purpose Input/Output (GPIO)-22 Event Detection Timing Diagram........................................... 103
Figure General Purpose Input/Output (GPIO)-23 Connection Diagram of Event Detection and SYSCPU or DSP
........................................................................................................................................................................... 108
Figure General Purpose Input/Output (GPIO)-24 Time Interval for a Signal to be able to Detect an Event Again
(PMU_WAKE_TRIG_NOISECUTEN0:0)....................................................................................................... 111
Figure Interrupt-25 Interrupt Connection Diagram ............................................................................................... 112
Figure PMU (Power Management Unit)-26 PMU and the Power Domain Layers............................................... 116
Figure PMU (Power Management Unit)-27 Individual Power Supply Control within the Power Domains......... 118
Figure PMU (Power Management Unit)-28 Power Supply Control within the Power Domain (PWD_APP Main
Memory) ............................................................................................................................................................ 119
Figure PMU (Power Management Unit)-29 Changes of Power Supply States ..................................................... 121
Figure PMU (Power Management Unit)-30 Overall Block Diagram of the PMU................................................ 124

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Figure PMU (Power Management Unit)-31 PMU Clock System ......................................................................... 125
Figure PMU (Power Management Unit)-32 Sleep/Wakeup Control Flow of the Application Processor............. 157
Figure Clock and Reset (Clock Reset Generator)-33 CRG Control Area within Overall Clock Scheme............. 159
Figure Clock and Reset (Clock Reset Generator)-34 CRG Clock Scheme........................................................... 159
Figure RTC-35 RTC0/1 Power Supply Framework.............................................................................................. 170
Figure RTC-36 Clock Resources of RTC.............................................................................................................. 172
Figure RTC-37 RTC Block Diagram..................................................................................................................... 173
Figure RTC-38 RTC (Time Update) Block Diagram............................................................................................ 174
Figure I2C-39 I2C0/I2C1 Clock and Reset System............................................................................................... 214
Figure I2C-40 I2C2 Clock and Reset System........................................................................................................ 216
Figure I2C-41 I2C4 Clock and Reset System........................................................................................................ 218
Figure DMAC-42 SDMAC Overview of Added Functions.................................................................................. 222
Figure DMAC-43 SDMAC Clock and Reset System............................................................................................ 224
Figure DMAC-44 HDMAC Overview of Added Functions ................................................................................. 225
Figure DMAC-45 HDMAC Clock and Reset System........................................................................................... 226
Figure DMAC-46 SYDMAC Clock and Reset System......................................................................................... 227
Figure DMAC-47 SYSUBDMAC Clock and Reset System................................................................................. 229
Figure DMAC-48 ADMAC Clock and Reset System........................................................................................... 230
Figure DMAC-49 IDMAC Function Block Diagram............................................................................................ 231
Figure DMAC-50 IDMAC Clock and Reset System ............................................................................................ 242
Figure SCU (Sensor Control Unit)-51 Block Function Overview......................................................................... 245
Figure SCU (Sensor Control Unit)-52 Memory Mapping from the Upper CPUs; the CPU in the SYSIOP and the
CPU in the GNSS; (hereinafter in the Chapter on SCU, referred as “upper CPUs”) ........................................ 246
Figure SCU (Sensor Control Unit)-53 Memory Mapping within the SCU as seen from the Upper CPUs........... 247
Figure SCU (Sensor Control Unit)-54 Memory Mapping as seen from the Internal Sequencer........................... 248
Figure SCU (Sensor Control Unit)-55 Memory Mapping as seen from the HOSTIFC ........................................ 248
Figure SCU (Sensor Control Unit)-56 Clock System............................................................................................ 251
Figure SCU (Sensor Control Unit)-57 Interrupt Connections............................................................................... 256
Figure SCU (Sensor Control Unit)-58 Decimation Partition Data Path................................................................ 261
Figure SCU (Sensor Control Unit)-59 Normal Sensor Partition Data Path........................................................... 261
Figure SCU (Sensor Control Unit)-60 Preprocessing Data Flow.......................................................................... 262
Figure SCU (Sensor Control Unit)-61 Decimation Processing Data Flow ........................................................... 263
Figure SCU (Sensor Control Unit)-62 Data Flow within the Math Function........................................................ 264
Figure SCU (Sensor Control Unit)-63 2 2nd Order IIR Filter Combinations........................................................ 265
Figure SCU (Sensor Control Unit)-64 2nd Order IIR Filter Internal Data Flow................................................... 266
Figure SCU (Sensor Control Unit)-65 Normalization Processing Data Flow....................................................... 266
Figure SCU (Sensor Control Unit)-66 Excess Detection Operation (by a Comparator and an Excess Detector). 267
Figure SCU (Sensor Control Unit)-67 Excess Detection Operation (Two-step Cascade Connection) ................. 268
Figure SCU (Sensor Control Unit)-68 FIFO Block Diagram................................................................................ 276

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Figure SCU (Sensor Control Unit)-69 Sequencer Overall Image.......................................................................... 278
Figure SCU (Sensor Control Unit)-70 Sequencer Process Flow (Example) ......................................................... 278
Figure SCU (Sensor Control Unit)-71 Overall Data Flow (excluding Data Duplication Function)...................... 279
Figure SCU (Sensor Control Unit)-72 Startup Control......................................................................................... 280
Figure SCU (Sensor Control Unit)-73 External Bus Transaction Generation....................................................... 281
Figure SCU (Sensor Control Unit)-74 External Data Capture .............................................................................. 282
Figure SCU (Sensor Control Unit)-75 Sensor Data Flow when Capturing External Data.................................... 283
Figure SCU (Sensor Control Unit)-76 Data Normalization (Example)................................................................. 284
Figure SCU (Sensor Control Unit)-77 Data Stacked in the FIFO (Image)............................................................ 285
Figure SCU (Sensor Control Unit)-78 Sequencer Data Flow................................................................................ 292
Figure SCU (Sensor Control Unit)-79 Sequencer Completed............................................................................... 294
Figure SCU (Sensor Control Unit)-80 Sequencer Suspended............................................................................... 294
Figure SCU (Sensor Control Unit)-81 MATH_PROC Parameter Change (Example).......................................... 295
Figure SCU (Sensor Control Unit)-82 Error Notification (Example).................................................................... 297
Figure SCU (Sensor Control Unit)-83 DMA Handshake Signal Connections...................................................... 299
Figure SCU (Sensor Control Unit)-84 PWM Output Mode using ADC Timing as a Reference.......................... 303
Figure SCU (Sensor Control Unit)-85 ADC Data Capture Mode using the PWM Output Timing as a Reference
........................................................................................................................................................................... 306
Figure SCU (Sensor Control Unit)-86 Processing Block Overview...................................................................... 354
Figure SCU (Sensor Control Unit)-87 Filter Overview......................................................................................... 356
Figure SCU (Sensor Control Unit)-88 Excess Detection Overview...................................................................... 392
Figure SCU (Sensor Control Unit)-89 I2C Master Control (Example)................................................................. 860
Figure SCU (Sensor Control Unit)-90 Basic Startup Timing................................................................................ 861
Figure SCU (Sensor Control Unit)-91 Delay at Start (Example) .......................................................................... 861
Figure SCU (Sensor Control Unit)-92 Time Stamp Fluctuation by the Presence/Absence of HPADC Execution866
Figure SCU (Sensor Control Unit)-93 Counter Basic Operation .......................................................................... 868
Figure SCU (Sensor Control Unit)-94 1 One-to-One Connection (Example)....................................................... 869
Figure SCU (Sensor Control Unit)-95 One-to-N Connection (Example).............................................................. 869
Figure SPI-96 SPI0 Clock and Reset System........................................................................................................ 876
Figure SPI-97 SPI3 Clock and Reset System........................................................................................................ 879
Figure SPI-98 SPI4 Clock and Reset System........................................................................................................ 880
Figure SPI-99 SPI5 Clock and Reset System........................................................................................................ 882
Figure UART-100 UART1 Clock and Reset System............................................................................................ 885
Figure UART-101 UART2 Clock and Reset System............................................................................................ 887
Figure APP-102 Application Domain Clock System ............................................................................................ 896
Figure APP-103 Application Domain Reset System............................................................................................. 897
Figure APP-104 APP_DSP Block Diagram.......................................................................................................... 907
Figure APP-105 WDTRES Connection ................................................................................................................ 914
Figure APP-106 Address Map............................................................................................................................... 918

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Figure APP-107 Input-Output Addresses of Address Converter........................................................................... 919
Figure APP-108 Address Conversion Operation Scheme..................................................................................... 920
Figure APP-109 Example of Address Conversion: Conversion of Bit Assignment for ADSP0........................... 923
Figure APP-110 Example of Address Conversion: Conversion Address Map for ADSP0 and ADSP1............... 923
Figure APP-111 Success Case 1 of Exclusive Access........................................................................................... 925
Figure APP-112 Success Case 2 of Exclusive Access........................................................................................... 925
Figure APP-113 Failure Case 1 of Exclusive Access............................................................................................ 926
Figure APP-114 Failure Case 2 of Exclusive Access............................................................................................ 926
Figure APP-115 Failure Case 3 of Exclusive Access............................................................................................ 926
Figure SYSIOP Clock and Reset Control-116 SYSIOP Clock Configuration Diagram....................................... 936
Figure SYSIOP Clock and Reset Control-117 SYSIOP Reset Configuration Diagram........................................ 950
Figure ADC-118 Block Diagram ADCIF module and around ADC macro circuits............................................. 957
Figure ADC-119 Memory Map inside the ADCIF................................................................................................ 958
Figure ADC-120 Schematic Diagram of the Clock Control.................................................................................. 960
Figure ADC-121 Data Flow of the ADC............................................................................................................... 962
Figure ADC-122 HPADC Gain Control Overview............................................................................................... 964

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Table Contents
Table Notation-1 Notation of Numerical Value ...................................................................................................... 31
Table Memory Mapping-2 Memory Mapping of the SYSIOP Block (SYS Window)............................................ 41
Table Memory Mapping-3 Memory Mapping of the APP Block (APP Window).................................................. 42
Table Power Management-4 Power Supply States.................................................................................................. 51
Table I/O Configuration-5 Function List................................................................................................................. 53
Table I/O Configuration-6 HOST I/F Decided in Accordance with Pin SYSTEM{0,1}........................................ 54
Table I/O Configuration-7 List of Registers for Controlling Pin Multiplexer......................................................... 55
Table I/O Configuration-8 List of Registers for Controlling IOCELL.................................................................... 55
Table I/O Configuration-9 List of Registers for AUDIO and SDIO Control.......................................................... 58
Table I/O Configuration-10 Overview of Registers for Selecting a Role of the I/O Pins Belonging to SYS Group
............................................................................................................................................................................. 59
Table I/O Configuration-11 Table of Role Selection for I/O Pins Belonging to SYS Group.................................. 60
Table I/O Configuration-12 Overview of Registers for Selecting a Role of the I/O Pins Belonging to APP Group
............................................................................................................................................................................. 62
Table I/O Configuration-13 Table of Role Selection for the I/O Pins Belonging to APP Group............................ 63
Table I/O Configuration-14 Overview of Registers to Select Function of IOCELL............................................... 65
Table I/O Configuration-15 Correspondence Table of IOCELL Control Registers and Controllable I/O Pins...... 67
Table I/O Configuration-16 Overview of Registers for Selecting Output Function of I2S..................................... 68
Table I/O Configuration-17 Overview of Register for Selecting PDM_CLK Output Function.............................. 68
Table I/O Configuration-18 Overview of Registers for Selecting Input Value to SDIO......................................... 69
Table General Purpose Input/Output (GPIO)-19 Function List............................................................................... 86
Table General Purpose Input/Output (GPIO)-20 GPIO Control Register............................................................... 89
Table General Purpose Input/Output (GPIO)-21 Correspondence of GPIO Control Registers to I/O Pins............ 90
Table General Purpose Input/Output (GPIO)-22 IO Pin Selection (SYS Group) ................................................... 94
Table General Purpose Input/Output (GPIO)-23 Correspondence of I/O Pins to Setting Values (SYS Group)..... 95
Table General Purpose Input/Output (GPIO)-24 I/O Pin Selection (APP Group) .................................................. 95
Table General Purpose Input/Output (GPIO)-25 Correspondence of I/O Pins to Setting Values (APP Group)..... 96
Table General Purpose Input/Output (GPIO)-26 External Interrupt Selection........................................................ 98
Table General Purpose Input/Output (GPIO)-27 I/O Pins That Can be Used for Event Detection....................... 101
Table General Purpose Input/Output (GPIO)-28 Event Detection Setting for I/O Pins........................................ 103
Table General Purpose Input/Output (GPIO)-29 Status of Event Detection......................................................... 106
Table General Purpose Input/Output (GPIO)-30 Registers to Clear the Status of the Event Detections .............. 107
Table General Purpose Input/Output (GPIO)-31 Time Interval for a Signal to be Able to Detect an Event Again
(1*)....................................................................................................................................................................... 110