Nuvoton ISD61S00 ChipCorder Guide

ISD61S00 ChipCorder
Telephony Feature Chip
Design Guide
©2008 Nuvoton Technology Corporation America all rights reserved.
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ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 2 - Revision 2.7
Table of Contents
1. GENERAL DESCRIPTION ............................................................................................................10
2. FEATURES....................................................................................................................................10
3. PIN CONFIGURATION..................................................................................................................12
4. PIN DESCRIPTION........................................................................................................................13
5. BLOCK DIAGRAM.........................................................................................................................16
6. CONFIGURATION REGISTER MAP.............................................................................................17
6.1 Configuration Register Groups......................................................................................17
6.2 Register Map .................................................................................................................17
7. DEVICE STATUS...........................................................................................................................32
7.1 Device Status Register..................................................................................................32
8. FUNCTIONAL DESCRIPTION ......................................................................................................34
8.1 SPI Interface..................................................................................................................34
8.2 Record and Playback Control........................................................................................36
8.2.1 COMP_CFG –Compression Configuration....................................................................36
8.2.2 COMP_CTRL –Compression Control............................................................................38
8.2.3 COMP_SRC –Compression Source..............................................................................39
8.2.4 CLK_CTRL –Clock Control............................................................................................39
8.2.5 CFG17 –Update Mode...................................................................................................40
8.3 Clock Generation and PLL ............................................................................................40
8.3.1 Phase Locked Loop (PLL) Design Example ...................................................................41
8.3.2 PLL_CLK ........................................................................................................................42
8.3.3 PLL_FRAC......................................................................................................................43
8.3.4 PLL_CTRL......................................................................................................................43
8.4 Digital Audio Interface Control.......................................................................................43
8.4.1 PCM_CFG......................................................................................................................44
8.4.2 PCM_TSLOTL................................................................................................................45
8.4.3 PCM_TSLOTR................................................................................................................45
8.4.4 PCM_COMP0.................................................................................................................45
8.4.5 PCM_TSLOTL1..............................................................................................................45
8.4.6 PCM_TSLOTR1..............................................................................................................46
8.4.7 PCM_COMP1.................................................................................................................46
8.4.8 PCM_TX_SEL ................................................................................................................47
8.4.9 PCM_RX_SEL................................................................................................................48
8.5 GPIO and Interrupt Configuration..................................................................................48
8.5.1 PORT_CFG....................................................................................................................48
8.5.2 PORTx_IE.......................................................................................................................49
8.5.3 IE0..................................................................................................................................49
8.5.4 IE1..................................................................................................................................50

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 3 - Revision 2.7
8.5.5 PORTA_DO....................................................................................................................50
8.5.6 PORTA_OE....................................................................................................................50
8.5.7 PORTA_PE.....................................................................................................................50
8.5.8 PORTA_DI......................................................................................................................51
8.5.9 PORTA_PS.....................................................................................................................51
8.5.10 PORTA_DS ....................................................................................................................51
8.5.11 PORTA_AF.....................................................................................................................51
8.6 16 bit Indirect Index register R0-R7...............................................................................53
8.7 Microphone interface and Auxiliary Interface................................................................54
8.7.1 MIC_CTRL......................................................................................................................54
8.7.2 MIC_BIAS.......................................................................................................................55
8.8 PSTN Analog Input........................................................................................................60
8.8.1 TI_GAIN..........................................................................................................................61
8.8.2 TI_CTRL.........................................................................................................................61
8.9 Analog Outputs..............................................................................................................63
8.9.1 ANA_OUT.......................................................................................................................64
8.9.2 ANA_CTRL.....................................................................................................................64
8.10 DTMF Detection ............................................................................................................65
8.10.1 DTMF_CTRL ..................................................................................................................67
8.10.2 DTMF_FIFO_CTRL........................................................................................................67
8.10.3 DTMF_FIFO....................................................................................................................68
8.10.4 DTMF_FIFO_STATUS ...................................................................................................68
8.10.5 DTMF_THRES................................................................................................................68
8.10.6 DTMF_PDT.....................................................................................................................69
8.10.7 DTMF_ADT.....................................................................................................................70
8.10.8 DTMF_ACCT..................................................................................................................70
8.10.9 70
8.10.10 DTMF_RX_DATA...........................................................................................................70
8.10.11 DTMF_ROW_FREQ.......................................................................................................71
8.10.12 DTMF_COL_FREQ ........................................................................................................71
8.10.13 Tip & Tricks.....................................................................................................................71
8.11 DTMF and Arbitrary Tone Generation...........................................................................72
8.11.1 TONE_CTRL ..................................................................................................................73
8.11.2 TONE_FREQ_A .............................................................................................................73
8.11.3 TONE_FREQ_B .............................................................................................................74
8.11.4 TONE_LEVEL_A............................................................................................................74
8.11.5 TONE_LEVEL_B............................................................................................................74
8.11.6 TONE_ON_TIME............................................................................................................74
8.11.7 TONE_OFF_TIME..........................................................................................................75
8.11.8 TONE_LENGTH.............................................................................................................75
8.11.9 75
8.11.10 TONE_INDEX_0 ~ TONE_INDEX_A..............................................................................76
8.12 FSK Generation.............................................................................................................76
8.12.1 FSKE_CTRL1.................................................................................................................78

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 4 - Revision 2.7
8.12.2 FSKE_CTRL2.................................................................................................................78
8.12.3 FSKE_TX_DATA............................................................................................................79
8.12.4 FSKE_STATUS..............................................................................................................79
8.12.5 FSKE_GAIN....................................................................................................................79
8.12.6 FSKE_PROG..................................................................................................................79
8.12.7 FSKE_BAUD (SW_MODE = 1) ......................................................................................80
8.12.8 FSKE_MARK_FREQ (SW_MODE = 1)..........................................................................80
8.12.9 FSKE_SPACE_FREQ (SW_MODE = 1) ........................................................................81
8.12.10 FSKE_TEST...................................................................................................................81
8.12.11 81
8.12.12 Example FSK Generator Usage .....................................................................................81
8.13 FSK Detection ...............................................................................................................85
8.13.1 FSKD_CTRL...................................................................................................................86
8.13.2 FSKD_MODE .................................................................................................................88
8.13.3 FSKD_ADJUST..............................................................................................................88
8.13.4 FSKD_STATUS..............................................................................................................89
8.13.5 FSKD_THRES................................................................................................................89
8.13.6 FSKD_JUDGE................................................................................................................90
8.13.7 FSKD_SYNC..................................................................................................................90
8.13.8 FSKD_CDET ..................................................................................................................90
8.13.9 FSKD_FIFO_CTRL.........................................................................................................91
8.13.10 FSKD_FIFO_DOUT........................................................................................................92
8.13.11 FSKD_FIFO_STATUS....................................................................................................92
8.13.12 FSKD_ENERGY_HIGH_TH ...........................................................................................92
8.13.13 FSKD_ENERGY_LOW_TH............................................................................................93
8.13.14 FSKD_ENERGY_TC......................................................................................................93
8.13.15 93
8.13.16 FSKD_CDB_FREQ_LOW_CNT.....................................................................................93
8.13.17 FSKD_CDB_FREQ_HIGH_CNT ....................................................................................94
8.13.18 FSKD_LIMIT_TH............................................................................................................94
8.13.19 Example FSK Detector Usage........................................................................................95
8.14 CAS and Arbitrary Tone (ATD) Detector.......................................................................99
8.14.1 CAS_CTRL...................................................................................................................101
8.14.2 CAS_THRES_LOW –CAS detector low threshold.......................................................102
8.14.3 CAS_MULT...................................................................................................................102
8.14.4 CAS_PRESENT ...........................................................................................................103
8.14.5 CAS_ABSENT..............................................................................................................104
8.14.6 CAS_STATUS..............................................................................................................104
8.14.7 CAS_MODE - Arbitrary Tone Detection Mode..............................................................104
8.14.8 ATD_MAX_HFC (ATD_MODE = 1)..............................................................................105
8.14.9 ATD_MIN_HFC (ATD_MODE = 1) ...............................................................................105
8.14.10 ATD_MAX_LFC (ATD_MODE = 1)...............................................................................106
8.14.11 ATD_MIN_LFC (ATD_MODE = 1)................................................................................106
8.14.12 External Dual-IIR Coefficient (ATD_MODE= 1)............................................................106

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 5 - Revision 2.7
8.14.13 FSK_COEFF –FSK Encoder Coefficient RAM Data....................................................107
8.14.14 FSK_COEFF_ADDR - FSK Encoder Coefficient RAM Address...................................108
8.14.15 CAS_MAX_HFC (FINE_TUNE = 1)..............................................................................108
8.14.16 CAS_MIN_HFC (FINE_TUNE = 1)...............................................................................109
8.14.17 CAS_MAX_LFC (FINE_TUNE = 1)...............................................................................109
8.14.18 CAS_MIN_LFC (FINE_TUNE = 1)................................................................................109
8.14.19 110
8.14.20 110
8.14.21 Arbitrary Tone Detector Example..................................................................................110
8.15 Voice Energy Detection (Speech Energy Detection) ..................................................115
8.15.1 VD_CTRL .....................................................................................................................116
8.15.2 VD_STATUS.................................................................................................................116
8.15.3 VD_THRES...................................................................................................................116
8.15.4 VD_ENERGY................................................................................................................116
8.16 Call Progress Tone Detector.......................................................................................117
8.16.1 CPT_CTRL...................................................................................................................117
8.16.2 CPT_STATUS ..............................................................................................................118
8.16.3 CPT_THRES_H............................................................................................................118
8.16.4 CPT_THRES_L ............................................................................................................118
8.16.5 CPT_ENERGY .............................................................................................................119
8.17 Ring Detection and Pulse / Period Width Measurement.............................................119
8.17.1 RNG_CTRL ..................................................................................................................120
8.17.2 RNG_STATE................................................................................................................122
8.17.3 RNG_CNTR..................................................................................................................122
8.17.4 RNG_LATCH................................................................................................................123
8.17.5 123
8.18 Timer............................................................................................................................123
8.18.1 123
8.18.2 TIME_TARG.................................................................................................................124
8.18.3 TIME_CNT....................................................................................................................124
8.19 Gain Stage and Mixer..................................................................................................124
8.19.1 GS_CTRL.....................................................................................................................128
8.19.2 CODEC EC Gain Stages..............................................................................................129
8.19.3 AECin Path Mixing Gain Control...................................................................................130
8.19.4 LECin Path Mixing Gain Control...................................................................................130
8.19.5 REC Path Mixing Gain Control Registers.....................................................................131
8.19.6 I2SLin Path Mixing Gain Control Registers................................................................132
8.19.7 I2SRin Path Mixing Gain Control Registers..................................................................132
8.19.8 Mixer Source Enable Registers ....................................................................................133
8.20 Air and Line CODEC ...................................................................................................133
8.20.1 AC_EN, LC_EN –Air /Line CODEC Enable Register...................................................134
8.20.2 AC_CTRL, LC_CTRL –Air /Line CODEC Dither Control .............................................135
8.20.3 AC_ADCG, LC_ADCG –Air/Line CODEC ADC Gain................................................135
8.20.4 AC_DACG, LC_DACG –Air/Line CODEC DAC Gain. .................................................135

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 6 - Revision 2.7
8.20.5 136
8.20.6 136
8.21 RINGER TONE GENERATOR....................................................................................136
8.21.1 PWM Clock...................................................................................................................137
8.21.2 PWM Tone1 Control.....................................................................................................137
8.21.3 PWM Tone1 Frequency................................................................................................138
8.21.4 PWM Tone2 Control.....................................................................................................138
8.21.5 PWM Tone2 Frequency................................................................................................139
9. ACOUSTIC PROCESSING BLOCK............................................................................................139
9.1 Full/Half AEC Block Diagram ......................................................................................139
9.2 Control Register Memory Map ....................................................................................141
9.2.1 Threshold and Power Calculation.................................................................................145
9.3 Control Registers.........................................................................................................145
9.3.1 CONFIG........................................................................................................................146
9.3.2 RESET..........................................................................................................................146
9.3.3 EC_BELTA ...................................................................................................................147
9.3.4 AS_COEFF...................................................................................................................148
9.4 Double Talk Detector Control Registers......................................................................148
9.4.1 Function........................................................................................................................149
9.4.2 DT_LONG_TC..............................................................................................................149
9.4.3 DT_SHORT_TC............................................................................................................149
9.4.4 Double Talk Detector Parameters.................................................................................150
9.4.5 DIVERGENCE..............................................................................................................150
9.5 Voice Detector Control Registers................................................................................151
9.5.1 Function........................................................................................................................151
9.5.2 VD_LONG_TC..............................................................................................................151
9.5.3 VD_SHORT_TC ...........................................................................................................151
9.5.4 Voice Detector Parameters...........................................................................................151
VD_AVE_TC 152
9.5.5 VD_AVE_THRESH.......................................................................................................153
9.6 AS1 & AS2 Control Registers......................................................................................153
9.6.1 Function........................................................................................................................153
9.6.2 AS1_BUILD_UP_TIME.................................................................................................153
9.6.3 AS1_MAX_ATTEN .......................................................................................................153
9.6.4 AS2_BUILD_UP_TIME.................................................................................................154
9.6.5 AS2_MAX_ATTEN .......................................................................................................154
9.7 Noise Suppressor Registers........................................................................................154
9.7.1 Function........................................................................................................................154
9.7.2 NS_POWER_ATTACK_TC ..........................................................................................155
9.7.3 NS_ATTEN _TC...........................................................................................................155
9.7.4 NS_ACTIVE_THRESHOLD..........................................................................................155
9.8 155
9.9 Soft Clip (SC) Control Registers..................................................................................156

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 7 - Revision 2.7
9.9.1 Functional Description..................................................................................................156
9.9.2 SC_CTRL .....................................................................................................................156
9.9.3 SC_NORMAL_INDEX ..................................................................................................157
9.9.4 SC_LOW_INDEX..........................................................................................................158
9.9.5 SC_THRESH................................................................................................................158
9.9.6 SC_POWER_ATTACK_TC ..........................................................................................158
9.9.7 SC_GAIN_TC...............................................................................................................159
9.10 State Read back Registers..........................................................................................159
9.10.1 Functional Description..................................................................................................159
9.10.2 Power Monitor...............................................................................................................159
9.10.3 Signal Monitor...............................................................................................................160
9.11 160
9.12 Automatic Gain Control ...............................................................................................161
9.12.1 AGC_CTRL...................................................................................................................162
9.12.2 AGC_INIT_GAIN ..........................................................................................................163
9.12.3 AGC_GAIN_HOLD.......................................................................................................163
9.12.4 AGC_INC_DEC............................................................................................................163
9.12.5 AGC_ATK_DCY ...........................................................................................................163
9.12.6 AGC_GAIN_READ.......................................................................................................164
9.12.7 AGC_STATE ................................................................................................................164
9.12.8 AGC_PWR_TC.............................................................................................................164
9.12.9 AGC_PK_TC ................................................................................................................165
9.12.10 AGC_PK.......................................................................................................................165
9.12.11 AGC TARGETS............................................................................................................165
9.12.12 AGC NOISE PARAMETERS........................................................................................166
10. SPI COMMANDS.........................................................................................................................166
10.1 Audio Play and Record Commands ............................................................................169
10.1.1 Play Voice Prompt........................................................................................................170
10.1.2 Play Voice Prompt @Rn, n = 0 ~ 7...............................................................................170
10.1.3 Play Voice Prompt, Loop..............................................................................................170
10.1.4 Play Voice Prompt, Loop, @Rn, n = 0 ~ 7....................................................................172
10.1.5 Stop Loop-Play Command............................................................................................172
10.1.6 Execute Voice Macro....................................................................................................172
10.1.7 Execute Voice Macro @Rn, n = 0 ~ 7...........................................................................173
10.1.8 Record Message...........................................................................................................173
10.1.9 Record Message at Address.........................................................................................174
10.1.10 Play Message at Address.............................................................................................174
10.1.11 Play Silence..................................................................................................................175
10.1.12 Stop Command.............................................................................................................175
10.1.13 Erase Message at Address...........................................................................................176
10.1.14 SPI Send Audio Data....................................................................................................176
10.1.15 SPI Receive Audio Data...............................................................................................177
10.1.16 SPI Send Compressed Audio Data for direct programming to flash.............................179

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 8 - Revision 2.7
10.1.17 SPI Receive previous REC_MSG or REC_MSG@ compressed Audio Data stored in flash
180
10.1.18 SPI Send Compressed Data to Decode .......................................................................181
10.1.19 SPI Receive Encoded Data ..........................................................................................182
10.2 Device Status Commands...........................................................................................183
10.2.1 Read Status..................................................................................................................183
10.2.2 Read Interrupt...............................................................................................................183
10.2.3 Read Recorded Message Address Details...................................................................183
10.2.4 Read Message Length..................................................................................................184
10.2.5 Read ISD61S00 ID.......................................................................................................184
10.3 Digital Memory Commands.........................................................................................185
10.3.1 Digital Read..................................................................................................................185
10.3.2 Digital Write ..................................................................................................................185
10.3.3 Erase Memory ..............................................................................................................186
10.3.4 Chip Erase....................................................................................................................186
10.3.5 CHECKSUM.................................................................................................................187
10.4 Device Configuration Commands................................................................................187
10.4.1 PWR_UP –Power up...................................................................................................188
10.4.2 PWR_DN –Power Down..............................................................................................188
10.4.3 WR_CFG_REG –Write Configuration Register............................................................188
10.4.4 RD_CFG_REG –Read Configuration Register............................................................188
10.5 Device Power Up Sequence .......................................................................................189
11. ISD61S00 MEMORY MANAGEMENT.........................................................................................189
11.1 ISD61S00 Memory Format..........................................................................................189
11.2 Message Management................................................................................................190
11.2.1 Voice Prompts ..............................................................................................................191
11.2.2 Voice Macros................................................................................................................191
11.2.3 User Data .....................................................................................................................192
11.2.4 Reserved Sectors.........................................................................................................192
11.2.5 Message Recordings....................................................................................................192
11.3 Memory and Message Headers ..................................................................................193
11.3.1 Memory Header............................................................................................................193
11.3.2 Message Header ..........................................................................................................194
11.4 Digital Access of Memory............................................................................................194
11.5 Device Erase Commands............................................................................................195
11.6 Memory Contents Protection.......................................................................................195
12. DEVICE INITIALIZATION ............................................................................................................195
13. APPLICATION REFERENCE SCHEMATICS .............................................................................196
13.1 PCB Layout Guidelines ...............................................................................................196
14. PACKAGE SPECIFICATION.......................................................................................................199
14.1 LQFP48L (7x7x1.4mm footprint 2.0mm).....................................................................199
15. ELECTRICAL CHARACTERISTICS............................................................................................200
15.1 Absolute Maximum Ratings.........................................................................................200

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 9 - Revision 2.7
15.2 Operating Conditions...................................................................................................200
15.3 DC Parameters............................................................................................................201
15.4 Analog Transmission Characteristics..........................................................................202
15.5 Analog Distortion and Noise Parameters....................................................................202
15.5.1 8kHz sampling..............................................................................................................202
15.5.2 16kHz sampling............................................................................................................203
15.6 SPI Timing...................................................................................................................203
15.7 Recommended Clock/Crystal Specification ................................................................204
15.8 Dual Tone Alert Signal (CAS)......................................................................................205
15.9 FSK Detection –1200baud Bell 202, ITU V.23, 300 baud Bell 103, ITU V.21 ...........206
15.10 FSK Transmitter –Bell 202, ITU-V.23, Bell 103, ITU-V.21.........................................208
15.11 DTMF Detection ..........................................................................................................209
16. ORDERING INFORMATION........................................................................................................210
17. REVISION HISTORY...................................................................................................................211

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 10 - Revision 2.7
1. GENERAL DESCRIPTION
The ISD61S00 is a feature chip for the security and telephony industry. The device incorporates audio
storage with a powerful macro scripting ability to facilitate audio prompting in a multi-language
environment and simple address-free recording and playback. It utilizes external serial flash memory for
audio data storage. In addition, the device includes circuitry to perform telephony based data
communications including DTMF detection and generation, FSK modem functions from 75-1200 baud,
CAS and CPT (Call Progress Tone) detection and ring detection. The audio path of the device is
designed to interface to both the air side and line side of a PSTN system. The air side includes a flexible
microphone interface incorporating a bias generator and gain control and a differential analog output for
driving a speaker or power amplifier. The line side incorporates a line driver to drive PSTN loads and two
variable gain differential inputs. The audio path includes full and half-duplex acoustic and line echo
cancellation to implement full and half-duplex speakerphone functions. The digital audio interface can be
configured to I2S or PCM mode for digital serial audio communication. Control, monitoring and device
programming is perfomed via a SPI interface. The device package is LQFP-48L.
2. FEATURES
External Memory:
oThe ISD61S00 supports the following flash:
Manufacturer
Winbond
Numonyx
MXIC
Family
25X
25Q
25P
25PX
25PE
25L / 25V
JEDEC ID
EF 30 1X
EF 40 1X
20 20 1X
20 71 1X
20 80 1X
C2 20 1X
oThe addressing ability of ISD61S00 is up to 128Mbit, which is 64-minute record/playback
time based on 8kHz/4bit ADPCM.
Fast pre-recording: Recording is limited by the write rate of the attached external flash.
Operating voltage: 2.7-3.6V.
Sampling frequency: Recording and playback sampling frequencies of 4, 5.3, 6.4, 8, 10.6, 12.8
and 16 kHz.
Compression algorithm:
oFor record and playback:
oADPCM compression at 2, 3, 4 or 5 bits per sample.
oµ-Law companding at 6, 7 or 8 bits per sample.
oDifferential µ-Law encoding at 6, 7 or 8 bits per sample.
oPCM encoding at 8, 10 or 12 bits per sample.
For pre-recorded audio playback (Voice prompts) additionally:
oEnhanced ADPCM compression at 2, 3, 4 or 5 bits per sample.
oMulti-Bit rate optimized compression. This allows best possible compression given a
metric of SNR and background noise levels.
Message Management:
oSimple address free real-time recording.
oFlexible Voice Prompt message management and Voice Macro scripting for pre-recorded
messages.
External serial flash memory interface: Support up to 128Mbit for audio and digital data storage,
equivalent to 64 minutes based on 8khz 4bit ADPCM.
Digital access to flash memory: Memory can be reserved on a 4Kbyte sector basis for use as

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 11 - Revision 2.7
conventional digital memory by host.
Telephony/Modem/Data Features at 8KHz CODEC sampling rate:
oDTMF encoder with 20 digit dial string buffer.
oDTMF detector.
oFSK generation at 75/110/150/300/1200 baud for Bell 103, Bell 202, V.21 or V.23 modem
standards. Transmit FIFO to reduce host interaction.
oFSK detector at 75/110/150/300/1200 baud for Bell 103, Bell 202, V.21 or V.23 modem
standards with receive FIFO.
oRing Detector.
oCall Progress Tone (CPT) detector for detecting dial tones, busy tones etc.
oCAS detector for caller ID type I, type II implementation.
oArbitrary dual tone generator.
oArbitrary tone detector.
Acoustic Echo Cancellation (AEC), Line Echo Cancellation (LEC) and Automatic Gain Control
(AGC) for on-chip speakerphone support.
Up to 17 GPIO pins accessible through the SPI interface.
Audio Input:
oTI1 and TI2: Differential Analog inputs for PSTN interface (on-hook and off-hook).
oMIC+/-: Analog interface to microphone.
Audio Output:
oPO: Differential Analog output for PSTN interface.
oSPK: Differential output buffer for speaker driver.
I/O:
oSPI interface: MISO, MOSI, SCLK, SS for commands and digital audio data.
oINT and R/B signal for signaling and flow control.
Package: Green LQFP-48L
Temperature: -40C to 85C

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 12 - Revision 2.7
3. PIN CONFIGURATION
2
3
4
5
6
7
8
9
10
1
2
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
33
32
31
30
29
44 43 42 41 40 39 38 37
ISD61S00
36
35
34
47 46 4548
GPIO<13>/RDET
VSSD
DO/GPIO<0>
CLK/GPIO<1>
VDDL
XTALI
XTALO
VSSD
GPIO<14>/RDET
INTB
RESET
VCCD
GPIO<10> GPIO<12> GPIO<11>
GPIO<9>/SDI1
GPIO<8>/SDO1
GPIO<7>/SDI
GPIO<6>/SCK
GPIO<5>/WS
GPIO<4>/SDO
DI
CSB
AUXOUT
VSSA
VCCA
PO+
SPN
PO-
VBG
VMID
SPP
MCP
VSSA
MCGND
MCO
TI2N TI1P TI2P GPIO<15>/RDET GPIO<16>/RDET MISO SCLK SSB MOSI RDY_BSYB NC TI1N
Figure 3-1 ISD61S00 48-Lead LQFP Pin Configuration.

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 13 - Revision 2.7
4. PIN DESCRIPTION
Pin
Number
Pin Name
I/O
Function
Drive
1
RESET
I
Raising this pin to VCC will reset the chip.
N/A
2
INTB
O
Active low interrupt request pin. This pin has an
open drain output.
4/8mA
3
GPIO<14>/RDET
I/O*
General Purpose IO Pin or the Ring Detect input
(RDET).
4/8mA
4
VSSD
G
Digital Ground.
N/A
5
XTALOUT
O
Crystal Interface output pin.
N/A
6
XTALIN
I
Crystal interface input pin. It can also be used to
provide an external clock to the device.
N/A
7
VDDL
O
This pin has a nominal 1.8V output to supply the
internal logic. A 2.2nF capacitor should be
connected to this pin.
N/A
8
VCCD
P
Digital power supply pin
N/A
9
VSSD
G
Digital Ground.
N/A
10
GPIO<13>/RDET
I/O*
General Purpose IO Pin.
4/8mA
11
DO/GPIO<0>
I/O
Flash interface data out. Alternatively General
Purpose IO Pin.
4/8mA
12
CLK/GPIO<1>
I/O
Flash interface clock. Alternatively General Purpose
IO Pin.
4/8mA
13
CSB
O
Flash interface chip select bar.
4/8mA
14
DI
I
Flash interface data in.
4/8mA
15
GPIO<4>/SDO
I/O*
General Purpose IO Pin. Serial Data Out for the I2S
interface.
8/16mA
16
GPIO<5>/WS
I/O*
General Purpose IO Pin. Word Select (WS) output
for the I2S Interface
8/16mA
17
GPIO<6>/SCK
I/O*
General Purpose IO Pin. Serial Clock output for the
I2S Interface
8/16mA
18
GPIO<7>/SDI
I/O*
General Purpose IO Pin. Serial Data Input (SDI)
input pin for the I2S Interface.
8/16mA
19
GPIO<8>/SDO1
I/O*
General Purpose IO Pin. Secondary Serial Data Out
for the I2S interface.
4/8mA
20
GPIO<9>SDI1
I/O*
General Purpose IO Pin. Secondary Serial Data
Input (SDI) input pin for the I2S Interface.
4/8mA

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 14 - Revision 2.7
21
GPIO<10>
I/O*
General Purpose IO Pin.
4/8mA
22
GPIO<11>
I/O*
General Purpose IO Pin or the Ring Detect input
(RDET).
4/8mA
23
GPIO<12>
I/O*
General Purpose IO Pin.
4/8mA
24
AUXOUT
O
Auxiliary output from PSTN or SPEAKER DAC.
N/A
25
VSSA
G
Analog Ground Pin
N/A
26
SPKN
O
Negative speaker driver output
N/A
27
PO-
O
Negative line driver output
N/A
28
VCCA
P
Analog Power Pin
N/A
29
PO+
O
Positive line driver output
N/A
30
SPKP
O
Positive speaker driver output
N/A
31
VSSA
G
Analog Ground Pin
N/A
32
MCGND
I
Analog ground pin for MIC. This pin should be
connected to a quiet VSSA and used as the return
for microphones connected to MCP.
N/A
33
MCO
I/O
MIC feedback signal
N/A
34
MCP
I
Positive MIC signal input.
N/A
35
VBG
I/O
Voltage reference, a 100nF capacitor should be
connected to this pin.
N/A
36
VMID
I/O
Voltage reference, a 4.7uF capacitor should be
connected to this pin.
N/A
37
TI1P
I
PSTN Line #1 positive input
N/A
38
TI1N
I
PSTN Line #1 negative input
N/A
39
TI2P
I
PSTN Line #2 positive input
N/A
40
TI2N
I
PSTN Line #2 negative input
N/A
41
GPIO<15>/RDET
I/O*
General Purpose IO Pin. Can be configured as Ring
Detect (RDET) input.
4/8mA
42
GPIO<16>/RDET
I/O*
General Purpose IO Pin. Can be configured as Ring
Detect (RDET) input.
4/8mA
43
MISO
O
SPI slave serial data output from the ISD61S00 to
the host. This pin is tri-stated when SSB=1.
4/8mA
44
SCLK
I
SPI serial Clock input to the ISD61S00 from the
host.
N/A
45
SSB
I
Slave select input to the ISD61S00 from the host
N/A
46
MOSI
I
SPI slave serial data input to the ISD61S00 from the
host.
4/8mA

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 15 - Revision 2.7
47
RDY/BSYB
O
This pin is at VCCD when the chip is ready to
accept a new command/data and is at VSSD when
device is busy.
4/8mA
48
NC
* Default state for digital I/O pins is input with internal pull-up [38Kohms to 83Kohms] to VCCD supply

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 16 - Revision 2.7
5. BLOCK DIAGRAM
ADC
DAC
AEC

ADC
DAC
LEC
Compression
De-Compression
Flash Memory Controller
SPI Interface Memory Management and Command
Interpreter
SCLK
SSB
MISO MOSI
INTB
RDY/BSYB
MUX
and
MIX
MCP
MCO
PO
PO1P
TI1P
DTMF Detection
DTMF Generation
FSK Generation
FSK Detection
I2S Interface
SCK
WS
SDO
SDI
TI1 TI2
TI1N
TI2P
TI2N
PO1N
SPK
SPKP
SPKN
MIC
MCGND A
MIC BIAS
AUXOUT AUX
stage1 stage2
Figure 5-1 ISD61S00 Block Diagram

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 17 - Revision 2.7
6. CONFIGURATION REGISTER MAP
6.1 Configuration Register Groups
Data memory address
Size (Byte)
Function
Usage
ALL
0x000 ~ 0x0FF
256
Device Control Registers
0x110 ~ 0x13F
32
Gain stage and Mixer Control Registers
0x140 ~ 0x14F
16
Air CODEC Control
0x150 ~ 0x15F
16
Line CODEC Control
0x160 ~ 0x17F
32
FSK Encoder Control
0x180 ~ 0x19F
32
FSK Decoder Control
0x1A0 ~ 0x1AF
16
Ringer Tone(PWM) Control Registers
0x1B0 ~ 0x1BF
16
Ring Detection PPM Control
0x1CO ~ 0x1DF
32
DTMF and Tone Generation
0x1E0 ~ 0x1EF
16
DTMF Detection Control
0x1F0 ~ 0x1FF
16
Voice Energy Detection Control
0x200 ~ 0x27F
128
CAS Detection Control
0x280 ~ 0x28F
16
CPT Detector Control
0x290 ~ 0x29F
16
Timer Control
0x300 ~ 0x3FF
256
AEC/LEC Control
6.2 Register Map
Addr.
Name
Mode
Value
At
Reset
Function
0x000
AUD
R/W
0x64
Compression & SR ctrl
8.2.1
0x001
REG1
R/W
0x00
Compression Control
8.2.2
0x002
REG2
R/W
0x00
Compression Source
8.2.3
0x003
REG3
R/W
0x03
Clock Control
8.2.4
0x004
TI_GAIN
R/W
0x00
Input Amplifier Gain
8.8.1
0x005
TI_CTRL
R/W
0x00
Input Amplifier Control
8.8.2
0x006
MIC_CTRL
R/W
0x00
MIC Interface Control
8.7.1

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 18 - Revision 2.7
Addr.
Name
Mode
Value
At
Reset
Function
0x007
MIC_BIAS
R/W
0x00
MIC Interface Bias
8.7.2
0x008
ANA_OUT
R/W
0x00
Analog Output Control
8.9.1
0x009
ANA_CTRL
R/W
0x10
Analog Control
8.8.2
0x00A
ID_OVR
R/W
0x00
Memory Control
0x00B
PORT_CFG
R/W
0x00
GPIO INT Ctrl
8.5.1
0x00C
PORTA_IE
R/W
0x00
Port A INT Enable
8.5.2
0x00D
PORTB_IE
R/W
0x00
Port B INT Enable
8.5.2
0x00E
PORTC_IE
R/W
0x00
Port C INT Enable
8.5.2
0x00F
DPLL Control
R/W
0x00
Digital PLL Control
8.5.2
0x014
IE0
R/W
0xFF
INT Enable 0
8.5.3
0x015
IE1
R/W
0xFF
INT Enable 1
8.5.4
0x017
UPDATE_MD
R/W
0x01
Update Ctrl
8.2.5
0x018
CHK_SUM_CTRL
R/W
0x01
Check sum control
0x019
PORTA_DO
R/W
0x00
Port A Dout
8.5.5
0x01A
PORTA_OE
R/W
0x00
Port A Output Enable
8.5.6
0x01B
PORTA_PE
R/W
0xFF
Port A Pull Enable
8.5.7
0x01C
PORTA_DI
R
NA
Port A Din
8.5.8
0x01D
PORTA_PS
R/W
0xFF
Port A pull Select
8.5.9
0x01E
PORTA_DS
R/W
0x00
Port A Drive Strength
8.5.10
0x01F
PORTA_AF
R/W
0x03
Port A Alternate Function
8.5.11
0x020
R0_LSB
R/W
0x00
Indirect reg R0 LSB
8.6
0x021
R0
R/W
0x00
Indirect reg R0
8.6
0x022
R1_LSB
R/W
0x00
Indirect reg R1 LSB
8.6
0x023
R1
R/W
0x00
Indirect reg R1
8.6
0x024
R2_LSB
R/W
0x00
Indirect reg R2 LSB
8.6
0x025
R2
R/W
0x00
Indirect reg R2
8.6
0x026
R3_LSB
R/W
0x00
Indirect reg R3 LSB
8.6
0x027
R3
R/W
0x00
Indirect reg R3
8.6
0x028
R4_LSB
R/W
0x00
Indirect reg R4 LSB
8.6
0x029
R4
R/W
0x00
Indirect reg R4
8.6
0x02A
R5_LSB
R/W
0x00
Indirect reg R5 LSB
8.6
0x02B
R5
R/W
0x00
Indirect reg R5
8.6
0x02C
R6_LSB
R/W
0x00
Indirect reg R6 LSB
8.6
0x02D
R6
R/W
0x00
Indirect reg R6
8.6

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 19 - Revision 2.7
Addr.
Name
Mode
Value
At
Reset
Function
0x02E
R7_LSB
R/W
0x00
Indirect reg R7 LSB
8.6
0x02F
R7
R/W
0x00
Indirect reg R7
8.6
0x030
PORTB_DO
R/W
0x00
Port B Dout
8.5
0x031
PORTB_OE
R/W
0x00
Port B Output Enable
8.5
0x032
PORTB_PE
R/W
0xFF
Port B Pull Enable
8.5
0x033
PORTB_DI
R
NA
Port B Din
8.5
0x034
PORTB_PS
R/W
0xFF
Port B pull Select
8.5
0x035
PORTB_DS
R/W
0x00
Port B Drive Strength
8.5
0x036
PORTB_AF
R/W
0x00
Port B Alternate Function
8.5.11
0x037
PORTC_DO
R/W
0x00
Port C Dout
8.5
0x038
PORTC_OE
R/W
0x00
Port C Output Enable
8.5
0x039
PORTC_PE
R/W
0xFF
Port C Pull Enable
8.5
0x03A
PORTC_DI
R
NA
Port C Din
8.5
0x03B
PORTC_PS
R/W
0xFF
Port C pull Select
8.5
0x03C
PORTC_DS
R/W
0x00
Port C Drive Strength
8.5
0x03D
PORTC_AF
R/W
0xFC
Port C Alternate Function
8.5
0x040
PLL_CLK
R/W
0x20
PLL Clock Control
8.3.2
0x041
PLL_K2
R/W
0x00
PLL Fraction MSB
8.3.3
0x042
PLL_K1
R/W
0x00
PLL Fraction byte 1
8.3.3
0x043
PLL_K0
R/W
0x00
PLL Fraction LSB
8.3.3
0x044
PLL_CTRL
R/W
0x88
PLL Control Register
8.3.4
0x050
PCM_CFG
R/W
0x00
PCM Configuration
8.4.1
0x051
PCM_TSLOTL
R/W
0x01
Left Channel PCM MSB start
8.4.2
0x052
PCM_TSLOTR
R/W
0x11
Right Channel PCM MSB start
8.4.3
0x053
PCM_COMP0
R/W
0x00
PCM0 Compression
8.4.4
0x054
PCM_TSLOTL1
R/W
0x01
Left Channel PCM1 MSB start
8.4.5
0x055
PCM_TSLOTR1
R/W
0x11
Right Channel PCM1 MSB start
8.4.6
0x056
PCM_COMP1
R/W
0x00
PCM1 Compression
8.4.7
0x057
PCM_TX_SEL
R/W
0x00
PCM Transmission Select
8.4.8
0x058
PCM_RX_SEL
R/W
0x00
PCM Receive Select
8.4.9
0x059
CHKSUM SUM1 LSB
R
0x00
Chksum1[7:0]
0x05A
CHKSUM SUM1
R
0x00
Chksum1[15:8]
0x05B
CHKSUM SUM2 LSB
R
0x00
Chksum2[7:0]
0x05C
CHKSUM SUM2
R
0x00
Chksum2[15:8]

ISD61S00 DESIGN GUIDE
Publication Release Date: March 10, 2011
- 20 - Revision 2.7
Addr.
Name
Mode
Value
At
Reset
Function
0x05D
REC_MSG_LEN LSB
R/W
0x00
REC Message Sector Length [7:0]
0x05E
REC_MSG_LEN
R/W
0x00
REC Message Sector Length [15:8]
0x110
GS_CTRL
R/W
0x00
GS Control
0x111
GS_ACST
R/W
0x40
Air CODEC Side tone
0x112
GS_ACIG
R/W
0x00
Air CODEC input Gain
0x113
GS_ACOG
R/W
0x00
Air CODEC output Gain
0x114
GS_AEOG
R/W
0x00
AEC Output Gain
0x115
GS_AEIG
R/W
0x00
AEC Input Gain
0x116
GS_LCIG
R/W
0x00
Line CODEC input Gain
0x117
GS_LCOG
R/W
0x00
Line CODEC output Gain
0x118
GS_LEOG
R/W
0x00
LEC Output Gain
0x119
GS_LEIG
R/W
0x00
LEC Input Gain
0x11A
GS_AOAI
R/W
0x00
AEC out - AEC in Gain
0x11B
GS_LOAI
R/W
0x00
LEC out - AEC in Gain
0x11C
GS_PLAI
R/W
0x00
PLAY - AEC in Gain
0x11D
GS_ILAI
R/W
0x00
I2SL - AEC in
0x11E
GS_IRAI
R/W
0x00
I2SR - AEC in
0x11F
GS_AOLI
R/W
0x00
AEC out - LEC in Gain
0x120
GS_LOLI
R/W
0x00
LEC out - LEC in Gain
0x121
GS_PLLI
R/W
0x00
PLAY - LEC in Gain
0x122
GS_ILLI
R/W
0x00
I2SL - LEC in
0x123
GS_IRLI
R/W
0x00
I2SR - LEC in
0x124
GS_AORI
R/W
0x00
AEC out - REC in Gain
0x125
GS_LORI
R/W
0x00
LEC out - REC in Gain
0x126
GS_PLRI
R/W
0x00
PLAY - REC in Gain
0x127
GS_ILRI
R/W
0x00
I2SL - REC in
0x128
GS_IRRI
R/W
0x00
I2SR - REC in
0x129
GS_AOIL
R/W
0x00
AEC out - I2SL in Gain
0x12A
GS_LOIL
R/W
0x00
LEC out - I2SL in Gain
0x12B
GS_PLIL
R/W
0x00
PLAY - I2SL in Gain
0x12C
GS_ILIL
R/W
0x00
I2SL - I2SL in
0x12D
GS_IRIL
R/W
0x00
I2SR - I2SL in
0x12E
GS_AOIR
R/W
0x00
AEC out - I2SR in Gain
0x12F
GS_LOIR
R/W
0x00
LEC out - I2SR in Gain