Intel Agilex User manual

Intel® Agilex™ General Purpose I/O
and LVDS SERDES User Guide
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Contents
1. Intel® Agilex™ General Purpose I/O and LVDS SERDES Overview................................... 4
1.1. Intel Agilex I/O and Differential I/O Buffers...............................................................4
1.2. Package Selection and I/O Vertical Migration Support................................................. 5
1.3. I/O Banks.............................................................................................................5
2. Intel Agilex I/O Features and Usage...............................................................................8
2.1. GPIO Features.......................................................................................................8
2.1.1. Supported I/O Standards............................................................................8
2.1.2. Intel Agilex I/O Buffer Behavior................................................................. 10
2.1.3. I/O Standards Restrictions and Implementation Guidelines............................ 10
2.2. Programmable I/O Element (IOE) Features in Intel Agilex Devices.............................. 11
2.2.1. Programmable Output Slew Rate Control.....................................................15
2.2.2. Programmable IOE Delay.......................................................................... 15
2.2.3. Programmable Open-Drain Output..............................................................15
2.2.4. Programmable Bus Hold............................................................................16
2.2.5. Programmable Pull-Up Resistor.................................................................. 16
2.2.6. Programmable Pre-Emphasis..................................................................... 16
2.2.7. Programmable De-Emphasis......................................................................17
2.2.8. Programmable Differential Output Voltage................................................... 18
3. Intel Agilex I/O Termination........................................................................................ 19
3.1. 1.5 V True Differential Signaling I/O Termination...................................................... 19
3.1.1. External I/O Termination...........................................................................20
3.1.2. 1.5 V True Differential Signaling I/O Standard OCT Termination......................20
3.2. Single-Ended I/O Termination in Intel Agilex Devices................................................ 21
3.2.1. Single-Ended I/O Standard OCT Termination................................................21
3.2.2. OCT Calibration Block............................................................................... 25
3.2.3. Single-Ended I/O Standards External Termination ........................................26
4. Intel Agilex I/O Design Guidelines............................................................................... 29
4.1. Placement Requirements.......................................................................................29
4.2. Special Pins Requirement...................................................................................... 29
4.3. External Memory Interface Pin Placement Requirements............................................30
4.4. HPS Shared I/O Requirements............................................................................... 31
4.5. SDM Shared I/O Requirements.............................................................................. 31
4.6. Configuration Pins................................................................................................31
4.7. Unused Pins........................................................................................................ 31
4.8. Guidelines for GPIO Pins During Power Sequencing...................................................32
4.9. Maximum DC Current Restrictions.......................................................................... 32
4.10. 1.2 V I/O Interface Voltage Level Compatibility...................................................... 32
4.11. I/O Simulation...................................................................................................34
4.11.1. HSPICE Models...................................................................................... 34
5. Intel Agilex High-Speed SERDES I/O Architecture........................................................ 35
5.1. Intel Agilex High-Speed SERDES I/O Overview.........................................................35
5.1.1. High-Speed SERDES Architecture............................................................... 35
5.1.2. Intel Agilex GPIO Banks, SERDES, and DPA Locations................................... 38
5.2. Intel Agilex LVDS SERDES Transmitter.................................................................... 39
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5.2.1. LVDS SERDES Transmitter Blocks............................................................... 39
5.2.2. Serializer Bypass for DDR and SDR Operations.............................................39
5.2.3. Serializer................................................................................................ 40
5.2.4. Differential I/O Bit Position........................................................................41
5.2.5. Clocking Differential Transmitters............................................................... 42
5.3. Intel Agilex LVDS SERDES Receiver........................................................................ 42
5.3.1. LVDS SERDES Receiver Blocks................................................................... 42
5.3.2. Clocking LVDS SERDES Receivers...............................................................47
5.3.3. LVDS SERDES Receiver Modes .................................................................. 47
5.4. Intel Agilex LVDS SERDES Source-Synchronous Timing Budget.................................. 50
5.4.1. Transmitter Channel-to-Channel Skew........................................................ 50
5.4.2. Receiver Skew Margin ..............................................................................51
5.5. Intel Agilex LVDS SERDES Timing.......................................................................... 52
5.5.1. I/O Timing Analysis..................................................................................53
5.6. Intel Agilex LVDS SERDES Design Guidelines........................................................... 53
5.6.1. Use High-Speed Clock from PLL to Clock SERDES Only..................................53
5.6.2. Pin Placement for Differential Channels....................................................... 54
5.6.3. SERDES Pin Pairs for Soft-CDR Mode.......................................................... 54
6. Documentation Related to the Intel Agilex General Purpose I/O and LVDS SERDES
User Guide............................................................................................................... 55
7. Document Revision History for the Intel Agilex General Purpose I/O and LVDS
SERDES User Guide..................................................................................................56
Contents
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1. Intel® Agilex™ General Purpose I/O and LVDS SERDES
Overview
The Intel® Agilex™ I/O system includes a general purpose I/O (GPIO) interface, a
Secure Device Manager (SDM) I/O interface and a Hard Processor System (HPS) I/O
interface. Each I/O interface is designed to meet different interfacing requirements.
The General Purpose I/O interface system can support:
• 1.2 V single-ended non-voltage referenced Joint Electron Device Engineering
Council (JEDEC) compliant I/O standards.
• 1.2 V single-ended and differential voltage referenced JEDEC compliant I/O
standards.
• 1.5 V true differential I/O compatible with LVDS, RSDS, Mini-LVDS, and LVPECL
I/O standards.
• DDR4 memory interface up to 1600 MHz with a Hard Memory Controller (HMC).
• LVDS serializer/deserializer (SERDES) interface up to 1.6 Gbps.
The SDM and HPS I/O interfaces can support 1.8 V single-ended non-voltage
referenced I/O standard for SDM and HPS interfacing.
Related Information
Intel Agilex Data Sheet
1.1. Intel Agilex I/O and Differential I/O Buffers
The I/O bank within the GPIO interface supports differential and single-ended I/O
standards. The GPIO bank has true differential I/O buffers using the 1.5 V True
Differential Signaling I/O standard, which is compatible with the LVDS, RSDS, Mini-
LVDS, and LVPECL I/O standards. The true differential buffer forms a pair of
unidirectional true differential channels. Half of the true differential channels support
dedicated transmitter pins and the other half support dedicated true receiver pins.
Refer to the device pin-out files for locations of dedicated receiver and transmitter
channels.
Differential voltage referenced output pins are not true differential output pins. The
differential voltage referenced I/O standards use two single-ended output pins where
one of the output pins is inverted.
The I/O bank within the HPS and SDM interfaces supports single-ended IO standard.
Different power supplies power the Intel Agilex I/O buffer:
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Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

•VCCIO_PIO and VCCPT power the I/O buffers located in the I/O bank within the
GPIO interface.
•VCCIO_SDM powers the I/O buffers located in the I/O bank within the SDM I/O
interface.
•VCCIO_HPS powers the I/O buffers located in the HPS I/O bank within the HPS
I/O interface.
Each I/O bank within the interface has its own VCCIO power supply and supports only
one VCCIO voltage. The supported I/O standards vary between interfaces. Refer to
Supported I/O Standards for the list of I/O standards supported by each I/O interface.
1.2. Package Selection and I/O Vertical Migration Support
Figure 1. Migration Capability Across Intel Agilex Product Lines—Preliminary
• The arrows indicate the migration paths. The shades represent the devices
included in each vertical migration path.
• To achieve full I/O migration across product lines in the same migration path,
restrict I/Os and transceivers utilization to match the product line with the lowest
I/O and transceiver counts.
• Different device packages have a different number of I/O banks. Refer to the
device pin-out files for the total number of I/O banks available for each device
package.
F894A
Package
R1681A R1957A R2280A R3343A R3803A R2068A R2486A R2486B
Variant
AGF 004
Product Line
F-Series
AGF 006
AGF 008
AGF 012
AGI 022
AGI 027
I-Series
AGF 014
AGF 022
AGF 027
R2979A
1.3. I/O Banks
There are three types of I/O banks available in the Intel Agilex I/O interface system:
• GPIO banks
• HPS I/O bank
• SDM I/O bank
In each GPIO bank, there are two sub-banks. The top sub-bank is placed near the
edge of the die, and the bottom sub-bank is placed near the FPGA core.
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In each sub-bank, there are four I/O lanes with 12 I/O pins in each lane that make up
a total of 48 single-ended I/O pins or 24 true differential I/O pairs per sub-bank. Each
I/O lane supports three differential receiver input buffer pairs with SERDES and
dynamic phase alignment (DPA) channels and three differential transmitter output
buffer pairs with SERDES channels.
Other than the I/O lanes, SERDES and DPA, each I/O sub-bank also contains
dedicated circuitries including I/O PLL, hard memory controller and OCT calibration
blocks.
The total bank count in a GPIO bank varies across different device packages. Certain
GPIO banks are shared with the SDM and HPS function blocks. Refer to the device pin-
out files for available GPIO banks, GPIO and SDM shared I/O banks, and GPIO and
HPS shared I/O banks per package.
The HPS I/O bank consists of 48 I/O pins. These pins are used for HPS clocks,
peripherals, mass storage flash and JTAG.
The SDM I/O bank consists of 24 dedicated pins for device configuration purposes.
Refer to the device pin-out files for the dedicated function of each pin in the SDM I/O
bank.
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Figure 2. Intel Agilex I/O Bank Structure (Bottom View)
This diagram shows the I/O bank structure of Intel Agilex AGF 012 and AGF 014 devices.
2A
HPS 3D 3C 3B 3A
2B2C
2D SDM
OCT
OCT
I/O PLL I/O VR
I/O PLL I/O VR
Hard Memory
Controller
Hard Memory
Controller
I/O Center
I/O Center
I/O Lane I/O Lane
I/O Lane I/O Lane
I/O Lane I/O Lane
I/O Lane I/O Lane
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SDM Shared
GPIO Bank
HPS Shared
GPIO Bank
GPIO Bank SDM I/O Bank
HPS I/O Bank
Top Sub-BankBottom Sub-Bank
Different device packages have a different number of I/O banks. Refer to the device pin-out files for available bank location for each device package.
Top I/O bank Row
Bottom I/O bank Row
2A
HPS 3D 3C 3B
2B2C
2D
Top I/O bank Row
Bottom I/O bank Row
3A
SDM
Top Sub-Bank Bottom Sub-Bank
Differential RX buffer pair
Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
OCT
OCT
I/O PLL I/O VR
I/O PLL I/O VR
Hard Memory
Controller
Hard Memory
Controller
I/O Center
I/O Center
I/O Lane I/O Lane
I/O Lane I/O Lane
I/O Lane I/O Lane
I/O Lane I/O Lane
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair Differential RX buffer pair Differential TX buffer pair
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
SERDES & DPA
SERDES
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2. Intel Agilex I/O Features and Usage
The I/O buffers in Intel Agilex devices provide the following features:
• Single-ended non-voltage referenced and voltage referenced I/O standards
• Differential voltage-referenced I/O standards
• True differential transmitters and receivers
• Serializer/deserializer (SERDES)
• Programmable slew rate
• Programmable bus-hold
• Programmable weak pull-up resistor
• Programmable differential output voltage (VOD)
• Programmable open-drain output
• On-chip series termination (RS OCT) with and without calibration
• On-chip parallel termination (RT OCT)
• On-chip differential termination (RD OCT)
• Dynamic on-chip parallel termination
• Internally generated VREF with DDR4 calibration
• Programmable pre-emphasis for true differential output buffer
• Programmable de-emphasis for voltage-referenced /O standards
2.1. GPIO Features
2.1.1. Supported I/O Standards
VCCIO_PIO, VCCPT, and VCC power supplies power the Intel Agilex GPIO buffers. The
VCCIO_SDM power supply powers the SDM I/O buffer and the VCCIO_HPSpower
supply powers the HPS I/O buffer. Each I/O bank has its own power supply and
supports only one I/O voltage.
The following table shows the supported I/O standards for GPIO, HPS, and SDM I/O
banks:
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Table 1. Intel Agilex I/O Standards Support per I/O Bank Type
The 1.5 V True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL
standards at lower signal swing. Refer to Intel Agilex Device Data Sheet for the electrical specifications of the
1.5 V True Differential Signaling I/O standard.
I/O Standard GPIO Bank HPS I/O Bank SDM I/O Bank
1.8 V LVCMOS No Yes Yes
1.2 V LVCMOS Yes No No
SSTL-12 Yes No No
HSTL-12 Yes No No
POD12 Yes No No
Differential SSTL-12 Yes No No
Differential HSTL-12 Yes No No
Differential HSUL-12 Yes No No
Differential POD12 Yes No No
1.5 V True Differential
Signaling
Yes No No
Table 2. Intel Agilex GPIO Bank Supported I/O Standards
I/O Standard VCCIO_PIO
(V)
VCCPT (V) Vref (V) VTT (V) Application JEDEC
Standard
1.2 V LVCMOS 1.2 1.8 - - General
purpose
JESD-12A.01
SSTL-12 1.2 1.8 0.6 0.6 DDR4,
RLDRAM3,
QDR-IV
JESD79-4B
HSTL-12 1.2 1.8 0.6 0.6 QDR-IV JESD-16A
HSUL-12 1.2 1.8 0.6 - LPDDR3 JESD209-3C
POD12 1.2 1.8 Internally
calibrated
1.2 DDR4, QDR-IV JESD79-4B
Differential
SSTL-12(1)
1.2 1.8 - 0.6 RLDRAM3 JESD79-4B
Differential
HSTL-12(1)
1.2 1.8 - 0.6 General
purpose
JESD8-16A
Differential
HSUL-12(1)
1.2 1.8 - - LPDDR3 JESD209-3C
Differential
POD-12(1)
1.2 1.8 Internally
calibrated
1.2 DDR4 JESD79-4B
1.5 V True
Differential
Signaling
1.5 1.8 - - SGMII, SFI,
SPI
-
Related Information
Special Pins Requirement on page 29
(1) Uses two single-ended outputs with second output programmed as inverted.
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2.1.2. Intel Agilex I/O Buffer Behavior
All I/O pins in the GPIO bank are configured as tri-stated with weak pull-up enabled
during device power up and device configuration. During device power down, all I/O
pins are in undetermined state and pin signal is measured between GND to
VCCIO_PIO level.
Input signals of an I/O pin at any point should not exceed the maximum DC input
voltage specification as specified in the Intel Agilex Device Data Sheet.
2.1.3. I/O Standards Restrictions and Implementation Guidelines
Observe the following I/O standard restrictions and implementation guidelines to
ensure the success of your design. Unless noted otherwise, these guidelines apply to
all variants of the Intel Agilex device family.
2.1.3.1. Guidelines: VREF Sources and VREF Pins
Consider the following VREF pins guidelines:
• Intel Agilex devices support internal and external VREF sources.
—There is an external VREF pin for every I/O bank, providing one external VREF
source for all I/Os in the same bank.
— Each I/O lane in the bank also has its own internal VREF generator. You can
configure each I/O lane independently to use its internal VREF or the I/O bank's
external VREF source. All I/O pins in the same I/O lane use the same VREF
source.
• You can use the internal VREF with calibration to support DDR4 using the POD12
I/O standard.
•You can place any combination of input, output, or bidirectional pins near VREF
pins. There is no VREF pin placement restriction.
•The VREF pins are dedicated for voltage-referenced single-ended I/O standards.
You cannot use the VREF pins as user I/Os.
•Connect unused VREF pins to GND.
The VREF pin leakage current is typically 0.15 uA, and can go up to 4.1 uA.
2.1.3.2. Guidelines: I/O Standards Implementation based on VCCIO_PIO
Voltages
The following guidelines apply to I/O standards based on the VCCIO_PIO voltages.
1.2 V VCCIO_PIO
When using 1.2 V VCCIO_PIO, you can implement singled-ended non-voltage-
referenced and voltage-referenced I/O standards. This buffer also supports differential
voltage-referenced I/O standards with this voltage. You can implement a mix of both
voltage-referenced and non-voltage-referenced I/O standards within the I/O bank.
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1.5 V VCCIO_PIO
When using 1.5 V VCCIO_PIO voltage, you can only implement true differential I/O
standards. The buffer can interface with upstream or downstream devices that are
compatible with the electrical specification of Intel Agilex devices, specified in the Intel
Agilex Device Data Sheet. Analyze the electrical specification requirement to
implement your true differential receiver. Implement DC coupling when the signal
swing and offset voltage requirement is bounded within the Intel Agilex 1.5 V True
Differential Signaling standard specification. Otherwise, implement AC coupling and
external bias circuitry.
Related Information
Intel Agilex Data Sheet
2.2. Programmable I/O Element (IOE) Features in Intel Agilex
Devices
The SDM and HPS I/O buffers in the Intel Agilex devices support different I/O
standards and programmable I/O features than the general purpose I/O buffers. The
following tables list the supported I/O standards and features by each I/O bank.
Table 3. Programmable IOE Feature Settings for Intel Agilex GPIO Bank
I/O
Standard
Programmable IOE Feature
Slew Rate
Control
I/O
Delay
Open-Drain
Output
Bus-Hold Weak Pull-
up Resistor
Pre-
Emphasis
De-Emphasis Differential
Output
Voltage
1.2 V
LVCMOS
• Fast
(Default)
• Medium
• Slow
Refer
to
data
sheet
• Off
(Default)
• On
• Off
(Default)
• On
• Off
(Default)
• On
— — —
SSTL-12 • Fast
(Default)
• Medium
• Slow
Refer
to
data
sheet
— — — — • Off
(Default)
• Low
• Medium
• High
• Low
constant
impedance
• Medium
constant
impedance
• High
constant
impedance
—
HSTL-12 • Fast
(Default)
• Medium
• Slow
Refer
to
device
data
sheet
— — — — • Off
(Default)
• Low
• Medium
• High
—
continued...
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I/O
Standard
Programmable IOE Feature
Slew Rate
Control
I/O
Delay
Open-Drain
Output
Bus-Hold Weak Pull-
up Resistor
Pre-
Emphasis
De-Emphasis Differential
Output
Voltage
• Low
constant
impedance
• Medium
constant
impedance
• High
constant
impedance
HSUL-12 • Fast
(Default)
• Medium
• Slow
Refer
to
device
data
sheet
— — — — • Off
(Default)
• Low
• Medium
• High
• Low
constant
impedance
• Medium
constant
impedance
• High
constant
impedance
—
POD-12 • Fast
(Default)
• Medium
• Slow
Refer
to
device
data
sheet
— — — — • Off
• Low
• Medium
• High
(Default)
—
Differential
SSTL-12
• Fast
(Default)
• Medium
• Slow
Refer
to
device
data
sheet
— — — — • Off
(Default)
• Low
• Medium
• High
• Low
constant
impedance
• Medium
constant
impedance
• High
constant
impedance
—
Differential
HSTL-12
• Fast
(Default)
• Medium
• Slow
Refer
to
device
data
sheet
— — — — • Off
(Default)
• Low
• Medium
• High
—
continued...
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I/O
Standard
Programmable IOE Feature
Slew Rate
Control
I/O
Delay
Open-Drain
Output
Bus-Hold Weak Pull-
up Resistor
Pre-
Emphasis
De-Emphasis Differential
Output
Voltage
• Low
constant
impedance
• Medium
constant
impedance
• High
constant
impedance
Differential
HSUL-12
• Fast
(Default)
• Medium
• Slow
Refer
to
device
data
sheet
— — — — • Off
(Default)
• Low
• Medium
• High
• Low
constant
impedance
• Medium
constant
impedance
• High
constant
impedance
—
Differential
POD12
• Fast
(Default)
• Medium
• Slow
Refer
to
device
data
sheet
— — — — • Off
• Low
• Medium
• High
(Default)
—
1.5 True
Differential
Signaling
— Refer
to
device
data
sheet
— — — Off, Low
power
(Default),
Constant
impedance
— • Low
• Medium
low
• Medium
high
(Default)
• High
Table 4. Programmable IOE Feature Settings for Intel Agilex HPS I/O Bank
I/O Standard Programmable IOE Feature
Current Strength Slew Rate Weak Pull-up/
Pull-down
Schmitt
Trigger/TTL
Input
Open Drain
1.8 V LVCMOS • 2 mA
• 4 mA
• 6 mA
• 8 mA (Default)
• Slow
• Fast (Default)
• Disable
• Weak pull-up
with 20 kOhm
resistor
(Default)
• Weak pull-up
with 50 kOhm
resistor
• Weak pull-up
with 80 kOhm
resistor
• Schmitt
Trigger
(Default)
• TTL
• Enable
• Disable
(Default)
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I/O Standard Programmable IOE Feature
Current Strength Slew Rate Weak Pull-up/
Pull-down
Schmitt
Trigger/TTL
Input
Open Drain
• Weak pull-
down with 20
kOhm resistor
• Weak pull-
down with 50
kOhm resistor
• Weak pull-
down with 80
kOhm resistor
Table 5. Intel Agilex Configuration Pin I/O Standards and Features
Configuration Pin
Function
Location Direction I/O Standard Drive
Strength
(mA)
Weak Pull-Up/Pull-
Down
TDO SDM I/O
bank
Output 1.8 V LVCMOS 8 Weak pull-up
TMS SDM I/O
bank
Input Schmitt Trigger Input — Weak pull-up
TCK SDM I/O
bank
Input Schmitt Trigger Input — Weak pull-down
TDI SDM I/O
bank
Input Schmitt Trigger Input — Weak pull-up
nSTATUS SDM I/O
bank
Output 1.8V LVCMOS 8 Weak pull-up
OSC_CLK_1 SDM I/O
bank
Input Schmitt Trigger Input — Weak pull-down
nCONFIG SDM I/O
bank
Input Schmitt Trigger Input — Weak pull-up
SDM_IO[0],SDM_IO[8]
, SDM_IO[16]
SDM I/O
bank
I/O Schmitt Trigger Input or
1.8 V LVCMOS
8 Weak pull-down
SDM_IO[7:1],SDM_IO[
15:9]
SDM I/O
bank
I/O Schmitt Trigger Input or
1.8 V LVCMOS
— Weak pull-up
AVST_CLK SDM
Shared
GPIO bank
Input 1.2 V LVCMOS — —
AVST_READY SDM
Shared
GPIO bank
Output 1.2 V LVCMOS Series 34
ohm on-
chip
termination
(OCT)
—
continued...
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Configuration Pin
Function
Location Direction I/O Standard Drive
Strength
(mA)
Weak Pull-Up/Pull-
Down
without
calibration(
2)
AVST_VALID SDM
Shared
GPIO bank
Input 1.2 V LVCMOS — —
AVST_DATA SDM
Shared
GPIO bank
Input 1.2 V LVCMOS — —
2.2.1. Programmable Output Slew Rate Control
Each I/O pin contains a slew rate control, allowing you to specify the slew rate on a
pin-by-pin basis. The slew rate control affects both the rising and falling edges of the
signal.
You can select between three slew rate settings: Fast, Medium, and Slow.
• The Fast slew rate provides high-speed transitions for high-performance systems.
This is the default setting.
• The Slow slew rate reduces system noise and crosstalk but adds a nominal delay
to the rising and falling edges.
• Enable the DQS DLL in the same lane when you use a medium or slow slew rate
for voltage referenced I/O standards
2.2.2. Programmable IOE Delay
You can activate the programmable IOE delays to ensure zero hold time, minimize
setup time, or increase clock-to-output time. This feature helps read and write timing
margins because it minimizes the uncertainties between signals in the bus.
Each pin can have a different input delay from pin-to-input register or a delay from
output register-to-output pin values. This is to ensure that the signals within a bus
have the same delay going into or out of the device.
For more information about the programmable IOE delay specifications, refer to the
device data sheet.
Related Information
Intel Agilex Data Sheet
2.2.3. Programmable Open-Drain Output
Intel Agilex devices support open drain output on 1.2 V LVCMOS I/O standard. The
programmable open-drain output provides a high-impedance state on output when
logic to the output buffer is high. If logic to the output buffer is low, output is low.
(2) Slow slew rate signal
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You can attach several open-drain outputs to a wire. This connection type is like a
logical OR function, and is commonly called an active-low wired-OR circuit. If at least
one of the outputs is in logic 0 state (active), the circuit sinks the current and brings
the line to low voltage.
You can use open-drain output if you are connecting multiple devices to a bus. For
example, you can use the open-drain output for system-level control signals that can
be asserted by any device or as an interrupt.
Do not pull the output voltage higher than the VI (DC) level. Intel recommends that
you perform HSPICE simulation to verify the output voltage in your selected topology.
Ensure the output voltage meets the VIH and VIL requirements of the receiving
device.
2.2.4. Programmable Bus Hold
Intel Agilex devices support the programmable bus hold feature on 1.2 V LVCMOS
output. Each I/O pin provides an optional bus-hold feature that is active only after
configuration. When the device enters user mode, the bus-hold circuit captures the
value that is present on the pin by the end of the configuration.
The bus-hold circuitry uses a resistor to weakly pull the signal level to the last-driven
state of the pin. The bus-hold circuitry holds this pin state until the next input signal is
present. Therefore, you do not require an external pull-up or pull-down resistor to
hold a signal level when the bus is tri-stated.
For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-
driven pins away from the input threshold voltage—where noise can cause unintended
high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives
the voltage level of the I/O pin lower than the VCCIO_PIO level.
If you enable the bus-hold feature, you cannot use the programmable pull-up option.
2.2.5. Programmable Pull-Up Resistor
Intel Agilex devices support programmable pull up resistor on 1.2 V LVCMOS I/O. Each
I/O pin provides an optional programmable pull-up resistor during user mode.
The programmable pull-up resistor feature is enabled by default on unused I/O for
both 1.2 V and 1.5 V VCCIO_PIO. The pull-up resistor weakly holds the I/O to the
VCCIO_PIO level.
If you enable the weak pull-up resistor, you cannot use the bus-hold feature.
2.2.6. Programmable Pre-Emphasis
The VOD setting and the output impedance of the driver set the output current limit of
a high-speed transmission signal. At a high frequency, the slew rate may not be fast
enough to reach the full VOD level before the next edge, producing pattern-dependent
jitter. With pre-emphasis, the output current is boosted momentarily during switching
to increase the output slew rate.
Pre-emphasis increases the amplitude of the high-frequency component of the output
signal, and thus helps to compensate for the frequency-dependent attenuation along
the transmission line. The overshoot introduced by the extra current happens only
during a change of state switching to increase the output slew rate, and does not ring,
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unlike the overshoot caused by signal reflection. The amount of pre-emphasis required
depends on the attenuation of the high-frequency component along the transmission
line.
Figure 3. Programmable Pre-Emphasis
This figure shows the true differential output with pre-emphasis.
OUT
OUT
VOD
VP
VP
Voltage boost
from pre-emphasis
Differential output
voltage (peak–peak)
2.2.7. Programmable De-Emphasis
The programmable de-emphasis feature is supported for all voltage-reference I/O
standards. This feature supports a two-taps de-emphasis implementation, which
consists of a main tap and a 1-UI delayed post tap.
When using this feature, the height of the I/O signal is attenuated whenever a symbol
is longer than one UI. This feature supports two types of de-emphasis:
• Constant impedance—available for single-ended and differential SSTL-12,
HSTL-12, and HSUL-12 I/O standards.
• Low power (non-constant impedance)—available for single-ended and differential
SSTL-12, HSTL-12, HSUL-12, and POD12 I/O standards.
Each of the de-emphasis has three equalization settings - low, medium, and high.
Constant impedance de-emphasis has double effective equalization level of the low
power de-emphasis.
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Figure 4. Programmable De-emphasis
This figure shows the SSTL and HSTL standards with de-emphasis enabled.
VCCIO/2
1 0 0 0
LOW
HIGH
01 011
HIGH
LOW
1 1 0 0
10 0
1 UI
2.2.8. Programmable Differential Output Voltage
The programmable VOD settings allow you to adjust the output eye opening to
optimize the trace length and power consumption. A higher VOD swing improves
voltage margins at the receiver end, and a smaller VOD swing reduces power
consumption. You can statically adjust the VOD of the differential signal by changing
the VOD settings in the software Assignment Editor.
Figure 5. Differential VOD
This figure shows the VOD of the true differential output.
Single-Ended Waveform
Positive Channel (p)
Negative Channel (n)
Ground
Differential Waveform
p - n = 0 V
VCM
VOD
VOD
VOD
VOD (diff peak - peak) = 2 x VOD (single-ended)
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3. Intel Agilex I/O Termination
3.1. 1.5 V True Differential Signaling I/O Termination
All GPIO banks have dedicated circuitry to support true differential I/O standards by
using the 1.5 V True Differential Signaling differential buffers without resistor
networks. The 1.5 V True Differential Signaling buffer is compatible with the LVDS,
RSDS, Mini-LVDS, and LVPECL standards ,and supports 100 Ω differential on-chip
termination (RD OCT).
Figure 6. 1.5 V True Differential Signaling I/O Standard Termination
Differential Outputs Differential Inputs
Differential Outputs Differential Inputs
50 Ω
100 Ω
50 Ω
50 Ω
100 Ω
50 Ω
1.5 V True Differential SignalingTermination
Receiver
OCT
External
On-Board
Termination
OCT Receiver
(True LVDS
Output)
Use OCT with these I/O standards to save board space and cost. OCT reduces the
number of external termination resistors usage. Refer to Intel Agilex device pin-out
files for more information on the dedicated differential transmitter and receiver pins.
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Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
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accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
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Registered

3.1.1. External I/O Termination
Use AC coupling and external voltage bias circuitry if the common-mode voltage of the
output buffer does not match the differential receiver input common-mode voltage.
For information about the VICM specification, refer to the device data sheet.
Note: Intel recommends that you use SPICE models to verify your AC/DC-coupled
termination.
Figure 7. AC-Coupled External Termination
Z0= 50 Ω VICM
Z0= 50 Ω 50 Ω
50 Ω
0.1 µF
0.1 µF
True DIfferential
Transmitter
True DIfferential
Receiver
3.1.2. 1.5 V True Differential Signaling I/O Standard OCT Termination
All I/O pins and dedicated clock input pins in Intel Agilex devices support on-chip
differential termination, RD OCT. The Intel Agilex devices provide a 100 ±40 Ω, on-
chip differential termination option on each differential receiver channel for 1.5 V True
Differential Signaling I/O standards.
Figure 8. OCT for Differential I/O Termination
Differential Receiver
with On-Chip 100 Ω
Termination
Differential
Transmitter
Z0= 50 Ω
Z0= 50 Ω
RD
3.1.2.1. Differential Input RD OCT Restrictions and Guidelines
For interfaces which require external voltage bias circuitry near the Intel Agilex
device's true differential receiver, you must disable the OCT RD.
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