STC STC12C5A Series User manual

STC TECHNOLOGY Co.,Ltd.
STC12C5A08/16/32/60
8-bit micro-controller
This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this
product without notice. 2007/12 version A1
Features.............................................................................................................................3
General Description..........................................................................................................4
Order Information:............................................................................................................4 
Pin Description..................................................................................................................5
Pin Definition............................................................................................................5
Pin Configuration......................................................................................................7
Block Diagram..................................................................................................................9
Address Map...........................................................................................................10
Bits Description ......................................................................................................11
Memory...........................................................................................................................13
Organization............................................................................................................13
RAM .......................................................................................................................13
Embedded Flash......................................................................................................14
ALE OUTPUT................................................................................................................15
Functional Description....................................................................................................17
I/O Port Configuration............................................................................................17
Timer/Counter.........................................................................................................21
BAUD-RATE GENERATOR(BRT).......................................................................25
Interrupt...................................................................................................................27
Watch Dog Timer....................................................................................................34
Universal Asynchronous Serial Port (UART).........................................................36
Secondary Universal Asynchronous Serial Port (S2) .............................................40
Programmable Counter Array (PCA)......................................................................45
Serial Peripheral Interface(SPI)..............................................................................55
Analog to Digital Converter....................................................................................63
Power Management ................................................................................................66
In System Programming and InApplication Programming....................................69
In System Programming (ISP)................................................................................69
In-Application Program (IAP)................................................................................72
Instructions Set................................................................................................................72
Absolute Maximum Rating (STC12C5Axx)..................................................................75
DC Characteristics (STC12C5Axx)................................................................................75
Absolute Maximum Rating (STC12LE5Axx)................................................................76
DC Characteristics (STC12LE5Axx) .............................................................................76
Package Dimension.........................................................................................................77
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2 STC12C5Axx Technical Summary
Version History ...............................................................................................................78
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STC12C5Axx Technical Summary 3
Features
zEnhanced 80C51 Central Processing Unit
z3.3V/5V operation voltage, built-in Low-Voltage Detector and Reset circuit
zOperation frequency range up to 25MHz
zMax 64K bytes on-chip flash memory with ISP/IAP capability
z256 byte scratch-pad RAM and 1024 bytes of auxiliary RAM
zTwo-level code protection for flash memory access
zTwo 16-bit timer/counter
z10 sources, 4-level-priority interrupt capability
zSecondary UART2 with self baud-rate generator
zOne enhanced UART with automatic address recognition and frame error detection
zSPI Master/Slave communication interface
z15 bits Watch-Dog-Timer with 8-bit pre-scalar, one-time enabled
zTwo Channel Programmable Counter Array (PCA)
z10-bit Analog-to-Digital Converter (ADC)
zPower control: idle mode and power-down mode, Power-down can be woken-up through
INT0 and INT1
z44(max) programmable I/O ports
zAlternative built-in 6MHz oscillator
zFully static operation
zExcellent noise immunity
zVery low power consumption
zPackage type:
-PDIP-40:
-LQFP-44
-PQFP-44
-PLCC-44
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4 STC12C5Axx Technical Summary
General Description
STC12C5Axx is a single-chip 8-bit micro-controller with instruction sets fully compatible with
industrial-standard 80C51 series micro controller.
There is very excellent MCU kernel built in this device compared to general 80C51 MCUs
those take twelve oscillating cycles to finish an instruction, the device could take only one
oscillating cycle to finish one instruction.
There is 8K(max) bytes flash memory embedded which could be used as program or data.
Also the In-System Programming and In-Application Programming mechanisms are
supported. The data endurance of the embedded flash gets over 20,000 times, and 21 years
data retention is guaranteed.
The operation frequency reaches at 25MHz. An user can apply a crystal oscillator for the
oscillating source, or alternatively uses the built in 6MHz RC oscillator to save system cost.
The built in 10Bits Analog-To-Digital Converter make it easy to sensing the environment or
implement a set of scan keys in low cost.
The UART interfaces make the device convenient to communicate with the peripheral
component, say talking to a personal computer via RS-232 port, or communicating with a
serial memory.
The Pulse-Width-Modulator (PWM) and Programmable Counter Array (PCA) make the device
to drive the peripheral step motor or LED in least cost.
The STC12xx is really the most efficient MCU adapted for simple control, say electronic
scales, remote controller, security encoder/decoder, and user interface controller.
Order Information:
Part Number Temperature
Range
Package Packing Operation
Voltage
12x5Aaa-bbb-cc-d-eee-ff -40℃~+85℃PDIP-40 Tray LE3.3V/ C:5V
12x5Aaa-bbb-cc-d-eee-ff -40℃~+85℃PLCC-44 Tray LE3.3V/ C:5V
12x5Aaa-bbb-cc-d-eee-ff -40℃~+85℃LQFP-48 Tray LE3.3V/ C:5V
12x5Aaa-bbb-cc-d-eee-ff -40℃~+85℃LQFP-44 Tray LE3.3V/ C:5V
.x: voltage aa: rom size bbb:ADC,PWM .or. none cc:active frequency
.d: temperature “I” for industrial eeee: package type ff: pin count
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STC12C5Axx Technical Summary 5
Pin Description
Pin Definition
MNEMONIC Package Type DESCRIPTION
PDIP40 PLCC44 PQFP44 LQFP48
P0.0 ~ P0.7 32-39 43-34 37-30 40-33 Port0: Port0 is an open-drain,
bi-directional IO port. When 1s are
written to Port0, they become
high-impedance inputs. Port0 is also
the multiplexed low-order address
and data bus during accesses to
external program and data memory.
P1.0 /ADC0/
CLKOUT2
P1.1/ADC1
P1.2/ADC2/ECI/
RXD2
P1.3/ADC3/CCPO/
TXD2
P1.4/ADC4/CCP1/SS
P1.5/ADC5/MOSI
P1.6/ADC6/MISO
P1.7/ADC7/SCLK
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
40
41
42
43
44
1
2
3
43
44
45
46
47
2
3
4
Port1: General-purposed I/O with
weak pull-up resistance inside. When
1s are written into Port1, the strong
output driving PMOS only turn-on two
period and then the weak pull-up
resistance keep the port high.
ADCn: Analog to Digital Converter
Input.
P2.0 ~ P2.7 21-28 24-31 18-25 19-23
26-28
Port2: Port2 is an 8-bit bi-directional
I/O port with pull-up resistance.
Except being as GPIO, Port2 emits
the high-order address byte during
accessing to external program and
data memory.
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0/CLKOUT0
P3.5/T1/CLKOUT1
P3.6/WR
P3.7/RD
10-17 11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
6
8
9
10
11
12
13
14
Port3: General-purposed I/O with
weak pull-up resistance inside. When
1s are written into Port1, the strong
output driving PMOS only turn-on two
period and then the weak pull-up
resistance keep the port high. Port3
also serves the special function of
STC12C5Axx.
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6 STC12C5Axx Technical Summary
P4.0/SS
P4.1/ECI/MOSI
P4.2/CCP0/MISO
P4.3/CCP1/SCLK
P4.4/NA
P4.5/ALE
P4.6/EX_LVD/RST2
P4.7/RST
29
30
31
9
23
34
1
12
32
33
35
10
17
28
39
6
26
27
29
4
18
31
42
7
29
30
32
5
Port4: Port4 are extended I/O ports
such like Port1. It can be available
only on 44L-PLCC, 44L-PQFP and
48L-LQFP.
ALE: Address Latch
EX_LVD: External Low Voltage Reset
Detector.
RESET 9 10 4 5
RESET: A high on this pin for at least
two machine cycles will reset the
device.
P5.0
P5.1
P5.2
P5.3
24
25
48
1
Port5: Port4 are extended I/O ports
such like Port1. It can be available
only on 48L-LQFP.
XTAL1 19 21 15 16
Crystal1: Input to the inverting
oscillator amplifier.
XTAL2 18 20 14 15
Crystal2: Output from the inverting
amplifier.
VDD 40 44 38 41
Power
VSS 20 22 16 17
Ground
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STC12C5Axx Technical Summary 7
Pin Configuration
CLKOUT2/P1.0
ECI/P1.2
CCP0/P1.3
SS/CCP1/P1.4
MOSI/P1.5
MISO/P1.6
SCLK/P1.7
RST/P4.7
RXD/P3.0
TXD/P3.1
INT0/P3.2
INT1/P3.3
CLKOUT0/T0/P3.4
CLKOUT1/T1/P3.5
WR/P3.6
RD/P3.7
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EX_LVD/P4.6/RST2
ALE/P4.5
NA/P4.4
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
XTAL2
XTAL1
GND
P0.1/AD1
P0.0/AD0
VDD
1
20 21
40
PDIP-40
P1.1
STC12C5Axx
MOSI/P1.5
MISO/P1.6
SCLK/P1.7
RXD/P3.0
RST/P4.7
TXD/P3.1
INT0/P3.2
INT1/P3.3
CLKOUT0/T0/P3.4
CLKOUT1/T1/P3.5
P3.6/WR P3.7/RD XTAL2 XTAL1 GND P4.0/SS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12
P0.4/AD4
P2.5/A13
SS/CCP1/P1.4
CCP0/P1.3
ECI/P1.2
CLKOUT2/P1.0
MISO/CCP0/P4.2
VDD
AD0/P0.0 AD1/P0.1 AD2/P0.2 AD3/P0.3
1
SCLK/CCP1/P4.3 STC12C5Axx
LQFP-48
P0.5/AD5
P0.6/AD6
P4.6/E_LVD/RST2
P0.7/AD7
P4.5/ALE
NA/P4.4
P2.7/A15
P2.6/A14
P4.1/ECI/MOSI
P5.0
P5.1
P5.3
P1.1 P5.2
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STC TECHNOLOGY Co.,Ltd.
STC12C5A08/16/32/60
8-bit micro-controller
This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this
product without notice. 2007/12 version A1
MOSI.P1.5
MISO/P1.6
SCLK/P1.7
RXD/P3.0
RST/P4.7
TXD/P3.1
INT0/P3.2
INT1/P3.3
CLKOUT0/T0/P3.4
CLKOUT1/T1/P3.5
P3.6/WR P3.7/RD XTAL2 XTAL1 GND P4.0/SS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12
P0.4/AD4
P0.5/AD5
P0.6/AD6
EX_LVD/P4.6/RST2
P0.7/AD7
P4.5/ALE
NA/P4.4
P2.7/A15
P2.6/A14
P2.5/A13
SS/CCP1/P1.4
CCP0/P1.3
ECI/P1.2
P1.1
CLKOUT2/P1.0
MISO/CCP0/P4.2
VDD
AD0/P0.0 AD1/P0.1 AD2/P0.2 AD3/P0.3
1
7
40
SCLK/CCP1/P4.3 P4.1/ECI/MOSI
18 29
STC12C5Axx
PLCC-44
MOSI/P1.5
MISO/P1.6
SCLK/P1.7
RXD/P3.0
RST/P4.7
TXD/P3.1
INT0/P3.2
INT1/P3.3
CLKOUT0/T0/P3.4
CLKOUT1/T1/P3.5
P3.6/WR P3.7/RD XTAL2 XTAL1 GND P4.0/SS P.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12
P0.4/AD4
P2.5/A13
SS/CCP1/P1.4
CCP0/P1.3
ECI/P1.2
CLKOUT2/P1.0
MISO/CCP0/P4.2
VDD
AD0/P0.0 AD1/P0.1 AD2/P0.2 AD3/P0.3
1
SCLK/CCP1/P4.3 STC12C5Axx
PQFP/LQFP-44
P0.5/AD5
P0.6/AD6
P4.6/EX_LVD/RST2
P0.7/AD7
P4.5/ALE
P4.4/NA
P2.7/A15
P2.6/A14
P4.1/ECI/MOSI
P1.1
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STC12C5Axx Technical Summary 9
Block Diagram
ALU
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10 STC12C5Axx Technical Summary
Special Function Register
Address Map
9 A B C D E F
F8 CH CCAP0H CCAP1H
F0 B PCAPWM0*PCAPWM1*
E8 CL CCAP0L CCAP1L
E0 ACC
D8 CCON CMOD CCAPM0 CCAPM1
D0 PSW
C8 P5 P5M1 P5M0 SPSTAT SPCTL SPDAT
C0 P4 WDT_CONTR IAP_DATA IAP_ADDRH IAP_ADDRL IAP_CMD IAP_TRIG IAP_CONTR
B8 IP SADEN P4SW ADC_CONTR ADC_RES ADC_RESL
B0 P3 P3M1 P3M0 P4M1 P4M0 IP2 IP2H IPHIPH
A8 IE SADDR
A0 P2 BUS_SPEED AUXR1 TEST_WDT
98 SCON SBUF S2CON S2SBUF BRT P1ASF
90 P1 P1M1 P1M0 P0M1 P0M0 P2M1 P2M0 CLK_DIV
88 TCON TMOD TL0 TL1 TH0 TH1 AUXR WAKE_CLK0
80 P0 SP DPL DPH PCON
* Write Only
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STC12C5Axx Technical Summary 11
Bits Description
SYMBOL ADDRESS
MAP
BIT ADDRESS AND SYMBOL
MSB LSB
INITIAL
VALUE
P0 80H xxxx1111B
SP 81H 00000111B
DPL 82H 00000000B
DPH 83H 00000000B
PCON 87H -- -- -- -- -- -- PD IDL xxxxxx00B
TCON 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000B
TMOD 89H GATE C/T M1 M0 GATE C/T M1 M0 00000000B
TL0 8AH 00000000B
TL1 8BH 00000000B
TH0 8CH 00000000B
TH1 8DH 00000000B
AUXR 8EH T0X12 T1X12 UART_ BRTR S2SMOD BRTX12 EXTRAM S1BRS 00xxxxxxB
WAKE_CLKO 8FH PCA RXD_PIN_ T1_PIN_ T0_PIN_ LVD_WA BRTCLK T1CLKO T0CLKO 00000x00B
P1 90H P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 11111111B
P1M1 91H P1.7M1 P1.6M1 P1.5M1 P1.4M1 P1.3M1 P1.2M1 P1.1M1 P1.0M1 00000000B
P1M0 92H P1.7M0 P1.6M0 P1.5M0 P1.4M0 P1.3M0 P1.2M0 P1.1M0 P1.0M0 00000000B
P0M1 93H P0.7M1 P0.6M1 P0.5M1 P0.4M1 P0.3M1 P0.2M1 P0.1M1 P0.0M1 00000000B
P0M0 94H P0.7M0 P0.6M0 P0.5M0 P0.4M0 P0.3M0 P0.2M0 P0.1M0 P0.0M0 00000000B
P2M1 95H P2.7M1 P2.6M1 P2.5M1 P2.4M1 P2.3M1 P2.2M1 P2.1M1 P2.0M1 00000000B
P2M0 96H P2.7M0 P2.6M0 P2.5M0 P2.4M0 P2.3M0 P2.2M0 P2.1M0 P2.0M0 00000000B
CLK_DIV 97H CLKS2 CLKS1 CLKS0 xxxxx000B
SCON 98H SM0 SM1 SM2 REN TXSTS TISEL TI RI 00000000B
SBUF 99H SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 xxxxxxxxB
S2CON 9AH S2SM0 S2SM1 S2SM2 S2REN S2TB8 S2RB8 S2TI S2RI 00000000B
S2SBUF 9BH S2D7 S2D6 S2D5 S2D4 S2D3 S2D2 S2D1 S2D0 xxxxxxxxB
BRT 9CH 00000000B
P1SF 9DH P1.7ASF P1.6ASF P1.5ASF P1.4ASF P1.3ASF P1.2ASF P1.1ASF P1.0ASF 00000000B
P2 A0H P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 11111111B
BUS_SPEED A1H ALES1 ALES0 RWS2 RWS1 RWS0 xx100x11B
AUXR1 A2H PCA_P4 SPI_P4 S2_P4 GF2 ADRJ DPS 00000000B
TEST_WDT A7H 0xx00000B
IE A8H EA -- ESPI ES ET1 EX1 ET0 EX0 0x000000B
SADDR A9H -- -- -- -- -- 00000000B
IE2 AFH ESPI ES2 xxxxxx00B
P3 B0H P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 11111111B
P3M1 B1H P3.7M1 P3.6M1 P3.5M1 P3.4M1 P3.3M1 P3.2M1 P3.1M1 P3.0M1 00000000B
P3M0 B2H P3.7M0 P3.6M0 P3.5M0 P3.4M0 P3.3M0 P3.2M0 P3.1M0 P3.0M0 00000000B
P4M1 B3H P4.7M1 P4.6M1 P4.5M1 P4.4M1 P4.3M1 P4.2M1 P4.1M1 P4.0M1 00000000B
P4M0 B4H P4.7M0 P4.6M0 P4.5M0 P4.4M0 P4.3M0 P4.2M0 P4.1M0 P4.0M0 00000000B
IP2 B5H PSP1 PS2 xxxxxx00B
IP2H B6H PSP1H PS2H xxxxxx00B
IPH B7H PPCAH PLVDH PADCH PSH PT1H PX1H PT0H PX0H 00000000B
IP B8H PPCA PLVD PADC PS PT1 PX1 PT0 PX0 00000000B
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12 STC12C5Axx Technical Summary
SADEN B9H 00000000B
P4SW BBH LVD_P4.6 ALE_P4.5 NA/P4.4 x000xxxxB
ADC_CONTR BCH ADC SPEED1 SPEED0 ADC_ ADC_ CHS2 CHS1 CHS0 00000000B
ADC_RES BDH 00000000B
ADC_RESL BEH 00000000B
P4 C0H 11111111B
WDT_CONTR C1H WDT_ -- EN_WDT CLR_ IDL_ PS2 PS1 PS0 xx000000B
IAP_DATA C2H 11111111B
IAP_ADDRESS C3H 00000000B
IAP ADDRESS C4H 00000000B
IAP CMD C5H MS1 MS0 xxxxxx00B
IAP_TRIG C6H xxxxxxxxB
IAP_CONTR C7H IAPEN SWBS SWRST CMD_Fail WT2 WT1 WT0 00001000B
P5 C8H
P5M1 C9H P5.7M1 P5.6M1 P5.5M1 P5.4M1 P5.3M1 P5.2M1 P5.1M1 P5.0M1 xxxx0000B
P5M0 CAH P5.7M0 P5.6M0 P5.5M0 P5.4M0 P5.3M0 P5.2M0 P5.1M0 P5.0M0 xxxx0000B
SPSTAT CDH SPIF WCOL 00xxxxxxB
SPCTL CEH SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 00000100B
SPDAT CFH 0000000B
PSW D0H CY AC F0 RS1 RS0 OV -- P 00000000B
CCON D8H CF CR CCF1 CCF0 00xxxx00B
CMOD D9H CIDL CPS2 CPS1 CPS0 ECF 0xxx0000B
CCAPM0 DAH ECOMO CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x0000000B
CCAPM1 DBH ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x0000000B
ACC E0H 00000000B
CL E9H WRF -- ENW CLW WIDL PS2 PS1 PS0 0x000000B
CCAP0L EAH 11111111B
CCAP1L EBH 00000000B
B F0H 00000000B
PCA_PWM0 F2H -- -- -- -- -- -- EPC0H EPC0L xxxxxx00B
PCA_PWM1 F3H EPC1H EPC1L xxxxxx00B
CH F9H 00000000B
CCAP0H FAH 00000000B
CCAP1H FBH 00000000B
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STC TECHNOLOGY Co.,Ltd.
STC12C5A08/16/32/60
8-bit micro-controller
This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this
product without notice. 2007/12 version A1
Memory
Organization
RAM
There are 1280 bytes RAM built in STC12C5Axx.
The user can visit the leading 128-byte RAM via direct addressing instructions, we name those RAM as
direct RAM that occupies address space 00h to 7Fh.
Followed 128-byte RAM can be visited via indirect addressing instructions, we name those RAM as
indirect RAM that occupied address space 80h to FFh.
There are extra 1024 bytes RAM can be visited via MOVX @Ri or @DPTR instructions which are
named external or auxiliary RAM. None of P0 status and P2 status will be affected during MOVX
instruction.
A control bit EXTRAM located in SFR AUXR.1register is to control access of auxiliary RAM. When set,
disable the access of auxiliary RAM. When clear (EXTRAM=0), this auxiliary RAM is the default target
for the address range from 0x0000 to 0x03FF. If EXTRAM=0 and the target address is over 0x03FF,
STC12C5Axx switches to access external RAM automatically. When EXTRAM=0, the content in DPH is
ignored when the instruction MOVX @Ri is executed.
00-7F RAM, Access it via direct addressing
80-FF SFR, Access it via direct addressing
80-FF indirect on-chip RAM,
Access it via indirect addressing
00
80
FF
Address Space for STC12C5Axx RAM
7F
0000-03FF On-Chip External auxiliary RAM.
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14 STC12C5Axx Technical Summary
Embedded Flash
There is totally 64K byte flash embedded in the STC12C5Axx.
The user can configure the whole flash to store his application program, or he can configure
the flash for both storage of application (AP) program and In-System-Program (ISP) code,
even he can configure the flash for storage of AP, ISP, and In-Application-Program (IAP)
memory.
If there is requirement from the user’s application program to store nonvolatile parameters,
the user can allocate part of the embedded flash as IAP memory by Part No..
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STC TECHNOLOGY Co.,Ltd.
STC12C5A08/16/32/60
8-bit micro-controller
This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this
product without notice. 2007/12 version A1
ALE OUTPUT
As we have known, an 8051 MCU always outputs ALE the signal. However, the device doesn’t
output the ALE signal except when accessing the external data memory.
Access Timing Stretching for Low-speed Memory
To access the low-speed external data memory, the timing-stretch mechanism is designed to
control the access timing of the “MOVX” instructions. The bits ALES1 and ALES0, in
BUS_SPEED register, control the stretching of the setup time and hold time with respect to ALE
negative edge. And, the bits RWS2, RWS1 and RWS0 control the stretching of the read/write
pulse width. Users should configure STRETCH register properly to conform to the read/write
requirements of the external data memory being used.
BUS_SPEED (Address=A1H, External Access Stretch Register)
BUS_SPEED register
Read/Write Address:0XA1H
Default:XX10-X011
Bit 7 6 5 4 3 2 1 0
Name ALES1 ALES0 RWS2 RWS1 RWS0
Note:The reset value for BUS_SPEED is 00100011b (0x23). That is, {ALES1,ALES0}={1,0} and
{RWS2,RWS1,RWS0}={0,1,1}.
{ALES1, ALES0}:
00: No stretch, the P0’s address setup/hold time to the following ALE falling edge is 1 clock cycle.
01: 1 clock stretched, the P0’s address setup/hold time to the following ALE falling edge is 2 clock cycles.
10: 2 clocks stretched, the P0’s address setup/hold time to the following ALE falling edge is 3 clock
cycles.
11: 3 clocks stretched, the P0’s address setup/hold time to the following ALE falling edge is 4 clock
cycles.
{RWS2, RWS1, RWS0}:
000: No stretch, the MOVX read/write pulse is 1 clock cycle.
001: 1 clock stretched, the MOVX read/write pulse is 2 clock cycles.
010: 2 clocks stretched, the MOVX read/write pulse is 3 clock cycles.
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16 STC12C5Axx Technical Summary
011: 3 clocks stretched, the MOVX read/write pulse is 4 clock cycles.
100: 4 clocks stretched, the MOVX read/write pulse is 5 clock cycles.
101: 5 clocks stretched, the MOVX read/write pulse is 6 clock cycles.
110: 6 clocks stretched, the MOVX read/write pulse is 7 clock cycles.
111: 7 clocks stretched, the MOVX read/write pulse is 8 clock cycles.
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STC12C5Axx Technical Summary 17
Functional Description
I/O Port Configuration
There are 44(max) port pins on STC12C5Axx may be independently configured to one of four
modes: quasi-bidirectional(standard 8051 port output), push-pull output, open-drain output or
input-only. All port pins default to quasi-bidirectional after reset. Each port pin has a
Schmitt-triggered input for improved input noise rejection. During power-down, all the
schmitt-triggered inputs are disabled with the exception of P3.2 (INT0) and P3.3 (INT1) or
RXD_PIN to drive this device escape power-down mode. Therefore such kind of pins should not be left
floating during power-down.
There are several special function registers designed to configure those I/O ports.
SFR: P0M0(P0 Configuration 0)
Read/Write Address:0X94H
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P0M0.7 P0M0,6 P0M0.5 P0M0.4 P0M0.3 P0M0.2 P0M0.1 P0M0.0
SFR: P0M1(P0 Configuration 1)
Read/Write Address:0X93H
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P0M1.7 P0M1,6 P0M1.5 P0M1.4 P0M1.3 P0M1.2 P0M1.1 P0M1.0
SFR: P1M0(P1 Configuration 0)
Read/Write Address:0X92H
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P1M0.7 P1M0,6 P1M0.5 P1M0.4 P1M0.3 P1M0.2 P1M0.1 P1M0.0
SFR: P1M1(P1 Configuration 1)
Read/Write Address:0X91H
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P1M1.7 P1M1,6 P1M1.5 P1M1.4 P1M1.3 P1M1.2 P1M1.1 P1M1.0
SFR: P3M0(P3 Configuration 0)
Read/Write Address:0XB2H
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P3M0.7 P3M0,6 P3M0.5 P3M0.4 P3M0.3 P3M0.2 P3M0.1 P3M0.0
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18 STC12C5Axx Technical Summary
SFR: P3M1(P3 Configuration 1)
Read/Write Address:0XB1H
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P3M1.7 P3M1,6 P3M1.5 P3M1.4 P3M1.3 P3M1.2 P3M1.1 P3M1.0
SFR: P4M0(P4 Configuration 0)
Read/Write Address:0XB4H
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P4M0.7 P4M0,6 P4M0.5 P4M0.4 P4M0.3 P4M0.2 P4M0.1 P4M0.0
SFR: P4M1(P4 Configuration 1)
Read/Write Address:0XB3H
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P4M1.7 P4M1,6 P4M1.5 P4M1.4 P4M1.3 P4M1.2 P4M1.1 P4M1.0
SFR: P5M0(P5 Configuration 0)
Read/Write Address:0XCAH
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P5M0.7 P5M0,6 P5M0.5 P5M0.4 P5M0.3 P5M0.2 P5M0.1 P5M0.0
SFR: P5M1(P5 Configuration 1)
Read/Write Address:0XC9H
Default: 0000-0000
Bit 7 6 5 4 3 2 1 0
Name P5M1.7 P5M1,6 P5M1.5 P5M1.4 P5M1.3 P5M1.2 P5M1.1 P5M1.0
Configuration of I/O port
PxM0nPxM1nPort Mode
0 0
Quasi-bidirectional(default)
0 1
Push-Pull output
1 0
Input Only (High-impedance)
1 1
Open-Drain Output
( x= 1or 3n= 7, 6, 5, 4, 3, 2, 1 or 0)
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STC12C5Axx Technical Summary 19
Quasi-bidirectional Mode
Port pins in quasi-bidirectional output mode function similar to the standard 8051 port pins. A
quasi-bidirectional port can be used as an input and output without the need to reconfigure the
port. This is possible because when the port outputs logic high, it is weakly driven, allowing an
external device to pull the pin low. When the pin outputs low, it is driven strongly and able to
sink a large current. There are three pull-up transistors in the quasi-bidirectional output that
serve different purposes.
One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port register
for the pin contains a logic “1”. This very weak pull-up sources a very small current that will
pull the pin high if it is left floating.
A second pull-up, called the “weak” pull-up, is turned on when the port register for the pin
contains a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the
primary source current for a quasi-bidirectional pin that is outputting a ‘1’. If this pin is pulled
low by the external device, this weak pull-up turns off, and only the very weak pull-up remains
on. In order to pull the pin low under these conditions, the external device has to sink enough
current to over-power the weak pull-up and pull the port pin below its input threshold voltage.
The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up
low-to-high transitions on a quasi-bidirectional port pin when the port register changes from a
logic “0” to a logic “1”. When this occurs, the strong pull-up turns on for two CPU clocks,
quickly pulling the port pin high.
VDDVDD VDD
Port pin
2 clocks
delay
Strong Very weak
Weak
Input data
Port latch data
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20 STC12C5Axx Technical Summary
Open-drain Output
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port pin when the port register contains logic “0”. To use this configuration in
application, a port pin must have an external pull-up, typically tied to VDD. The input path of
the port pin in this configuration is the same as quasi-bidirection mode.
Port pin
Input data
Port latch data
Input-only Mode
The input-only configuration is a Schmitt-triggered input without any pull-up resistors on the
pin.
Port pin
Input data
Push-pull Output
The push-pull output configuration has the same pull-down structure as both the open-drain
and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the
port register contains a logic “1”. The push-pull mode may be used when more source current
is needed from a port output.
VDD
Port pin
Input data
Port latch data
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