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SUPER P6DNH/P6DNH2 User’s Manual
of wider datapaths both inside and outside the chip. It has an
external 64-bit bus in order to communicate more efficiently with the
system memory. The package have two cavities with about 21 mil-
lion transistors. The larger one is the CPU core with 5.5 million
transistors. The smaller one is the non-blocking cache which con-
tains 15.5 million transistors.
The i960 RP/RD I/O processor is a highly integrated intelligent I/O
subsystem on a chip. Mode 3 is the default setting for its normal
operation. The i960 RP/RD has two main functions. As a local
processor, it offloads interrupt-intensive I/O tasks from the host
CPU. Its architecture is composed of a RISC core surrounded by
peripherals essential to the I/O function. The on-board PCI-to-PCI
bridge enables designers to connect I/O components directly to the
PCI bus and also add additional PCI slots. The bridge improves
overall system performance by reducing bus traffic. SUPER
P6DNH/P6DNH2 supports four primary and four secondary PCI
buses.
I2O is an open software-interface standard for I/O devices, indepen-
dent of the specific device and operating system. It is implemented
on the i960 RP/RD I/O processor. With I2O, I/O hardware vendors
do not have to write drivers in countless variation, one for each
operating system version.
To attain portability across multiple operating systems and host
platforms, I2O drivers are divided into the OS Services Module
(OSM), and Hardware Device Module (HDM). The first module inter-
faces with the host operating system. The second interfaces with
the particular device, media or server managed by the driver. The
two modules interface with each other through a two-layered com-
munications system. A Message Layer sets up a communications
session. A Transport Layer defines how information will be shared.
The Message Layer resides on the Transport Layer.
Peripheral Component Interconnect (PCI) provides industry-leading
performance and compatibility. The 32-bit, 33 MHz pathway to the
CPU offers performance unmatched by other bus architectures. The