GOWIN DK-START-GW1NR9 User manual

DK-START-GW1NR9 V1.1
User Guide
DBUG361-1.2E, 2019/12/19

Copyright©2019 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
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consent of GOWINSEMI.
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responsible for any damage incurred to your hardware, software, data, or property resulting
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Terms and Conditions of Sale. All information in this document should be treated as
preliminary. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the current
documentation and errata.

Revision History
Date
Version
Description
03/19/2019
1.0E
Initial version published.
11/29/2019
1.1E
MIPI input function removed.
12/19/2019
1.2E
The version of DK-START-GW1NR9 added.

Contents
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Contents
Contents...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Supported Products............................................................................................................1
1.3 Related Documents............................................................................................................1
1.4 Terminology and Abbreviation ............................................................................................ 2
1.5 Support and Feedback .......................................................................................................3
2Development Board Introduction.................................................................4
2.1 Overview.............................................................................................................................4
2.2 A Development Board Suite................................................................................................ 5
2.3 PCB Components............................................................................................................... 6
2.4 System Diagram................................................................................................................. 7
2.5 Feature ............................................................................................................................... 8
2.6 Development Board Specification ......................................................................................9
3Development Board Circuit........................................................................ 11
3.1 FPGA Module ................................................................................................................... 11
3.1.1 Overview........................................................................................................................ 11
3.1.2 I/O BANK Introduction ...................................................................................................12
3.2 Download.......................................................................................................................... 14
3.2.1 Overview........................................................................................................................14
3.2.2 USB Download Circuit...................................................................................................14
3.2.3 Download Flow..............................................................................................................14
3.2.4 Pins Distribution.............................................................................................................14
3.3 Power Supply....................................................................................................................15
3.3.1 Overview........................................................................................................................15

Contents
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3.3.2 Power System Distribution ............................................................................................16
3.3.3 Pins Distribution.............................................................................................................16
3.4 Clock, Reset ..................................................................................................................... 17
3.4.1 Overview........................................................................................................................17
3.4.2 Clock, Reset ..................................................................................................................17
3.4.3 Pins Distribution.............................................................................................................17
3.5 LED...................................................................................................................................18
3.5.1 Overview........................................................................................................................18
3.5.2 LED Circuit.....................................................................................................................18
3.5.3 Pins Distribution.............................................................................................................18
3.6 Switches ........................................................................................................................... 19
3.6.1 Overview........................................................................................................................19
3.6.2 Switch Circuit.................................................................................................................19
3.6.3 Pins Distribution.............................................................................................................19
3.7 Key....................................................................................................................................20
3.7.1 Overview........................................................................................................................20
3.7.2 Key Circuit ..................................................................................................................... 20
3.7.3 Pins Distribution.............................................................................................................20
3.8 GPIO.................................................................................................................................21
3.8.1 Overview........................................................................................................................21
3.8.2 GPIO Circuit................................................................................................................... 21
3.8.3 Pins Distribution.............................................................................................................22
3.9 MIPI/LVDS ........................................................................................................................24
3.9.1 Overview........................................................................................................................24
3.9.2 MIPI/LVDS Circuit..........................................................................................................24
3.9.3 Pins Distribution.............................................................................................................25
4Precautions..................................................................................................29
5Gowin YunYuan Software...........................................................................30

List of Figures
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List of Figures
Figure 2-1 DK-START-GW1NR9 V1.1 Development Board.............................................................. 4
Figure 2-2 ADevelopment Board Suite .............................................................................................5
Figure 2-3 PCB Components.............................................................................................................6
Figure 2-4 System Diagram...............................................................................................................7
Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution ..................................................... 12
Figure 3-2 GW1N-9 LQ144 Package Pins Distribution (Top View) ...................................................13
Figure 3-3 Connection Diagram for FPGAUSB Download ...............................................................14
Figure 3-4 Power System Distribution ............................................................................................... 16
Figure 3-5 Clock, Reset..................................................................................................................... 17
Figure 3-6 LED Circuit .......................................................................................................................18
Figure 3-7 Switch Circuit.................................................................................................................... 19
Figure 3-8 Key Circuit Diagram.......................................................................................................... 20
Figure 3-9 GPIO Circuit .....................................................................................................................21
Figure 3-10 LVDS Circuit ...................................................................................................................24

List of Tables
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List of Tables
Table 1-1 Abbreviation and Terminology............................................................................................ 2
Table 2-1 Development Board Specification...................................................................................... 9
Table 3-1 GW1NR-9 FPGA Resources List....................................................................................... 11
Table 3-2 FPGA I/O Pins Distribution................................................................................................. 13
Table 3-3 FPGA Download Pins Distribution ..................................................................................... 14
Table 3-4 FPGA Power Pins Distribution ...........................................................................................16
Table 3-5 FPGA Clock and Reset Pins Distribution........................................................................... 17
Table 3-6 LED Pins Distribution.........................................................................................................18
Table 3-7 Switch Circuit Pins Distribution ..........................................................................................19
Table 3-8 Key Circut Pins Distribution ...............................................................................................20
Table 3-9 J14 GPIO Pins Distribution ................................................................................................22
Table3-10 J13 GPIO Pins Distribution ...............................................................................................22
Table 3-11 J15 FPGA Pin Distribution (IDES16:1 Supported)........................................................... 25
Table 3-12 J17 FPGA Pin Distribution ............................................................................................... 25
Table 3-13 J16 FPGA Pin Distribution (IDES16:1 Supported)........................................................... 27
Table 3-14 J18 FPGA Pin Distribution (IDES16:1 Supported)........................................................... 28

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK-START-GW1NR9 V1.1 user manual consists of the following
four parts:
1. A brief introduction to the features and hardware resources of the
development board;
2. An introduction to the function, circuit, and pin distribution of each
module;
3. Attentions in use of the development board;
4. An introduction to the usage of the FPGA development software.
1.2 Supported Products
The information in the guide applies to GW1NR series of FPGA
products: GW1NR-9.
1.3 Related Documents
The user manuals are available on the GOWINSEMI Website. You can
find the related documents at www.gowinsemi.com
1. DS117, GW1NR Series FPGA Products Data Sheet
2. UG119, GW1NR Series of FPGAProducts Package and Pinout Manual
3. UG801, GW1NR-9 Devices Pinout Manual
4. UG290, Gowin FPGA Products Programming and Configuration
Manual
5. SUG100, Gowin YunYuan Software User Guide

1 About This Guide
1.4 Terminology and Abbreviation
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1.4 Terminology and Abbreviation
The terminology and abbreviation used in this manual are as shown in
Table 1-1 below.
Table 1-1 Abbreviation and Terminology
Terminology and Abbreviation
Meaning
FPGA
Field Programmable GateArray
SIP
System in Package
SDRAM
Synchronous Dynamic RAM
PSRAM
Pseudo static random access memory
CFU
Configurable Function Unit
CLS
Configurable Logic Slice
CRU
Configurable Routing Unit
LUT4
Four-input Look-up Tables
LUT5
Five-input Look-up Tables
LUT6
Six-input Look-up Tables
LUT7
Seven-input Look-up Tables
LUT8
Eight-input Look-up Tables
REG
Register
ALU
Arithmetic Logic Unit
IOB
Input / Output Block
S-SRAM
Shadow SRAM
B-SRAM
Block Static Random Access Memory
SP
Single Port
SDP
Semi Dual Port
DP
Dual Port
DSP
Digital Signal Processing
DQCE
Dynamic Quadrant Clock Enable
DCS
Dynamic Clock Selector
PLL
Phase-locked Loop
DLL
Delay-locked Loop
LQ144
LQFP144 package

1 About This Guide
1.5 Support and Feedback
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1.5 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]
+Tel: [phone]

2 Development Board Introduction
2.1 Overview
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2Development Board Introduction
2.1 Overview
Figure2-1 DK-START-GW1NR9 V1.1 Development Board
The development board adopts the GW1NR-9 device, which is
embedded with PSRAM of 64Mbit, user flash memory and other resources.
The GW1NR series of FPGA products are the first generation of the Gowin
LittleBee®family and it is a SIP chip. Based on GW1N, GW1NR series
integrates abundant PSRAM. At the same time, it has the characteristics of
low power consumption, instant-start, low cost, non-volatility, high security,
rich packages, convenient and flexible usage, etc., which can effectively
reduce the learning cost and help users quickly enter the design and
development field of programmable logic devices.
The development board offers abundant external interfaces, including
MIPI/LVDS interfaces, GPIO interfaces, etc. There are also sliding switch,

2 Development Board Introduction
2.2 A Development Board Suite
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button switch, LED, clock, reset and other resources for developers or fans
to learn to use.
2.2 A Development Board Suite
A development board suite includes the following items:
DK-START-GW1NR9 V1.1 Development Board
USB Cable
Quick Start Guide
Figure2-2A Development Board Suite11
1
2
3
3
Gowin DK-START-GW1NR9
Development Board
USB Cable
1
2
3
3
Quick Start Guide
①DK-START-GW1NR9 V1.1 Development Board
②USB Cable
③Quick Start Guide

2 Development Board Introduction
2.3 PCB Components
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2.3 PCB Components
Figure2-3 PCB Components
GPIO
1.2V 3.3V
OSC
LED
RESET
FPGA
Download
5V IN
FPGA
1.8V
LVDS
LVDS
2.5V
LVDS
LVDS
GPIO
SWITCH
KEY

2 Development Board Introduction
2.4 System Diagram
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2.4 System Diagram
Figure2-4 System Diagram
4*LED4*SWITCH
OSC
50MHz
10Pairs
LVDS/MIPI
INPUT
4*BUTTON
10Pairs
LVDS/MIPI
OUTPUT
20PIN
GPIO
FPGA
Mini USB Interface
40PIN
GPIO
GW1NR-
LV9LQ144P
5V LDO
1.2V/1.8V/2.5V/3.3V

2 Development Board Introduction
2.5 Feature
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2.5 Feature
The structure and feature of the development board are as follows:
1. FPGA
LQFP144 package
Up to 120 user I/O
Embedded flash, data not easily lost if power down
Abundant LUT4 resources
Multiple modes and capacities of B-SRAM
2. FPGA Configuration Mode
JTAG
AUTO BOOT
3. Clock resource
50MHz Clock Crystal Oscillator
4. Key switch and slide switch
One reset button
Four key switches
Four Slide switch
5. LED
One power indicator (green)
One DONE indicator (green)
Four LEDs (green)
6. Memory
1Mbit embedded Flash
64Mbit embedded PSRAM
7. MIPI/LVDS
10 pairs of LVDS differential input; 10 pairs of MIPI/LVDS differential output
8. GPIO
55 I/O extended resources
9. LDO Power
3.3 V, 2.5V, 1.8V, and1.2V supported

2 Development Board Introduction
2.6 Development Board Specification
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2.6 Development Board Specification
Table 2-1 Development Board Specification
No.
Item
Functional Description
Technical Condition
Remarks
1
FPGA
Core chip
–
–
2
Download
Support an USB
interface; Support
JTAG, AUTOBOOT
USB to JTAG chip integrated on board
–
3
Power
Supply
3.3 V, 2.5V and 1.2 V
output via LDO circuit
Input power: 5V
Provide power for FPGA, download
circuit and other circuits via 5V–3.3 V
circuit;
Provide power for FPGAvia 5V to 2.5V
circuit;
Provide power for FPGAvia 5 V–1.2 V
circuit.
–
4
Slide
Switches
Available for testing
4
–
5
Key
Switches
Available for testing
4
–
6
Reset button
Reset for FPGA
1
–
7
LED
Test indicator, DONE
indicator, Power
indicator
Four Test indicators, green
One DONE indicator, green
One Power indicator, green
–
8
Crystal
Oscillator
Provide 50MHz clock
for FPGA
Package5032
–
9
Memory
Provides abundant
Flash and PSRAM for
design
1Mbit embedded Flash
64Mbit embedded PSRAM
–
10
GPIO
I/O, convenient for user
extension and test
36
–
11
MIPI/LVDS
MIPI/LVDS, used for
testing
10 pairs of input, 10 pairs of output
–
12
Protection
USB interface: ESD
protection;
Power interface:
Inverse current and
over current protection
USB interface ESD protection: ±15kV
non-contact discharge, ±8kV contact
discharge;
Schottky diode is connected between
positive and negative anodes of power
interface;
2A self-recovery fuses are connected
at power inlet
–
13
Voltage
–
Input Voltage: 5V
–
14
Humidity
–
95%
–

2 Development Board Introduction
2.6 Development Board Specification
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No.
Item
Functional Description
Technical Condition
Remarks
15
Temperatur
e
–
Operating range: –20°~70°
–

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
3.1.1 Overview
The resources of GW1NR series of FPGA products are shown in Table
3-1.
Table 3-1 GW1NR-9 FPGA Resources List
Device
GW1NR-9
LUT4
8,640
Flip-Flop (FF)
6,480
Shadow SRAM
S-SRAM (bits)
17,280
Block Static Random Access Memory
B-SRAM (bits)
468K
B-SRAM quantity
B-SRAM
26
User Flash (bits)
608K
PSRAM(bits)
64M
18 x 18 Multiplier
20
PLLs+DLLs
2+4
Total number of I/O banks
4
Max. user I/O1
120
Core Voltage (LV)
1.2V
Note!
See DS117, GW1NR series of FPGA Products Data Sheet for further details.

3 Development Board Circuit
3.1 FPGA Module
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3.1.2 I/O BANK Introduction
There are four I/O Banks in the GW1NR series of FPGA products, as
shown in Figure 3-1.
Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution
GW1NR
I/O BANK0
I/O BANK2
I/O BANK1 I/O BANK3

3 Development Board Circuit
3.1 FPGA Module
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Figure3-2 GW1N-9 LQ144 Package Pins Distribution (Top View)
Table 3-2 FPGA I/O Pins Distribution
I/O BANK No.
Modules Connected
I/O BANK0
Pins selection for download mode
LVDS differential input
GPIO
I/O BANK1
GPIO
50MHz clock input
LED
Slide Switches
Key Switches
Reset
I/O BANK2
MIPI/LVDS differential output
GPIO
I/O BANK3
GPIO Interface
JTAG download