Syntacore SCR1 SDK. Altera Arria-V Starter Kit Edition User manual

SCR1 SDK. Altera Arria-V Starter Kit
Edition. Quick Start Guide
© Syntacore, [email protected]
Version 1.4, 2019-04-08

Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê2
1. Setup equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê3
1.1. Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê3
2. SDK HW assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê4
2.1. Connecting serial console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê4
2.2. Pins assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê4
3. Arria-V HW image update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê6
4. Booting the new FPGA image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê8
5. Resetting the board: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê9
6. UART connection settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê9
7. Using UART terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê10
7.1. Load binary images to the Memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê10
7.2. Example: Dhrystone run from TCM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê12
7.3. Using OpenOCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê13
7.3.1. Installing OpenOCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê13
7.3.2. Starting the OpenOCD server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê13
7.3.3. Downloading and running an image using OpenOCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê14
8. Building SDK FPGA-project for the Arria V GX SDK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê16
8.1. General structure of the SDK project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê16
8.2. Additional requirements for compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê16
8.3. Building SDK FPGA project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê17
8.3.1. FPGA firmware generation (sof-format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê17
8.3.2. Converting FPGA-image to the board flash memory image (flash-format) . . . . . . . . . . . . . Ê17
8.3.3. SDK-specific pins assignment in FPGA-project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê19
8.4. SCR1 SDK FPGA-project functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê20
8.4.1. Common project structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê20
8.4.2. Qsys SoC module structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê20
8.4.3. Description of the blocks used in the SDK project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.3.1. SCR1-core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.3.2. AXI bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.3.3. Opencores UART 16550 IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.4. Description of the IP-components of the module Qsys SOC . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.4.1. BUILD ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
8.4.4.2. Onchip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
8.4.4.3. DDR3 Сontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
8.4.4.4. UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
8.4.4.5. Qsys Default slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
9. Appendix A. SDK Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê23

10. Appendix B. SDK IRQs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê24
11. Appendix C. Software build instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.1. SCR bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.1.1. Getting the sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.1.2. Building SCR bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.2. Zephyr OS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.2.1. Getting the sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.2.2. Building Zephyr OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3. SCR1 OpenOCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3.1. Getting the latest release. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3.2. Getting the sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3.3. Building and using OpenOCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3.4. Windows - USB JTAG Cable drivers installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê26

Copyright by Syntacore LLC © 2017. ALL RIGHTS RESERVED. STRICTLY
CONFIDENTIAL. Information contained in this material is confidential and
proprietary to Syntacore LLC and its affiliates and may not be modified, copied,
published, disclosed, distributed, displayed or exhibited, in either electronic or
printed formats without written authorization of the Syntacore LLC. Subject to
License Agreement.
1

Revision History
Version Date Description
1.0 2017-08-01 Initial revision
1.1 2019-01-30 Modifications:
•New section: "Windows - USB JTAG Cable drivers installation"
•Sections with memory map and IRQ mapping are moved to
appendix;
•Figure numbering is introduced.
1.2 2019-03-21 OpenOCD section updated for RISC-V debug. JTAG speed
requirement added.
1.3 2019-03-29 Fix figures numbers, fix image borders
1.4 2019-04-08 Upated IMPID, BUILDID
2

This is a user guide for the Arria V GX based SCR1 SDK Arria V GX FPGA Starter Kit from the Altera.
1. Setup equipment
Arria-V based SCR1 SDK HW platform consist of three mandatory components:
1. Arria V GX FPGA Starter Kit
https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-arria-v-starter.html
2. CP2104-MINIEK
http://www.silabs.com/products/development-tools/interface/cp2104-mini-evaluation-kit
3. ARM-USB-OCD-H
https://www.olimex.com/Products/ARM/JTAG/ARM-USB-OCD-H/
Additionally, you may need some wires and cables:
1. Wires: 3 mounting wires
2. Cables:
◦USB A (m) - mini USB B (m)
◦Ethernet cat.5E
1.1. Prerequisites
FPGA board image update is done over the network, so you’ll need access to the local network with
DHCP capability. Besides of the Arria-V board, you’ll need PC, connected to the same network.
IMPORTANT
1. Before the upgrade, please, make sure the board cooling Fan is ON. If not,
turn on Fan before power on.
2. To switch on board cooling Fan, move FAN_FORCE DIP switch to ON
position at SW. Corresponding DIP is marked by cursor in the figure
below
Figure 1. DIP Switch setup
3

2. SDK HW assembly
2.1. Connecting serial console
In order to get access to the board console, it is required to mount HSMC Debug Header Breakout
Board (included in Arria-V Starter Devkit) and connect CP2104-MINIEK USB-to-UART converter to
the breakout board with external wiring, as described in this section.
2.2. Pins assignment
•Connect CP2104 pin GND to the GND pin on the HSMC Debug board
•Connect CP2104 pin TXD to the 3 pin on the HSMC Debug board
•Connect CP2104 pin RXD to the 4 pin on the HSMC Debug board
•Connect JTAG pin GND to the 38 pin on the HSMC Debug board
•Connect JTAG pin GND to the 36 pin on the HSMC Debug board
•Connect JTAG pin GND to the 34 pin on the HSMC Debug board
•Connect JTAG pin GND to the 32 pin on the HSMC Debug board
•Connect JTAG pin GND to the 30 pin on the HSMC Debug board
•Connect JTAG pin GND to the 28 pin on the HSMC Debug board
•Connect JTAG pin GND to the 26 pin on the HSMC Debug board
•Connect JTAG pin GND to the 24 pin on the HSMC Debug board
•Connect JTAG pin VREF to the 22 pin on the HSMC Debug board
•Connect JTAG pin VREF* to the 21 pin on the HSMC Debug board
•Connect JTAG pin SRSTn to the 35 pin on the HSMC Debug board
•Connect JTAG pin TDO to the 33 pin on the HSMC Debug board
•Connect JTAG pin TCK to the 29 pin on the HSMC Debug board
•Connect JTAG pin TMS to the 27 pin on the HSMC Debug board
•Connect JTAG pin TDI to the 25 pin on the HSMC Debug board
•Connect JTAG pin TRSTn to the 23 pin on the HSMC Debug board
4

IMPORTANT
For proper JTAG interface functioning JTAG clock (TckFreq) and system
clock (SysClkFreq) frequencies must satisfy the following relation:
SysClkFreq / TckFreq >= 12.
IMPORTANT
You can either connect JTAG port using mounting wires, or apply the
existing flat cable from the Olimex kit. For the Olimex kit, some rework
will be needed, it also affects couple of unused pins on the header. It is
mandatory to cut two wires (19 and 20) in the Olimex cable, as shown
below.
The following figures assume the re-worked Olimex cable is used:
1. Wires connection to the CP2104
Figure 2. CP2104 serial interface connection
2. HSMC Debug Board mounting to the Arria-V HMSC header
Figure 3. HSMC header connection
3. Resulting setup
5

Figure 4. Arria V SDK setup
3. Arria-V HW image update
1. Connect board by the ethernet-cable to the network with DHCP-server
2. Power on the board and wait for IP-address to appear at the board LCD-display (IP address may
be different):
Figure 5. IP address indication on LCD display
3. Open web browser at PC and open http-connection the IP-address from LCD
4. You will see Board Update Portal page.
5. Press button “Choose File” and set proper file for "Hardware File Name:” (as shown on the
Figure), then press the "Upload" button
Figure 6. Upload parameters definition
6

6. Wait for upload completion:
Figure 7. Upload completion message
7. Power off the board. Flash update is complete.
7

4. Booting the new FPGA image
IMPORTANT
After FGPA image updated successfully, in order to load the new image,
you have to do the following sequence after every power on!
Otherwise (by default), system will boot into standard board update portal
image.
1. Press PGM_SEL (S2) one time so D25 LED is lighted green.
That selects new image to boot into - otherwise you’ll load the default image with Altera board
update portal SW.
Corresponding button is marked by cursor in the figure below:
Figure 8. PGM_SEL (S2) button
2. Press PGM_CONFIG (S1) once to load the selected image and check CONFDN (D12) led is active
Corresponding button is marked by cursor in the figure below:
Figure 9. PGM_CONFIG (S1) button
3. If CONFDN(D12) led is not active green and/or ERR (D10) led is active red after this step, repeat
the flash update sequence, as described in the section “Arria-V HW image update”
8

5. Resetting the board:
NOTE Press PB2 button if you need to reset board to the bootloader.
Corresponding button is in the figure below:
Figure 10. RESET (PB2) button
6. UART connection settings
NOTE
•Bps/Par/Bits - 115200 8N1
•speed - 115200
•bits - 8
•stop bits - 1
•parity - none
•Hardware Flow Control: No
9

7. Using UART terminal
1. Connect PC to the uart port and open any terminal (minicom is used in the example below)
After reset or FPGA firmware update you will see the bootloader prompt:
SCR loader v1.0-scr1_RC
Copyright (C) 2015-2017 Syntacore. All rights reserved.
ISA: RV32IMC [40001104] IMPID: 19040301
BLDID: 19040500
Platform: a5_scr1, cpuclk 30MHz, sysclk 30MHz
Memory map:
00000000-0FFFFFFF 00000000 DDR
F0000000-F001FFFF 00000000 TCM
F0040000-F0040FFF 00000000 MTimer
FF000000-FF0FFFFF 00000000 MMIO
FFFF0000-FFFFFFFF 00000000 On-Chip RAM
1: xmodem load @addr
g: start @addr
d: dump mem
m: modify mem
i: platform info
:
1. If you press "i" button you can see additional info about the platform
ISA: RV32IMC [40001104] IMPID: 19040301
BLDID: 19040500
Platform: a5_scr1, cpuclk 30MHz, sysclk 30MHz
Memory map:
00000000-0FFFFFFF 00000000 DDR
F0000000-F001FFFF 00000000 TCM
F0040000-F0040FFF 00000000 MTimer
FF000000-FF0FFFFF 00000000 MMIO
FFFF0000-FFFFFFFF 00000000 On-Chip RAM
Platform configuration:
FF010000 irq 0 UART16550
:
7.1. Load binary images to the Memory address
TIP SCR bootloader supports only .binary files loading using x-modem
1. Wait for the booloader prompt
10

1: xmodem load @addr
g: start @addr
d: dump mem
m: modify mem
i: platform info
:
2. Press button “1”
3. Print required TCM address (in hex) and press “Enter”. “C” character starts to print
continuously
xload @addr
addr: f0000000
CCCCCCCCCCCCCC
1. Open xmodem upload menu (for minicom terminal you need to press “Ctrl+A” and press “S”).
Then select “xmodem”:
Ê+-[Upload]--+
Ê| zmodem |
Ê| ymodem |
Ê| xmodem |
Ê| kermit |
Ê| ascii |
Ê+-----------+
1. Press “Enter”. Then select required bin-file for the loading (mark it and press “space” button
for minicom).
+------------------------[Select a file for upload]-------------------------+
|Directory: /images/a5/scr1/ |
| [..] |
| dhry21-o3lto.bin |
| |
1. Press “Enter” button. Image transfer will start.
11

+-----------[xmodem upload - Press CTRL-C to quit]------------+
|Sending dhry21-o3lto.bin, 107 blocks: Give your local XMODEM |
|receive command now. |
|Bytes Sent: 13952 BPS:5468 |
| |
|Transfer complete |
| |
| READY: press any key to continue... |
+-------------------------------------------------------------+
1. After loading completes, status information will be shown:
Xmodem successfully received 13952 bytes
7.2. Example: Dhrystone run from TCM memory
1. Load dhry21-o3lto.bin to the TCM base address (0xf0000000)
And run test from 0xf0000200 address:
1: xmodem load @addr
g: start @addr
d: dump mem
m: modify mem
i: platform info
start @addr
addr: f000200
1. After run you will see test results
12

Dhrystone Benchmark, Version 2.1 (Language: C)
Program compiled without 'register' attribute
Compiler flags: -O3 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto
HZ 1000000, CPU MHz 30.000
Execution starts, 500 runs through Dhrystone
...
Time: begin= 48999682, end= 49004684, diff= 5002
Microseconds for one run through Dhrystone: 10.004
Dhrystones per Second: 99960
7.3. Using OpenOCD
The OpenOCD (Open On-Chip Debugger) is open-source software that interfaces with a hardware
debugger’s JTAG port. OpenOCD provides debugging and in-system programming for embedded
target devices.
IMPORTANT When you boot from OpenOCD, you use images in .elf or .bin formats.
7.3.1. Installing OpenOCD
Official OpenOCD documentation is available at http://openocd.org/doc/html/index.html.
7.3.2. Starting the OpenOCD server
1. Setting environment variables:
$ export OOCD_ROOT=<Path to the OpenOCD installation directory>
2. Server start-up is entered in one line (Ubuntu):
13

$ sudo ${OOCD_ROOT}/bin/openocd \
-s ${OOCD_ROOT}/share/openocd/scripts \
-f ${OOCD_ROOT}/share/openocd/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg \
-f ${OOCD_ROOT}/share/openocd/scripts/target/syntacore_riscv.cfg
or if you build it from sources:
$ sudo ${OOCD_ROOT}/src/openocd \
-s ${OOCD_ROOT}/tcl \
-f ${OOCD_ROOT}/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg \
-f ${OOCD_ROOT}/tcl/target/syntacore_riscv.cfg
After execution to the current terminal, you will receive a message about the connection to the
RISCV kernel:
Open On-Chip Debugger 0.10.0+dev-01972-g01f0c8951 (2019-03-20-20:10)
Licensed under GNU GPL v2
For bug reports, read
Ê http://openocd.org/doc/doxygen/bugs.html
sw_reset_halt
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
adapter speed: 2000 kHz
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
connect_deassert_srst
Info : auto-selecting first available session transport "jtag". To override use
'transport select <transport>'.
riscv.cpu
Info : clock speed 2000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0xdeb11001 (mfg: 0x000 (<invalid>), part:
0xeb11, ver: 0xd)
Info : riscv.cpu: datacount=2 progbufsize=6
Info : riscv.cpu: Examined RISC-V core; found 1 harts
Info : riscv.cpu: hart 0: XLEN=32, misa=0x40001104
Info : Listening on port 3333 for gdb connections
3. Open the second terminal (terminal 2) and enter the command:
$ telnet localhost 4444
4. OpenOCD is up and ready to go. This terminal is an interactive console OpenOCD.
The help command lists the available openocd commands
7.3.3. Downloading and running an image using OpenOCD
1. The load command is entered in the OpenOCD console (terminal 2):
14

halt ; load_image dhry21-o3lto.bin 0xf0000000 bin ; resume 0xf0000200
or
halt ; load_image dhry21-o3lto.elf 0x0 elf ; resume 0xf0000200
IMPORTANT
The boot command assumes the location of the file in the current directory.
For a different location, the name of the uploaded file must include a
relative path.
2. After entering the command, the progress of the load is displayed
3. After the download is complete, the image will start with log output to the uart terminal:
Dhrystone Benchmark, Version 2.1 (Language: C)
Program compiled without 'register' attribute
Compiler flags: -O3 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto
HZ 1000000, CPU MHz 30.000
Execution starts, 500 runs through Dhrystone
...
Time: begin= 48999682, end= 49004684, diff= 5002
Microseconds for one run through Dhrystone: 10.004
Dhrystones per Second: 99960
15

8. Building SDK FPGA-project for the Arria V
GX SDK
8.1. General structure of the SDK project
The composition of the SDK folders is:
•doc - SDK and SCR1 user guides
•fpga
◦a5
▪scr1 - DE10-Lite FPGA project
▪ip - additional RTL IPs + bootloader image
▪uart - Opencores UART 16550 IP
◦arty
◦de10lite
•images
◦a5
▪scr1 - pre-built FPGA image
◦arty
◦de10lite
•scr1 - SCR1 repository, included as sub-module
◦src - SCR1 core RTL sources
•sw
◦fsbl - FPGA-bootloader
◦tests - some benchmark tests
Essential files: FPGA project file - a5_sdk.qpf (fpga/a5/scr1/a5_sdk.qpf)
Top module - a5_sdk (fpga/a5/scr1/a5_sdk.sv)
8.2. Additional requirements for compilation
FPGA build requires "Altera Quartus 13.0.1 Build 232" tool or earlier.
NOTE
FPGA-project compilation was verified for "Altera Quartus 13.0.1 Build 232" Full
version on Linux xUbuntu 16.04 with 8 GB of RAM.
Some build steps may be different for other Quartus versions.
Quartus Full version is required for a non time-limited HW firmware generation.
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8.3. Building SDK FPGA project
The step-by-step FPGA project build procedure is described below:
8.3.1. FPGA firmware generation (sof-format)
•Run Quartus 13.0.1 in GUI-mode
•Select and open fpga-project file (a5_sdk.qpf)
•Press "Start Compilation" button or sellect from menu Processing → "Start Compilation"
Figure 11. Selection of the "Start Compilation" option
•Wait for the compilation to complete (build time is typically 10-15 minutes)
•New "output" subfolder should appear in the "fpga" folder. It contains a5_sdk.sof file (Arria V
GX FPGA image in sof-format).
8.3.2. Converting FPGA-image to the board flash memory image (flash-
format)
•Open bash console and run
<PATH_TO_QUARTUS_ROOT_DIR>/nios2eds/nios2_command_shell.sh
$ <PATH_TO_QUARTUS_ROOT_DIR/nios2eds/nios2_command_shell.sh
------------------------------------------------
Altera Nios2 Command Shell [GCC 4]
Version 13.0sp1, Build 232
------------------------------------------------
•Run sof2flash programm with arguments below
sof2flash --input=<PATH_TO_A5_SOF>/a5_sdk.sof --output=./a5_hw.flash
--offset=0x01640000 --pfl --optionbit=0x00018000 --programmingmode=FPP
•Wait for the generation to complete
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