Syntacore SCR1 SDK. Altera Arria-V Starter Kit Edition User manual

SCR1 SDK. Altera Arria-V Starter Kit
Edition. Quick Start Guide
© Syntacore, [email protected]
Version 1.4, 2019-04-08

Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê2
1. Setup equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê3
1.1. Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê3
2. SDK HW assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê4
2.1. Connecting serial console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê4
2.2. Pins assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê4
3. Arria-V HW image update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê6
4. Booting the new FPGA image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê8
5. Resetting the board: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê9
6. UART connection settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê9
7. Using UART terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê10
7.1. Load binary images to the Memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê10
7.2. Example: Dhrystone run from TCM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê12
7.3. Using OpenOCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê13
7.3.1. Installing OpenOCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê13
7.3.2. Starting the OpenOCD server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê13
7.3.3. Downloading and running an image using OpenOCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê14
8. Building SDK FPGA-project for the Arria V GX SDK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê16
8.1. General structure of the SDK project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê16
8.2. Additional requirements for compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê16
8.3. Building SDK FPGA project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê17
8.3.1. FPGA firmware generation (sof-format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê17
8.3.2. Converting FPGA-image to the board flash memory image (flash-format) . . . . . . . . . . . . . Ê17
8.3.3. SDK-specific pins assignment in FPGA-project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê19
8.4. SCR1 SDK FPGA-project functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê20
8.4.1. Common project structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê20
8.4.2. Qsys SoC module structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê20
8.4.3. Description of the blocks used in the SDK project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.3.1. SCR1-core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.3.2. AXI bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.3.3. Opencores UART 16550 IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.4. Description of the IP-components of the module Qsys SOC . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê21
8.4.4.1. BUILD ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
8.4.4.2. Onchip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
8.4.4.3. DDR3 Сontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
8.4.4.4. UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
8.4.4.5. Qsys Default slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê22
9. Appendix A. SDK Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê23

10. Appendix B. SDK IRQs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê24
11. Appendix C. Software build instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.1. SCR bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.1.1. Getting the sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.1.2. Building SCR bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.2. Zephyr OS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.2.1. Getting the sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.2.2. Building Zephyr OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3. SCR1 OpenOCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3.1. Getting the latest release. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3.2. Getting the sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3.3. Building and using OpenOCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê25
11.3.4. Windows - USB JTAG Cable drivers installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ê26

Copyright by Syntacore LLC © 2017. ALL RIGHTS RESERVED. STRICTLY
CONFIDENTIAL. Information contained in this material is confidential and
proprietary to Syntacore LLC and its affiliates and may not be modified, copied,
published, disclosed, distributed, displayed or exhibited, in either electronic or
printed formats without written authorization of the Syntacore LLC. Subject to
License Agreement.
1

Revision History
Version Date Description
1.0 2017-08-01 Initial revision
1.1 2019-01-30 Modifications:
•New section: "Windows - USB JTAG Cable drivers installation"
•Sections with memory map and IRQ mapping are moved to
appendix;
•Figure numbering is introduced.
1.2 2019-03-21 OpenOCD section updated for RISC-V debug. JTAG speed
requirement added.
1.3 2019-03-29 Fix figures numbers, fix image borders
1.4 2019-04-08 Upated IMPID, BUILDID
2

This is a user guide for the Arria V GX based SCR1 SDK Arria V GX FPGA Starter Kit from the Altera.
1. Setup equipment
Arria-V based SCR1 SDK HW platform consist of three mandatory components:
1. Arria V GX FPGA Starter Kit
https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-arria-v-starter.html
2. CP2104-MINIEK
http://www.silabs.com/products/development-tools/interface/cp2104-mini-evaluation-kit
3. ARM-USB-OCD-H
https://www.olimex.com/Products/ARM/JTAG/ARM-USB-OCD-H/
Additionally, you may need some wires and cables:
1. Wires: 3 mounting wires
2. Cables:
◦USB A (m) - mini USB B (m)
◦Ethernet cat.5E
1.1. Prerequisites
FPGA board image update is done over the network, so you’ll need access to the local network with
DHCP capability. Besides of the Arria-V board, you’ll need PC, connected to the same network.
IMPORTANT
1. Before the upgrade, please, make sure the board cooling Fan is ON. If not,
turn on Fan before power on.
2. To switch on board cooling Fan, move FAN_FORCE DIP switch to ON
position at SW. Corresponding DIP is marked by cursor in the figure
below
Figure 1. DIP Switch setup
3

2. SDK HW assembly
2.1. Connecting serial console
In order to get access to the board console, it is required to mount HSMC Debug Header Breakout
Board (included in Arria-V Starter Devkit) and connect CP2104-MINIEK USB-to-UART converter to
the breakout board with external wiring, as described in this section.
2.2. Pins assignment
•Connect CP2104 pin GND to the GND pin on the HSMC Debug board
•Connect CP2104 pin TXD to the 3 pin on the HSMC Debug board
•Connect CP2104 pin RXD to the 4 pin on the HSMC Debug board
•Connect JTAG pin GND to the 38 pin on the HSMC Debug board
•Connect JTAG pin GND to the 36 pin on the HSMC Debug board
•Connect JTAG pin GND to the 34 pin on the HSMC Debug board
•Connect JTAG pin GND to the 32 pin on the HSMC Debug board
•Connect JTAG pin GND to the 30 pin on the HSMC Debug board
•Connect JTAG pin GND to the 28 pin on the HSMC Debug board
•Connect JTAG pin GND to the 26 pin on the HSMC Debug board
•Connect JTAG pin GND to the 24 pin on the HSMC Debug board
•Connect JTAG pin VREF to the 22 pin on the HSMC Debug board
•Connect JTAG pin VREF* to the 21 pin on the HSMC Debug board
•Connect JTAG pin SRSTn to the 35 pin on the HSMC Debug board
•Connect JTAG pin TDO to the 33 pin on the HSMC Debug board
•Connect JTAG pin TCK to the 29 pin on the HSMC Debug board
•Connect JTAG pin TMS to the 27 pin on the HSMC Debug board
•Connect JTAG pin TDI to the 25 pin on the HSMC Debug board
•Connect JTAG pin TRSTn to the 23 pin on the HSMC Debug board
4

IMPORTANT
For proper JTAG interface functioning JTAG clock (TckFreq) and system
clock (SysClkFreq) frequencies must satisfy the following relation:
SysClkFreq / TckFreq >= 12.
IMPORTANT
You can either connect JTAG port using mounting wires, or apply the
existing flat cable from the Olimex kit. For the Olimex kit, some rework
will be needed, it also affects couple of unused pins on the header. It is
mandatory to cut two wires (19 and 20) in the Olimex cable, as shown
below.
The following figures assume the re-worked Olimex cable is used:
1. Wires connection to the CP2104
Figure 2. CP2104 serial interface connection
2. HSMC Debug Board mounting to the Arria-V HMSC header
Figure 3. HSMC header connection
3. Resulting setup
5

Figure 4. Arria V SDK setup
3. Arria-V HW image update
1. Connect board by the ethernet-cable to the network with DHCP-server
2. Power on the board and wait for IP-address to appear at the board LCD-display (IP address may
be different):
Figure 5. IP address indication on LCD display
3. Open web browser at PC and open http-connection the IP-address from LCD
4. You will see Board Update Portal page.
5. Press button “Choose File” and set proper file for "Hardware File Name:” (as shown on the
Figure), then press the "Upload" button
Figure 6. Upload parameters definition
6

6. Wait for upload completion:
Figure 7. Upload completion message
7. Power off the board. Flash update is complete.
7