Tandy 26-3334 User manual

I '
\_,!
TABLE
OF
CONTENTS
SECTION
I.
GENERAL
1.1
1.
2
1.3
1.4
1.5
1.6
Introduction.......
5
System
Description
5...,.
Memory Map • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 8
I/O
Control
Registers
•••••••.••.•••••••••••••
9
Chip
Control
Registers
•••••••.••••••.•••••.
11
68B09E
Vector
Registers
•••••••••••••••••..•
22
SECTION
II.
SPECIFICATIONS
2.1
2.2
Technical
Physical
•••.•...•...••..••.•.
'
...•.•••......
23
.....
25
SECTION
III.
DISASSEMBLY/ASSEMBLY
3.1
3.2
3.3
Disassembly
..................................
26
Assembly
.....................................
26
512K
RAM
Upgrade
Instructions
••••••••••••••••
27
SECTION
IV.
BLOCK
DIAGRAM
4.1
4.2
NTSC
Version
..••.•.••.•...•..........•...•...
28
PAL
Version
..•.......•.••.......•••...••....•
29
SECTION
V.
THEORY
OF
OPERATION
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5
.11
5.12
5
.13
5.14
5.15
MC68B09E/MBL68B09E/HD68B09E
(ICl)
•••••••••••••
30
Memory
(RAM)
•••••••••••
·
•••••••••••••••••••••
•34
TCC1014
(VC2645QC)
•••••••••••••••••••••••••••
36
PAL
Encoder
(PAL
Version
Only)
•••••••••••••••
38
PIAs (IC4 and IC5)
•••••••••••••••••••••••••••
39
K~yboard
Interface
(ICS)
••••••••••••••••••••••
40
ROM
(
IC
2)
••••••••••••••••••••••••••••••••••••
41
DAC
Circuitry
(IC7)
••••••••••••••••••••••••••
42
SALT
Circuitry
..•................•..........
. 44
Cassette
Tape Format
Information
••••••••••••
47
RS-232C
Connector
(JK3)
••••••••••••••••••••••.
47
Cartridge
Connector
(CNl)
••••••••••••••••••••
49
Power
Transformer
•.••....•.•.•..•..•....•..•••
52
Joysticks·
..........................•.........
52
TV
Switch
Box
(NTSC
Version
Only)
••••••••••••
53
SECTION
VI.
TROUBLESHOOTING
6
.1
6.2
Introduction
•••••••••••••••.••••••••••••••••••
54
Video
Problems
................................
55
No
Display/No
Sync/Noisy
Video
..••.••••••••••
55
Wrong
Color
.................................
55
No
Color
....................................
55
Random
Character/Clear
Screen/No
Sign-on
••••
55
RGB
Problem
...•......................
•
..
•
....
55
Composite Video
Signal
Adjustment
(PAL
Version
Only)
•••..••••••..•.•...•••••••
56
-2-

u
u
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6
.10
Keyboard Problems
••••••••..•••.••••••.
.56
.56
No
Keyboard Entry/Wrong
Character
Processing
Problem
Cassette
Problems
••••••
Motor
Write
Control
Problem
Problem
Read
Problem
RS-232C
Problem
Sound
Problem
Joystick
Problem
Cartridge
Problem
•••
56
•••
56
••••
56
••••
56
•••
56
••
57
•••••••••••
57
•.•••••••••
5
7
••••
57
Power
Supply
Check
••••••••••••••••••••
•
•••
58
NTSC
Ve
rs
ion
•••.•.••••.••.••.••..•••.•••••••••
58
PAL
Version
•••
61
6.11
Major Waveforms
NTSC
Version
PAL
Version
•••••
64
••••••
64
••••••
70
SECTION
VII.
512K
EXPANSION
RAM
CARD
PCB
VIEWS
•••••••••••••••••••••••••••••••••••••
78
ELECTRICAL
PARTS
LIST
•••••••••••••••••.•••
79
SECTION
VIII.
NTSC
VERSION
PCB
VIEWS
•••••••••••••••
ELECTRICAL
PARTS
LIST
EXPLODED
VIEW
PARTS
LIST. ...............
...............................
EXPLODED
VIEW
SEMICONDUCTOR
INFORMATION
.82
.84
••
90
••
91
•••••••
93
SCHEMATIC
DIAGRAM•••••••••••••••••
•••••••
103
SECTION
IX.
PAL
VERSION
PCB
VIEWS
••••••••••••••••
••••••..••.•••••
108
ELECTRICAL
PARTS
LIST
EXPLODED
VIEW
PARTS
LIST•
• • • • • • . . • • • • • • • • • . • • • •111
•...•...•..••.•••.••••
119
• • • • • • • • • • • • • • • • • • • . • • • • • • • • • • •
•.
. 121
EXPLODED
VIEW
SEMICONDUCTOR
INFORMATION
SCHEMATIC
DIAGRAM
•••••••••
••••••
122
•
•••••
126

1-1.
1-2.
1-3.
3-1.
3-2.
3-3.
3-4.
4-1.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
LIST
OF
FIGURES
Color
Computer 3
Installation
•••••••••••••••
7
Color
Computer 3
Memory
Map
•••••••••••••••••
8
Memory
Map
for
SAM
Control
Register
•••••••••
21
Removal
of
Top Cover
...........•....••.•.•••
26
Removal
of
Main
PCB
...........•..••....•..••
26
Main
PCB
•••••••.••••....••.••••••••••••••••
•
27
512K
RAM
Card
•••••••••••••••••••••••••••••••
27
Block
Diagram
•..••.•••..•••.•••..••••••••••.
28
NTSC
Version
..•••••••••.•••.•••••.•.•..••..
•
28
PAL
Version
•..•.•.••••.•...•..•.•.•..•...•••
29
MC68B09E
Progranuning Model
••••••••••••••••••
30
MC68B09E
Pin
Assignments
••••••••••••••••••••
31
MC68B09E
Read/Write
Timing
at
0.89
MHz
••••••
33
DRAM
Block
Diagram
..•.•..•••.••.•.•.••••••••
34
DRAM
Timing
...................................
. 35
Color
Computer 3
Address
Decoding
•••••••••••
36
MMU
Block
Diagram
....••..•...•..........•..•
. 37
PIA
Block
Diagram
•••••••••••••••••••••••••••
39
Color
Computer 3 Keyboard
Array
•••••••••••••
40
DAC
Block
Diagram
(IC7)
•••••••••••••••••••••
42
SALT
Block
Diagram
(IC8)
••••••••••••••••••••
44
Color
Computer 3 Power
Supply
•••••••••••••••
45
I/O
Circuitry
•••••••••••••••••••••••••••••••46
RS-232C
Connector
Pinout
••••••••••••••••••••
48
Joystick
Schematic
••••••••••••••••••••••••••
52
Antenna
Switch
Box
Schematic
•••••••••••
.-
••••
53
LIST
OF
TABLES
1
Line
Printer
Variables
••••••••••••••••••••••
50
2
Alternate
Line
Printer
Variable
Values
••••••
50
3
Cartridge
Connector
Signals
•••••••••••••••••
51
-4-
'.))
'·.,
__
,/

SECTION
I.
GENERAL
1.1
Introduction
The
Color
Computer 3
is
a
refined
version
of
Tandy's
popular
Color
Computer
2.
It
is
designed
to
provide
the
same
reliable
operation
as
its
predecessor,
but
it
incorporates
the
latest
in
electronic
technology.
Figure
1-1
shows a
typical
installation
of
the
Color
Computer
3.
The
Color
Computer 3
contains
an
internal
BASIC
program
in
ROM
which
is
accessed
when
the
unit
is
powered
up.
Other
program
modules/cartridges
may
be
inserted
into
the
receptacle
on
the
right
side
of
the
unit.
An
optional
Multi-pak
Interface
module
allows
up
to
four
program
paks
to
be
installed
at
the
same
time,
with
selection
of
the
specific
module
active
at
any
one
time
selected
either
by
software
or
by a
switch
on
the
Multi-pak
Interface.
Additional
peripheral
devices,
such
as
an
external
disk
drive,
may
be
added
to
the
Color
Computer 3
for
additional
memory
storage
and
retrieval.
All
input
and
output
ports
for
the
Color
Computer
3,
with
the
exception
of
the
program
module/cartridge
slot
and
the
RGB
monitor
output
(for
CM-8),
are
located
on
the
rear
panel
of
the
unit.
These
include
the
joystick
input
ports
(right
and
left),
Serial
I/O,
Cassette
I/O,
TV
output
jack
(for
standard
color
television
set
and
composite
monitor),
POWER
ON/OFF
switch
and
RESET
switch.
A
recessed
channel
switch
(for
selecting
either
channel
on
the
TV
-
3/4
for
NTSC
and
1/2
for
PAL
version)
is
also
located
on
the
rear
panel
of
the
unit.
'
Note:
Before
installing
any
peripheral
device,
always
remember
to
unplug
the
Color
Computer's
power
cord.
This
wilT'prevent
damage
to
the
device
or
to
the
Color
Computer
3.
1.2
System
Description
The
primary
functions
of
the
Color
Computer 3
are
performed
by
four
Large
Scale
Integration
eLSI)
chips,
plus
Random
Access
Memory
(RAM)
and
Read
Only
Memory (ROM).
These
four
chips
are
labeled
on
the
block
diagram
as
CPU,
ACVC
and two
PIAs.
With
only
these
four
chips,
plus
Random
Access
Memory
(RAM),
Read Only
Memory
(ROM)
and
a power
supply,
the
Color
Computer 3
will
operate
and
provide
video
output
(RF,
Composite,
Analog
RGB). However,
to
allow
communication
with
the
outside
world,
I/O
interfaces
must
be
added.
The
main
component
of
any
computer
system
is
the
Central
Processing
Unit
(CPU,
ICl).
It
is
the
function
of
the
CPU
to
provide
or
request
data
and
select
the
proper
address
for
this
data.
In
addition,
the
CPU
is
capable
of
performing
a
limited
set
of
mathematical
and
logical
operations
on
the
data.
ROM
(IC2)
has
the
function
of
providing
the
CPU
with
a
predefined
set
of
instructions.
Without
ROM,
the
CPU
would
run
wild
and
randomly
execute
instructions.
In
normal
operation,
the
CPU
jumps
to
the
start
address
in
ROM,
after
the
reset
switch
has
been
pressed,
and
then
performs
the
reset
program
to
set
up
all
of
the
programmable
devices.
Following
this,
the
BASIC
interpreter
residing
in
ROM
is
in
control
of
the
CPU.

RAM
(IC16
-IC19)
provides
storage
for
the
programs
and/or
data
currently
being
executed.
In
the
standard
unit,
these
four
ICs
are
64K
x 4
but
may
be
upgraded
to
sixteen
256K
x 1 ICs
as
an
option.
(See
Paragraph
3.3
on
page
28
for
instructions.)
In
addition,
the
same
RAM
is
used
to
generate
the
video
display.
Normally,
no
conflict
will
be
observed
because
the
program
will
use
one
portion
of
RAM
and
the
display
will
use
another.
During
normal
usage,
the
BASIC
interpreter,
located
in
ROM,
will
control
the
execution
of
programs
located
in
RAM.
A
central
component
in
the
Color
Computer 3
is
the
Advanced
Color
Video
Chip
(IC6).
This
chip
provides
refresh
and
address
multiplexing
for
the
RAM.
It
also
provides
all
of
the
system
timing
and
device
selection.
ACVC
comprises
the
VDG
(Video
Display
Generator)
function
which
supports
High-Resolution
mode,
in
addition
to
I
all
other
modes
included
in
the
Color
Computer
2.
Dhring
High-Resolution
mode,
it
gene~ates
40 x 24
or
80 x 24
text
screen,
knd 320 x 192
or
640 x
192
graphics
Screen.
It
is
also
designed
to
ohtput
two
different
video
signals
I -
composite
video
and
analog
RGB.
I
ACVC
can
expand
memory
space
up
to
512K
bytes.
Hkving
a
built-in
MMU
(Memory Managkment
Unit),
it
can
I
support
2
banks
of
256K-byte
RAM,
each
with
a
9rline
address
bus,
even
though
the
CPU
possesses
only
16
address
linesl
I
The
remaining!
circuitry
in
the
Color
Computer 3
is
devoted
to
Input/Output
(I/O)
communication.
The
most
important
part
of
this
circuitry
is
the
keyboard,lwhich
allows
the
operator
to
enter.information.
Other
I/O
circuits
1re
provided
to
allow
joystick
input,
cassette
input
and
I •
output,
and
Rr-232C
input
and
output.
-6-

c
i
MODEM
SERIAL
PRINTER
•
c·
TV
CASSETTE RECORDER
~
'"?Q;~'h,.,rf'Rr\'~~
J
e:r{W~
COLOR COMPUTER 3
RIGHT
LEFT
JOYSTICK JOYSTICK
,,
.....
/.
.·
/
VIDEO
AUDIO
'-!
=
[[[[]
D
Ill
0
'\
......
[2J
'=-
PROGRAM
PAK
I I
--1
MUL
Tl-PAK
{
...)
c::__=i
INTERFACE
:~:--1~
l
I
I
,_
")
Figure
1-1.
Color
Computer 3
Installation
r
MONITOR
ANALOG
RGB
MONITOR
CM-8

1.3
Memory
Map
Figure
1-2
shows
the
breakdown
of
the
large
blocks
of
memory
in
the
Color
Computer
3.
The
rest
of
the
section
itemizes
the
following
registers:
•
1/0
Control
Register
•
Chip
Control
Register
• 68B09E
Vector
Register
S7FFFF
S7FFOO
S7EOOO
S7COOO
S7AOOO
$78000
$70600
$70400
$70000
S6EOOO
S6COOO
$68000
$60000
$00000
,...._
'
6
c
R
SUPER EXTENDED BASIC
CARTRIDGE ROM
COLOR BASIC
EXTEND COLOR BASIC
STANDARD TEXT SCREEN
.
HIGH RESOLUTION
TEXT SCREEN
HIGH RESOLUTION
GRAPHIC SCREEN
-=::::
8809E
VECTOR,
ONTROL
EGISTER, 1/0
Figure
1-2.
Color
Computer
3
Memory
Map
-8-
Q
N
~
2
0
a:
Q
.(0
~
2
<1'.
a:
'!)
:::J
0
a:
I-
z
0
u
c5
::::::
~
0
a:
I-
a..
w
u
x
!:!:!.
l£
N
~
~)
l!l
2
<1'.
a:

u
(
\_)
1.4
I/O
Control
Registers
FFOO
-FF03 PIA
IC5
FFOO:
FFOl:
FF02:
FF03:
BIT 0
=
BIT
1
=
BIT
2
=
BIT 3
BIT 4
=
BIT
5
=
BIT
6
=
BIT
7
BIT 0
BIT 1
BIT 2
=
BIT
3
=
BIT 4
=
BIT 5
=
BIT 6
=
BIT 7 =
KEYBOARD
ROW
1 and
right
joystick
switch
1
KEYBOARD
ROW
2 and
left
joystick
switch
l
KEYBOARD
ROW
3 and
right
joystick
switch
2
KEYBOARD
ROW
4 and
left
joystick
switch
2
KEYBOARD
ROW
5
KEYBOARD
RO}'l
6
KEYBOARD
ROW
7
JOYSTICK
COMPARISON
INPUT
Control
of
HSYNC
(63.
Sµs) { 0
1 =
IRQ*
to
CPU
Disabled
Interrupt
=
IRQ*
to
CPU
Enabled
Control
of
Interrupt
{
o
1
=
Flag
set
on
the
Polarity
falling
edge
of
HS
=
Flag
set
on
the
Normally 1:
SEL
1:
1 Always
I Always
Not
used
rising
edge
of
HS
0
=
Changes
FFOO
to
the
data
direction
LSB
of
the
two
analog
MUX
select
lines
Horizontal
sync
interrupt
flag
BIT 0 =
KEYBOARD
COLUMN
1
BIT
1
=
KEYBOARD
COLUMN
2
BIT 2
=
KEYBOARD
COLUMN
3
BIT 3
=
KEYBOARD
COLUMN
4
BIT 4
=
KEYBOARD
COLUMN
5
BIT
5 =
KEYBOARD
COLUMN
6
BIT
6
=
KEYBOARD
COLUMN
7/RAM
SIZE
OUTPUT
BIT 7 =
KEYBOARD
COLUMN
8
register
BIT 0
Control
of
VSYNC
(16.667ms) {
Ol
=
IRQ*
to
CPU
Disabled
Interrupt
=
IRQ*
to
CPU
Enabled
BIT
1
Control
of
Interrupt
Polarity
.(
o
1 =
sets
flag
on
falling
edge
FS
BIT
BIT
BIT
BIT
BIT
l =
sets
flag
on
rising
edge
FS
2
=
NORMALLY
1: 0
=
changes
FF02
to
the
data
direction
register
3
=
SEL
2:
MSB
of
the
two
analog
MUX
select
lines
4 =
5
=
6
1 Always
1 Always
Not
used
BIT 7 =
Field
sync
interrupt
flag
-9-

FF20 -FF23 PIA IC4
FF20:
FF21:
FF22:
FF23:
BIT 0
CASSETTE
DATA
INPUT
BIT 1
=
RS-232C
DATA
OUTPUT
BIT 2 6 BIT
D/A
LSB
BIT 3 = 6 BIT D/A
BIT 4 6 BIT D/A
BIT 5 = 6 BIT D/A
BIT 6
=
6 BIT D/A
BIT
7 =
6 BIT
D/A
MSB
BIT 0
Control
of
the
CD
(RS-232C
status)
Interrupt
{~:
FIRQ*
to
CPU
Disabled
FIRQ*
to
CPU
Enabled
Control
of
Interrupt
{0
1 =
sets
flag
on
falling
edge
CD
Polarity
=
sets
flag
on
rising
edge
CD
BIT 1
BIT
BIT
BIT
BIT
BIT
BIT
2 =
Normally
1:
0 =
changes
FF20
to
the
data
direction
register
3 =
Cassette
Motor
Control:
0 =
OFF
1 =
ON
4 = 1 Always
5 = 1 Always
6 = Not Used
7 =
CD
Interrupt
Flag
BIT 0 = RS-232C
DATA
INPUT
BIT 1 =
SINGLE
BIT
SOUND
OUTPUT
BIT 2 =
RAM
SIZE
INPUT
BIT 3 =
RGB
Monitor
Sensing
INPUT
BIT 4 =
VDG
CONTROL
OUTPUT
BIT
5 =
VDG
CONTROL
OUTPUT
BIT 6 =
VDG
CONTROL
OUTPUT
BIT
7 =
VDG
CONTROL
OUTPUT
BIT 0
Control
of
the
Cartridge
Interrupt
BIT 1
Control
of
Interrupt
Polarity
BIT 2
Normally
1:
0 =
changes
BIT 3 = Sound
Enable
BIT 4
=
1 Always
BIT 5 = 1 Always
BIT 6 = Not
used
BIT 7
=
Cartridge
Interrupt
Flag
css
GMO
&
UPPER/LOWER
CASE*
GMl
&
INVERT
GM2
A*/G
{~
{~
FF22
= FIRQ*
to
CPU
Disabled
= FIRQ*
to
CPU
Enabled
=
sets
flag
on
falling
edge
CART*
=
sets
flag
on
rising
edge
CART*
to
the
data
direction
register
'FF40 -FFBF: Not
used
Note:
FF22, FF23
are
duplicated
in
tccl014
(VC2645QC),
and
V.D.G
Control
Bit
(Bit
3
through
Bit
7)
affects
this
IC (TCC1014)
only
•
.....
-10-

1.5
Chip
Control
Registers
'
.I
FF90 -
FFDF
u
ACVC
IC6
FF90:
Initialization
Register
0 (INITO)
BIT
7 =
coco
I
=
Color
Computer 1 and 2
Compatible
BIT 6
=
M/P
1
=
MMD
enabled
BIT 5
=
IEN
1
=
Chip
IRQ
output
enabled
BIT 4
=
FEN
1
=
Chip
FIRQ
output
enabled
BIT 3
=
MC3
1
=
DRAM
at
XFEXX
is
constant
BIT 2
=
MC2
1
Standard
SCS
BIT I
=
MCI
ROM
map
control
(See
table
below)
BIT 0
=
MCO
ROM
map
control
(See
table
below)
MCI
MCO
ROM
mapping
0 x I6K
Internal,
16K
External
1 0
32K
Internal
1 1
32K
External
(except
for
vectors)
FF9I:
Initialization
Register
1
(INITI)
BIT 7
BIT 6
BIT 5
=
TINS
Timer
Input
Select:
1
=
70
nsec
I 0
=
63
µsec
BIT 4
BIT 3
BIT 2
L)
BIT I
BIT 0 =
TR
MMU
Task
Register
Select
FF92:
Interrupt
Request
Enable
Register
(IRQENR)
BIT 7
BIT 6
BIT 5 =
TMR
Interrupt
from Timer
enabled
BIT 4 =
HBO
RD
Horizontal
Border
IRQ
enabled
BIT 3 =
VBORD
Vertical
Border
IRQ
enabled
BIT 2 = EI2
Serial
Data
IRQ
enabled
BIT 1 =
Ell
Keyboard
IRQ
enabled
BIT 0 =
EIO
Cartridge
IRQ
enabled
FF93:
Fast
Interrupt
Request
Enable
Register
(FIRQENR)
BIT 7
BIT 6
BIT 5
=
TMR
Interrupt
from Timer
enabled
BIT 4
HBO
RD
Horizontal
Border
FIRQ
enabled
BIT 3 =
VBORD
Vertical
Border
FIRQ
enabled
BIT 2 = EI2
Serial
Data
FIRQ
enabled
BIT I
Ell
Keyboard
FIRQ
enabled
BIT 0 =
EIO
Cartridge
FIRQ
enabled
u

FF94:
FF95:
FF96:
FF97:
FF98:
FF99:
Timer Most
Significant
Nibble
Timer
Least
Significant
Byte
TIMER:
This
is
a
12-bit
interval
timer.
When
a
value
is
loaded
into
the
MSB,
the
count
is
automatically
begun.
The
input
clock
is
either
14
MHz
or
horizontal
sync,
as
selected
by
TINS
(bit
5
of
FF91).
As
the
count
falls
through
zero,
an
interrupt
is
generated
(if
enabled),
and
the
count
is
automatically
reloaded.
Reserved
Reserved
Video
Mode
BIT 7
BP
BIT
6
BIT 5
=
BPI
BIT 4
=
MOCH
BIT
3 =
H50
BIT
2 =
LPR2
BIT
1
=
LPRl
BIT 0 =
LPRO
LPR2
0
0
0
0
1
1
1
1
Register
LPRl
0
0
1
1
0
0
0 =
alphanumeric,
1 =
bit
plane
1 =
Burst
phase
inverted
1
=
monochrome
(on
composite)
1
=
50
Hz
vertical
sync
Lines
per
row
(See
table
below)
Lines
per
row
(See
table
below)
Lines
per
row
(See
table
below)
LPRO
Lines
per
character
row
0 one
(Graphics
modes)
1 two (Coco 1 and
CoCo
0
three
(Coco 1 and Coco
1
eight
0
nine
1
(reserved)
2
only)
2
only)
1 0
twelve
(CoCo
1 and Coco 2
only)
1 1
(reserved)
Video
Resolution
Register
BIT 7
BIT
6
=
LPFl
Lines
per
field
(See
table
below)
BIT 5
=
LPFO
Lines
per
field
BIT
4
=
HRES2
Horizontal
resolution
(See
Video
resolution
17)
BIT
3 =
HRESl
Horizontal
resolution
BIT 2
=
HRESO
Horizontal
resolution
BIT
1
=
CRESl
Color
resolution
(See
Video
resolution)
BIT 0
=
CRESO
Color
resolution
LPFl
LPFO
Lines
per
field
0 0 192
0
1
200
1
0
Reserved
1 1
225
-12-
on
page
.~.
':
·.
) .

FF9A:
Border
Register
(All
bits
are
0
for
CoCo
1
and Coco 2
compatibility).
BIT 7
BIT
6
u
BIT
5
=
REDl
Most
significant
red
bit
BIT 4
=
GRNl
Most
significant
green
bit
BIT
3
=
BLUl
Most
significant
blue
bit
BIT
2
=
REDO
Least
significant
red
bit
BIT
1 =
GRNO
Least
significant
green
bit
BIT
0
=
BLUO
Least
s
igni
fie
ant
blue
bit
FF9B:
Reserved
FF9C:
Vertical
Scroll
Register
BIT 7
BIT 6
BIT 5
BIT
4
BIT
3
=
VSC3
(Vert.
Scroll)
BIT 2
=
VSC2
BIT
1 =
VSCl
BIT 0
=
vs
co
NOTE:
In
the
CoCo
mode,
the
VSC's
must
be
initialized
to
OF
hex.
FF9D:
Vertical
Offset
1
Register
BIT 7
=
Yl8
(Vert.
Offset)
BIT 6
=
Yl7
BIT 5
=
Yl6
BIT 4
=
Yl5
I
BIT 3
=
Yl4
L'
.
'
BIT 2
=
Yl3
BIT
1 =
Yl2
BIT 0
=
Yll
FF9E:
Vertical
Offset
0
Register
.BIT
7
=
YlO
(Vert.
Offset)
BIT 6
=
Y9
BIT 5
=
YB
BIT
4
=
Y7
BIT
3
=
Y6
BIT
2
=
Y5
BIT
1
=
Y4
BIT
0 =
Y3
NOTE:
In
Coco mode, Yl5 -
Y9
are
not
effective,
and
are
controlled
by
SAM
bits
F6
-
FO.
Also
1n
Coco mode, Yl8 -Yl6
should
be
1,
all
others
o.
u
_l
"l-

"
FF9F:
Horizontal Offset 0 Register
BIT 7
HVEN
Horizontal Virtual
Enable
BIT 6 =
X6
Horizontal
Offset
address
BIT 5 =
XS
Horizontal
Offset address
BIT 4 =
X4
Horizontal
Offset address
BIT 3
X3
Horizontal Offset address
BIT 2 X2
Horizontal
Offset
address
BIT 1 Xl Horizontal Offset address
BIT 0 XO Horizontal
Offset
address
NOTE: HVEN enables a horizontal screen width of 128 bytes regardless of
the HRES bits and CRES bits selected. This will allow a "virtual" screen
somewhat larger than the displayed screen. The user can move the "window"
(the displayed screen) by means of the horizontal offset bits. In
character mode, the screen width is 128 characters regardless of
attribute (or 64, if double-wide is selected).
-14-
·~',
(~
J

u
u
Memory Management
Unit
(MMU)
XFFAO
-
XFFAF,
6
bits
(Write
only)
The
8-bit
CPU
in
the
Color
Computer 3
can
directly
address
only
64K
bytes
of
memory
with
its
16
address
lines
(AO
-
Al5).
The memory management
unit
(MMU)
extends
the
address
lines
to
19
(AO
-
Al8).
This
allows
the
computer
to
address
up
to
512K
bytes
of
memory ($00000 -$7FFFF).
The
MMU
consists
of
a
multiplexer
and a 16 x
6-bit
of
RAM
array.
Each
of
the
6-bit
elements
in
this
RAM
array
is
an
MMU
task
register,
and
the
task
registers
are
used
by
the
computer
to
determine
the
proper
8K
segment
of
memory
to
address.
These
registers
are
divided
into
2
sets,
8
registers
per
set.
The
TR
bit
of
FF91
(task
register
select
bit)
determines
which
set
is
selected.
The
relationship
between
the
data
in
the
task
register
and
the
generated
address
is
as
follows:
Bit
Corresponding
memory
address
D0-05
(CPU
DATA)
Al3-Al5
___
..._
TR
bit
AO-A3
SELECT
D5
D4
Al8 Al7
Multiplexer
D3
Al6
D2
Al5
RAO-
RA3
Dl
DO
Al4
Al3
Douti------>..
Al3-Al8
(Extended addr'esses)
When
the
CPU
needs
to
access
memory
outside
the
standard
I/O
and
control
range
(XFFOO
-XFFFF),
CPU
address
lines
Al3 -Al5
and
the
TR
bit
determine
the
address
of
the
task
register
which
the
MMU
will
access
while
SELECT
is
low.
When
the
CPU
writes
data
to
the
MMU,
AO
-
A3
determine
the
address
of
the
task
register
to
be
written
to
when
SELECT
goes
high.
-l'i-

The
data
from
the
MMU
is
then
used
as
the
upper
6
address
lines
(Al3 -Al8)
for
memory
access,
according
to
the
following:
TR
AlS Al4 Al3
(Address
range)
MMU
location
address
0 0 0 0
xoooo
-XlFFF
FFAO
0 0 0 1
X2000
-
X3FFF
FF
Al
0 0 1 0 X4000 -
XSFFF
FFA2
0 0 1 1 X6000 -
X7FFF
FFA3
0 1 0 0
X8000
-
X9FFF
FFA4
0 1 0 1
XAOOO
-
XBFFF
FFAS
0 1 1 0
xcooo
-
XDFFF
FFA6
0 1 1 1
XEOOO
-
XFFFF
FFA7
1 0 0 0
xoooo
-XlFFF
FFA8
1 0 0 1 X2000 -
X3FFF
FFA9
1 0 1 0 X4000 -
XSFFF
FFAA
1 0 1 1 X6000 -
X7FFF
FFAB
1 1 0 0 X8000 -
X9FFF
FFAC
1 1 0 1
XAOOO
-
XBFFF
FFAD
1 1 1 0
xcooo
-
XDFFF
FFAE
1 1 1 1
XEOOO
-
XFFFF
FFAF
It
is
important
to
note
that,
in
order
for
the
MMU
to
function,
the
CoCo
bit
of
FF90
must
be
cle.ared,
and
the
M/P
bit
of
FF90
must
be
set.
Prior
to
doing
this,
the
desired
addressing
information
for
each
segment
must
be
loaded
into
the
designated
set
of
task
registers.
For
example,
if
a
standard
64K
map
is
desired
in
the
top
of
512K
RAM,
with
the
TR
bit
set
to
0,
the
following
values
should
be
pre-loaded
into
the
MMU:
MMU
Location
Data
(Hex)
Data
(Bin)
Address
address
.range
FFAO
38 111000 70000 -71FFF
FF
Al
39 111001 72000 -73FFF
FFA2
3A
111010 74000 -75FFF
FFA3
3B
111011 76000 -77FFF
FFA4
3C
111100 78000 -79FFF
FFAS
3D
111101
7AOOO
-
7BFFF
FFA6
3E
111110
7COOO
-
7DFFF
FFA7
3F
111111
7EOOO
-
7FFFF
NOTE:
Data
loaded
can be
selected
freely
within
the
range
of
$00 -$3F.
-16-

(~';
\_)
COLOR
PALETTE
FFBO
-
FFBF:
16
addresses,
6
bits
each
For
the
RGB
output,
the
bits
are
defined
as
follows:
Data
Bit
DS
D4
D3 D2
Dl
DO
....
Corresponding
RGB
output
Rl
Gl
Bl
RO
GO
BO
For
the
Composite
output,
the
bits
are
defined
as
follows,
where I
is
intensity
level
and P
is
phase:
Data
Bit
DS
D4
D3 D2
Dl
DO
Corresponding
composite
I1
IO
P3 P2
Pl
PO
output
Some
Color
Examples:
RGB
Composite
Color
Binary
Hex
Binary
Hex
White
111111
(3F)
110000
(30)
Black
000000
(00)
000000
(00)
Bright
Green
010010
(12)
100010
(22)
Medium Green 010000
(10)
010010
(12)
Dark
Green
000010
(02)
000010
(02)
Medium Magenta 101000
(28)
010101
(15)
For
CoCo
compatibility,
the
following
values
should
be
loaded
upon
initialization.
(NOTE:
These
are
the
RGB
values.)
FFBO
Green
(12)
FFBl
Yellow
(36)
FFB2
Blue
(09)
FFB3
Red
(24)
FFB4
Buff
(3F)
FFB5
Cyan
(10)
FFB6
Magenta (2D)
FFB7
Orange
(26)
FFB8
Black
(00)
FFB9
Green
(12)
FFBA
Black
(00)
FFBB
Buff
(3F)
FFBC
Black
(00)
FFBD
Green
(12)
FFBE
Black
(00)
FFBF
Orange
(26)
NOTE:
For
the
PAL
version,
ignore
the
table
attributed
to
composite.
-17-

VIDEO
RESOLUTION
The
combination
of
HRES
and
GRES
bits
determine
the
resolution
of
the
screen.
The
following
resolutions
are
supported:
("')
'
Alphanumerics:
BP
=
0,
CoCo
=
0
~
HRES2
HRESl
HRESO
CRESl
CRESO
e
32
character
0
-
0
-1
40
character
0
-1 -1
80
character
1 -1 -1
Graphics:
BP
=
1,
CoCo
= 0
Pixels
Colors
HRES2
HRESl
HRESO
CRESl
CRESO
640 4 1 1 1 0 1
640 2 1 0 1 0 0
512 4 1 1 0 0 1
512 2 1 0 0 0 0
320 16 1 1 1 1 0
320 4 1 0 1 0 1
256 16 1 1 0 1 0
256 4 1 0 0 0 1
256 2 0 1 0 0 0
160 16 1 0 1 1 0
In
addition
to
the
above
modes,
the
previous
CoCo
modes
are
available.
COLOR
COMPUTER
MODE
SELECTION
MC6883
(SAM)
DISPLAY
MODE
REG.
FF22
V2
Vl
VO
7 6 5 4 3
Alphanumerics
0 0 0 0
x x
0 css
Alphanumerics
Inverted
0 0 0 0
x x
0 css
Semigraphics
- 4 0 0 0 0
x x
0
x
64 X 64
Color
Graphics
0 0 1 1 0 0 0 css
128 X 64
Graphics
0 0 1 1 0 0 1 css
128 X 64
Color
Graphics
0 1 0 1 0 1 0 css
128 X 96
Graphics
0 1 1 1 0 1 1 css
128
x
96
Color
Graphics
1 0 0 1 1 0 0 css
128
x
192
Graphics
1 0 1 1 1 0 1 css
128
x
192
Color
Graphics
1 1 0 1 1 1 0 css
256
x
192
Graphics
1 1 0 1 1 1 1 css
-18-

ALPHANUMERIC
MODES
Text
screen
memory:
/
(Character
byte)
I Even
Byte
\..._.)
--------------------------
BIT 7
..:~
BIT 6
Character
bit
6
BIT 5 =
Character
bit
5
BIT 4
Character
bit
4
BIT 3
Character
bit
3
BIT 2
Character
bit
2
BIT 1
Character
bit
1
BIT 0
=
Character
bit
0
Odd
Byte
(Attribute
byte)
-------------------------
BIT 7
=
BLINK
Characters
blink
at
1/2
sec.
rate
BIT 6
=
UNDLN
Characters
are
underlined
BIT 5
=
FGND2
Foreground
color
bit
(pallette
addr.)
BIT 4
=
FGNDl
Foreground
color
bit
(pallette
addr.)
BIT 3
=
FGNDO
Foreground
color
bit
(pallette
ad-dr.)
BIT 2
=
BGND2
Background
color
bit
(pallette
addr.)
BIT 1
=
BGNDl
Background
color
bit
(pallette
addr.)
BIT 0
=
BGNDO
Background
color
bit
(pallette
addr.)
NOTE:
Attributes
are
not
available
when
CoCo
=
1.
(
'
\_)
-19-

GRAPHICS
MODES
16
Color
Modes: (CRESl
1,
CRESO
=
O)
Byte from
DRAM
Bit
7 PA3,
First
Pixel
(\
Bit
6 PA2,
First
Pixel
}
Bit
5 PAl,
First
Pixel
Bit
4
PAO,
First
Pixel
,,._
Bit
3 PA3, Second
Pixel
Bit
2 PA2, Second
Pixel
Bit
1 PAl, Second
Pixel
Bit
0
PAO,
Second
Pixel
4
Color
Modes: (CRESl
0,
CRESO
=
1)
Byte from
DRAM
Bit
7 PAl,
First
Pixel
Bit
6
PAO,
First
Pixel
Bit
5 PAI, Second
Pixel
Bit
4
PAO,
Second
Pixel
Bit
3
PAl,
Third
Pixel
Bit
2
PAO,
Third
Pixel
Bit
I PA!,
Fourth
Pixel
Bit
0
PAO,
Fourth
Pixel
2
Color
Modes: (CRESl =
O,
CRESO
=
0)
Byte
from
DRAM
Bit
7
PAO,
First
Pixel
Bit
6
PAO,
Second
Pixel
Bit
5
PAO,
Third
Pixel
Bit
4
PAO,
Fourth
Pixel
Bit
3
PAO,
Fifth
Pixel
.·~,
Bit
2
PAO,
Sixth
Pixel
(
Bit
1
PAO,
Seventh
Pixel
('v(
Bit
0
PAO,
Eighth
Pixel
I
Pallette
Addresses
PA3 PA2
PAI
PAO
Address
of
Contents
Displayed
0 0
o·
0
FFBO
0 0 0
1
FFBl
0
0 1
0
FFB2
0 0 I I
FFB3
0
I
0
0
FFB4
0 1 0 1
FFBS
0 I I
0
FFB6
0 I 1 I
FFB7
I 0
0
0
FFB8
1 0 0 1
FFB9
I 0 I 0
FFBA
1 0 1 1
FFBB
I 1 0 0
FFBC
I 1 0 1
FFBD
1 1 1
0
FFBE
1 1 1 1
FFBF
-20-