Technics ST-9038 User manual

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PART 11
Synthesizer Tuner
CIRCUIT EXPLANATION MANUAL
sr-9038
Têchnics
SERVICE SUB.DEPT. STEREO DEPT.
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
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iPART II
CONTENTS
1. PLL Synthesizer .
Synthesizer
Block diagram of synthesizer section.
i -3 Interface circuit.
Prescaler
Programmable frequency divider. . ,
1-5-1 Operational description of lG
1-5-2 Frequency division in fixed code pressetting. . . . . .
1-5-3 Frequency division in variable code presetting . . . .
1-5-4 Programmable frequency dividing ratio. . . .
1-5-5 Faulty operation prevent¡ng eircuit.
1-6 Crystal frequency divider .
1-7 Phase comparator and low-pass filter.
1-1
1-2
1
1
1
1
2
3
3
5
7
I
I
I
11
1-4
1-5
2-2
3-4
3-5
1-7-1
1-7-2 Functions of phase detector, charge pump and LPF
Shock noise preventing circuit. . . . .
.....10
.....10
.....11
1-8 VCO (Voltage control oscillator). . .
2. Circuit for start and stop pulse generation in auto tuning, and adjacent
circuits ....12
2-1 station selector step scan
2-1-1 Flip-flopcircuit. .12
2-1-2 Start pulse generation (differential circuit)
2-1-3 Stop pulse generation
2-1-4 Adjacentcircuits
Operat¡ons with station selector at fine and standard . . .
2-2-1 Outline of auto tuning. . .
2-2-2 Clock pulse oscillator c¡rcuit and adjacent circuits
12
't3
14
14
16
17
.15
.16
2-2-3 Extraction of tuning signal
3. Operation of the tuning counter . . . . . 18
3-1 Operational description of lC . . . .
3-2
3-3 and clock pulse generator
3-3-1 Autotun¡ng.....
3-3-2 Step scan. . .
3-3-3 Manual tuning
Counter circuit for frequency code
3-4-1 Counteroperation.
3-4-2 Presettingoperation
3-4-3 Presetting operation (for the United States)
Last one memory
4. Frequency indicator circuit.
4-1 7-segment indicator tubes 32
32
33
4-2 Frequency indication I
4-3 Frequency indication II. .
5" Bus line ....35
Tuning frequency section
M code
S code
+B code
6. Tuning RS latch initial setting circuit
5-1
5-2
5-3
5-4
18
23
24
25
25
26
27
28
29
30
31
32
35
36
36
36
37
397. Schematic Diagram
.sT.9038 (M), (MC)
.sr-9038 (E), (XE), (XGF), (XGH), (XA), (X)

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PART II PLL SYNTHES]ZER
t1. PLL Synthesizer
1-1 Synthesizer
Dividing or multiplying a certain frequency or combining frequencies to obtaín the desired
frequency is called "frequency synthesis" A frequency synthesizer is a unit used to achieve this
purpose.
1-2 Block diagram of synthesizer section
98.3 (98.8) - 118.6 MHz 1/A 1/983 (1/988) -1/11a6
12.5 KHz
1 / 1024 Xtal
12.8 MHz
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" Frequency range 87.6 (88.1) - 107.g MHz
. Local oscillator frequency gB.3 (gB.B) - 118.6 MHz
. 1/8 prescaler 12.2815 (12.95) - 14.B25MHz
" Dividing ratio of programmable
frequency divider 983 (988) - 1 1Bo
. Comparison frequency 12.5 k1z
Note) Values in parentheses are specif ied for the U.S.A.
When a broadcast signal of 87.6 (88.1) to 1Oj.g MHz enters the receiver, the local oscillator
frequency (Vco) becomes 98.3 (98.8) to 118.6 MHz. The frequency is divided ar rhe ratio of 1/g
by the prescaler through the interface, and further divided ar rhe rario of 1/gB3 (1i98g) - 1/11g6
by the programmable frequency divider according to the input frequency thus obtaining 12.5 KHz.
On the other hand, a12.8MHz frequency from a high precision crystal oscillator is divided at the
ratio of 1/1024 to obtain 12.5 KHz, the standard comparison frequency. When these two
frequencies are added to the phase comparaTor, itsoutput is the phase difference. By passing the
output through the low-pass filter, a positive or negative voltage can be obtained in proportion to
the phase difference between the two frequencies. Vco is controlled by this voltage. As is evídent
in the above description, the composition of this circuit is that of a pLL synthesizer. The
description of each section ís given in the following.
1-3 lnterface circuit
This circuit connects Vco and prescaler, and serves as an amplifier and a buffer. TR901 is a buffer
for Vco and ECL (Emitter Coupled Logic lC), and TRg02 is a buffer/amplif ier for ECL and TTL.
Vco I nterface Prescaler Programmable frequäncy
d ¡vider
Low-pass
f ilter Phase
comparatof F req uency
d ¡vid er

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PART IT PLL SYNTHESIZER o
1-4 Prescaler
o-{
The local oscillator frequency for rhe FM broadcasring band of 97.6 (88.1) - 107.g MHz is gB.3
(98.8) - 118.6 MHz or 10.7 MHz higher than the broadcast band. To divide this frequency with a
variable divider is difficult for an ordinary TTL lC whose dividing capacity is only 1O - 20 MHz.
Therefore, a high speed scaling circuit or a prescaler is used in this equipment. That is, Vco is
divided by the extra-high speed fixed divider to lower the frequency beforehand. To achieve this
we use extra-high ECL, SVlMC10131P and SVlSN74LS76 lC'stodividerhefrequencyattheratio
of 1/8.
A. 10131P B. 10131P A. 74LS76
f in.
98.3 (98.8)
118.6 MHz
f in (VCO)
(4.10131P Ce1)
A 1013rP 01
(8.10131P Ce2) 1/a
B 10131P 02
{A. 74LS76 CK)
12.2A75 (12.351
14.825 Ml.lz
A. 74LS76 q
Time chart
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Both 10131P and 74L576 are equipped with two stages of FIF cÍrcuit (flip-flop circuit). And the
output is inverted when the clock (CK) input ir "1", that is, when it changes from "1 " ro "o".
ln the time chart, when fin is " 1", the 01 output of A10131p changes from "o" to "1". with
the next fin "]-', it changes from "1" ro "0". Thus, each stage of F/F.circuit divides the
frequency at the ratio of 1/2,that is, 1/B ¡n 3 stages.
2
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tESIZER
1-5 Programmablefrequencydivider
The prograr"nmable frequency (variable) divider plays the most important role in setting the
frequency for the PLL synthesizer.
Thefrequencydividingratio 1ln=1/983(9BB) - llBOnecessaryfortherespectivecountryisdone
in this section. ln the case of this equipment, lC's SVlSN74LS192 and ¡rPDB61 are series-con-
nected, and the results of division by the fixed and variable codes are totalled to achieve the
dividing ratio. "1"
74L574
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fin
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.O -.9 87 (88) - 107 To Phase comparator
Programmable frequency divider circuit
1-5-1 Operational description of lC
SVISN74LS192
4-bit BCD up/down programmable counter.
ln this circuit, it is used as a down counter, and the borrow output is fed into ¡rPDB61C.
When the BCD output changes from 0 to g, a down counter input pulse of negãtive polarity äppears
at the borrow output.
Also, when the load line is ar "1" level, the inputs of tl-ie preset inputs Da - Do are inhibited and
the counter counts down the frequency. But when the load signal becomes "0" level, the preset
data are given priority and set ¡nto each F/F irrespective of the input frequency conditions. When
the load line is again shifted back Io "1" level, the counter counts down from the preset value.
c
o
õ
D
ocK
CLR
B
74L574
oA oB oc oD
74L5192
Load
Db Dc Dd
down
Ða
Borrow
CLR P2 P3 P4 P5 P6 P7 P8
pPD861C
OUTln
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PART TI PLL SYNTH
@ svrsrrrzlLszl
D-type f lipfilop
When the clock (CK) input has changes from "0" Io "1" level, the information at the D input is
transferred to the O output. And when the clear (CLR) input is "0",o becomes "0"'
Õ
lnput (tn) Output (tn+1)
o o t_l
001
1I0
@ svrsN74Ls76
J-K Flip/flop
When the clock (CK) input changes from "1 " To "O", Q and Õ are inverted
@ SVI¡reD861C PLL lC for GB
Table of true values
x2 D2
tn: time before clock pulse changes from "0"
to "1".
tn*1: time after clock pulse has changed from
"0" ro "1".
AI AO
X1 FD
DO
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o
ls
@
t
PI
O
F ilter
amp.
Programmable divider
I bit
lnput mode sêlôct or SW
Cods convertsr
26
R sfersnce
froq uency
osc ¡ llàtor F/F D ¡vider
9 bit
P hase
comparãtor
MP1 P2 P3 P4 P5 P6 P7 P8
4
PO FP GND VDD

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PLL SYNTHESIZER
This PLL lC is designed for CB and has various functions, which include the following components.
(1 ) Programmable frequency divider
Changing the level of terminal @ V to "O" (l- level) causes P1 - PB to be directly connected
to the program terminals of the programmable divider.
Then the programming is performed in accordance with the binary codes and frequency
dividing can be done up to 3 - 255. P1 - P6 are used in this equipment, but P7 and PB are
not used
Also, P6 is fixed at "1", and the codes added to Pl - Pb make the frequency divíding ratio
variab le.
(2) Reference frequency oscillator and its frequency divider.
Connecting a crystal oscillator element to X1 - X2 makes higher precision frequencies
obtainable. ln this case a 12.5 KHz crystaloscillator element is connected, and the frequency
is divided by the divider with a stage of FIF and 9 bits, thus obtaining the reference frequency
as the comparison frequency of the PLL.
(3) Phase comparator
The reference frequency 12.5 KHz obtained in (2) is compared with the 12.5 K{zobtained by
division of the Vco, and the difference in phase between these two, if any, appears at the
output of the phase comparator.
il^ 1-5-2 Frequency division in fixed code presetting
fín
Contents of
74L5192 9-1 9-2 5
Borrow.out of
7 4L5192
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Contents of
lPD861C
Output of
,¡ PD861c
A 74L574 -O
B. 74L574 D
B 74L574 A
o57 56
t( Load signal)
5

I
PART PLL SY ESIZER.
When the input frequency fin enters the down of 74LS192 the counter countsdown from 9,8,7
... 1 to 0.
When the counting proceeds from 0 to 9, the borrow output is delivered. That is, the input
frequency fin is divided at the r:atio of l/10. The borrow output is put into ¡rPD861C where the
frequency is divided as programmed (codes from P'l - P6) and finally negative pulse "1" is Out
out.
87 LSI6ísinvertedbythispulse. SupposethatO ="O"andÕ ="1". Thenthelogical circuitisas
follows:
74L5192 861C
AcD.
tl
¡
A B C. D Eo
o
"1"
B 74LS76
Counter for scan
From the table of true values for OR and AND;when, "1" and "0t' are respectively put in one side
of OB and that of AND, then the output is "1" for OR and "0" for AND irrespective of the input
on the other side. That is, the kind of code put into the scanning counter has nothing to do with
the results in the above circuit. .
Therefore, the code of 741S192 is [1010] [5] that of 861C is [010111] _ t58l .
Next, as 861C is " J ",A74L574 transmits the D input, therefore O - "1" and O= "0". Atthat
time, when the content of 74LSl92 becomes 1 (i.e. OA, OB, OC and OD are respectively 1,0,0,
O.), "0" is added to all the diode OR circuits and, therefore, the D input of 874LS74 becomes "O".
The D input is transmitted to O with the next Iin " --f ".
ln other words, "0" is transmitted to O and the load signal is generated. The generation of load
signal causes the input [1010] of Dn - Do to be preset, therefore the resultat correcting is g - 2+
1*Sinsteadof 9- 2*1*0. Símultaneously,terminal CLRof A74LS74 isclearedwith"O"
added, and corisequently Õ becomes "1". Then, the D input of 874LS74 becomes "1", and O is
"1" with the next fin " -l ", causing the load signal to go out.
ln the above condition, however, 74LSl92 doesn't count and its content "5" remains as it is.
With the next fin " J ",74LS192performs counting:
5+4 *3*2 *1 *0 --9 *8 .-.-:--- That is, 9 - 2*1 -'@*@*@*@*Ø*O*O
+B+B """" Thus, the counting include extra six pulses as shown by encircling the numbers.
To summarize the above description, when ¡tLI-" (this òan be considered asthe load signal from
861C) comes out at the OUT of 861C, it includes 6 pulses more than the ordinary signal.
Accordingly, the number of frequency divisions by the fixed codes is 586 obtained by adding 6
and 10 x 58 = 580 that is the number of frequency divisions by 74LS192 and 861C.
"o" o
"1" -o
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PART II PLL SYNTHESIZER
û1-5-3 Frequency division in variable code presetting
After the 586 frequency division by the fixed codes, " l" is put out at the OUT of 861C
Bl4LS76 is inverted by this pulse. Then O = "1" and O - 'tott
* Frequency divis¡on in variable code presetting
f¡n
o9 -1 O¡ ol 9ry
Contents of
74L5192
Borrow out of
74L5192
Contents of
tPD861 C40
Output of
I PÐ861 C
A 74L574 A
B 74L574 0
B 74L574 Q.
( Load signal)
Tima chart
Now suppose that the received frequgncy is 90.1 MHz, then the content of the scanning counter ¡s
ilQOO] t0101Ol . Therefore, from the tables of true values for OR and AND, codes [1000]- tl l
and [010101] 142) are respect¡vely added to 74LS192 and 861C.
The subsequent operations are basically the same as for the frequency division by fixed codes.
The only difference is that the number preset into 74LS192 with the load signal given is "1" instead
of "5" in fixed code. The counting operations are I - 2*1"*O*e+Q+9*8 """""" lf
includes two extra pulses as shown by the circled numbers.
That is, the number of frequency divisions by the varíable codes in 90.1 MHz is 422 oblained by
adding 2 and 10 x 42 = 420 that is the number of frequency divisions by 74LS192 and 861C.
Therefoie, the frequency dividing ratio in 90.1 MHz is:
586 + 422 = 1008 --*+1 i 1008
9-2 I 1
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7

r
PART,II PLL SYNTHESIZER I
The whole conf iguration is as follows:
422 586 422 586 422
Oof
B 74L576 "1"
"o"
Example:
Let's review the counting operation in the variable codes for 96.3 MHz.
Since the code of 96 MHz is added to 861C and that of 0.3 MHz isto 74LS192,The contents of
the scanning counter are [i100] in 74LS192 and [00001] in 861C. Because Q and Õ of
874LS76 are "1" and "0" respectively, as obtained from the table of true values, t1100,]_13]
and [00001 1 ]- I48l are respectively added to 74LS1 92 and 861 C.
Thecountingoperationsareg-2-"+'l--@-+@*Ø*O*O-9-'8.......Thatis,four
extra pulses as shown by the circled numbers are counted.
Therefore, the number of frequency divisions by the variable codes in 96.3 MHz isr484 obtained
by adding 4 and '10 x 48 = 48O that is the number of frequency divisions by 74LS192and 861C.
Thus, the frequency dividing ratio ín the ease of fixed codes is always 1/586, and the variable
codes vary in accordance with the frequencies. The frequency dividing ratios are shown in the
following table.
1-5-4 Programmable Frequency dividing ratio
fin vco Fixed code Variable code Programm
F. divid-
87.6 MHz 98.3 MHz 586 391 983
88.1 98.8 586 402 988
90.1 100.8 586 422 1 008
96.3 107.0 586 484 1 070
100.0 110.7 586 521 1 107
106.0 116.7 586 581 1167
107.9 118.6 586 600 1 186
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PART IT i, PLL SYNTHESIZER
ü1-5-5 Circuit to prevent faulty operation
B. 74L574
oö
LS192 861 C
Load
B orrow tn
ln the illustration at left, an OR circuit is located
between 74L5192 and 861 C.
The description is given in the following.
When the decimal place is zero such as 88.0, 89.0
. 107.0, the emission of load signal.during
variable code frequency division causes "0" to b€
preset. The counting operation is as follows:
I - 2->1+0-+Q -+g-+g
I lt I
ba
comparison frequency Also, the frequency at
terminal
"o'
cT
0
o
Here, 74LS192 is to produce borrow output as a. However, as "0" is preset, it again produces
borrow output at b thus causing faulty operation. This results in the emergen.ce of a problem that
the received frequency does not match the indicated frequency.
Accordíngly, such defective operation is prevented by putting in Õ = "1" through the OR circuit
when the load signal is given, that is, when O of 874LS74 equals "0", not allowing the borrow
output at b to get into 861c. lncidqntally, c is provided for cutting "noise".
1-6 Crystal frequency divider
Trim mer
Crystal
330 K
The comparison frequency, the reference for the
PLL, is produced in this circuit. When a jZ.B MHz
crystal oscillator with a high accuracy of r20 ppM
is connected between @ and @ of ppDB6lC to
perform frequenc¡r division with one stage of F/F
and a 9-bit dívider:
12.8 MHz 12.8 MHz
=- =1'FVt-l-
21 o 1024 t ''e t\t tL
The frequency output ut @ is the reference
0
IS:
12.8 MHz
--;- = 6.4 MHz
z
I PÞ861C
This can be used to check for defective operation of the oscillator.
lncidentally, 330Ko is the bias resistor, and the trimmer is provided for fine adjustment of the
freq uency.
.f
Standard
oscillator F/F
9-b it
divider
I

i
PART II PLL SYNTHES]ZER t'
1-7 Phase comparator and low-pass filter
V1
Programmable
freq uency
divider output
12.5 KHz + L'f
Reference
compar¡son
frequency
12.5 KHz
+VDD Vcc
cBo5
a4
To VCO
R1
IS GND
Muting signal
(To lF)
(To AF)
1-7-1 Functions of phase detector, charge pump and LPF
ln the above-mentioned circuit, the charge pump by the phase detector and C-MOS is involved in lC
¡rPD861C, while LPF is of discrete.
When the reference comparison frequency is fed into one of the input sides of the phasedetector by
the sequential logíc circuit, and the output of the programmable frequency divider is fed into the
other, the phase or frequency difference between the two frequencies is detected, and its output ¡s
the logic value of "O" or "1" in accordance with the phase "lead" and "lag" or the frequency
differences. The results are shown in the following.
(1) When the programmable frequency divider output Vr is lagging in phase compared wlth the
reference comparison frequency Rr, "1" is theoutput at Dr, and "0" at Ur.
(2) ln the reverse case, "0" is the output at Dr , and "1" 4t Ur .
(3) When both are ¡dentical in phase, the output at Dr and Ur is "1"
(4) The outputs of Dr and Ur will never be "0" 4t any t¡me.
Since the phase detector is able to detect the phase lead and lag but unable to convert the current
into DC power, the charge pump of the C-MOS is used to achieve this. lt is connected to the active
low-pass filter consisting of a darlington amplif ier and a CB network which supplies the DC output
to the VCO.
Suppose the frequency of the VCO is shifted by +Af for some reason, then Vr leads in phase
compared to Rr, causing Dr to become "0". Then, Or, channel P, turns ON to change C'thus
decreasing the output voltage of the active LPF and lowering the VCO frequency. Next, VCO,
shifted by -Af, causes Ur to become "0", therefore Or of channel N turns ON causing the voltage
-t0*
t
I
o6
a7 *
G
chann
Phase detector'
N
chan nel
Ç

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PART II PLL SYNTHESIZER
,{rü of C to be dischar:ged thus incr"easing the output voltage of the LPF and raising the VCO frequency.
As these operations are repeated, the outputs become identical in phase, and both Dr and Ur
become "1". Consequently, Or and Oz turn OFF, causing charge and discharge to stop. These
operations result in a response as illustrated below.
,f,,) 1-7-2 Circuit to prevent shock noise
The lS (lnstant stop) terminal is employed to prevent shock noise during the OFF mode. The level
of this terminal is usually "l" when the PLL is being locked. lt becomes "0" immediately after the
power source turns OFF. (Reference: square wave form with PLL unlocked).
As shown in the afore-mentioned circuit diagram, a diode is connected to lS to discharge the
capacitor at the base of Oz during the OFF mode, thus accellerating the rise of the collector voltage
of Oo.
e1-g VCO (Voltage control oscillator)
sl¿
l/
4.5V 14V VD
_B
VD = 4.5 -approx. 14V
(from LPF output voltage) TO INTERFACE To MIX
Fis. 1Flg.2
This VCO is a Colpitts oscillator circuit in which a variable capacitor (variable capacitance diode)
and an inductance are combined as shown in Fig. 1. The frequency ranges from 98.3 (98.8) MHz
to 118.6 MHz.
lf inverse voltage VD is applied to the variable capacitor, it causesthe capacitor to have capacity C
as the space-charge layer spreads. The relation is in inverse proport¡on as shown in Fig. 2.
Therefore, the frequency is proportional to VD. The MA320G1-N (MEC make) employed for this
circu it varies with in 2 - 12pF , and VD used ranges f rom 4.5V to 1 4V.
Also, the ANT circuit uses two double tuned circuits with variable capacitors, which serves to apply
DC bias VD the same as VCO. This method, however, causes tracking erior problem to arise. So,
five variable capacitors whose variation in capacity at 3, 10, 17 and 25 is less than3% areemployed
for the ANT and OSC circuits.
- ll -
c
;
Buffer

crRcu¡T FoR srART año sro
lN AUTO TUNING, ANP PULSE GENERATION
D ADJACENT CIRCUITS 't
2.
2-1
Circuit fcir start and stop pulse generation during auto tuning, and adjacent cirouits
Station selector step scan
TR1'17
co I lector
+B
tc919
TR 109
+B
Stop
signal
4 5
t,
+B
To sy nthesizer
D108
Ft1 43
Auto mono ,o
P ink
no ise
s3-3
TR113
( M uting)
to "L" level
,o{ þ uo*n t
AT button
2-1-1 Flip-flopcircuit
Start The internal structure of 1C912 (SN74LS00) in
the above circuit is a flip-flop circuit as shown
here.
@
Stop To TR113
(Muting
controlsignal)
This flip-f lop c¡rcuit has such a characteristic that the level of
@changes from "H" I
ptn @
evel and changes from "H" to
@
"L" or l',L" to "H" only when pin @ ot
Now, let us see what occurs when a signal enters pin
t2-
7
1
1
D917 N
o)
o
1c912
SNT4LSOO
D919
D918
@ with the circuit stabilized as shown
t

tt PART II
initial state (pin @ "H", pin Ø "L", pin@
ptn )
@changes from "H" fo "L", causing pins
,,H
a
(9 to go "H" and pin
"'1", @remains "H" and @ remains
"L',:.
d: @ changes from "L" to "H", but @ and.
remaiir as in b and c.
2-1-2 Start pulse generation (differential circuit)
(The above is an example of
start pulse ¡n auto tuning.)
When S3-3 is ín auto or mono, B is +B (þl) via
R942 if the AT buton is not pushed. W¡rh the AT
button pushed, one side of Cg17 is grounded'and
the potential is momentarily reduced to ground
(L). But it is soon charged by the time constant of
R942 (10Ko) and C917 (0.68¡lF), and irs
potential returnes to the +B line. This can be
f igured as fo llows.
lf the AT button is released early or kept depressed
longer will not change the wave form.
AT button pushed
H
L
H
L
H
L
L
H
H
H
ü
a
b
c
64
rogo L
+B
Auto Mono
----o
Pink
noise
s3-3
L
H
L
0
t(,
tc912 o
\f
o)
r
(o
o)
o
o)
(Ð
o)
tr
o)
o)
oTR91 O
Þ920
tc912
5
5down
A uto-tu ning
(AT) button
\
;By
of time constant
C927 x R942
- 13 -
RS flip-flop
\t
o)
tr c\l
\l
o)
tr
t'\
o)
O
+B ,'H,
"L"

i
CIRCUIT FOR STARTSANÞ STOP PULSE GENERATION
ENT CIRCUITS
PART II IN AUTO TUNING AND ADJAC I
2-1-3 Stop pulse generat¡on
When the AT button is not pushed in the circuit ment¡oned in2-1-2, TF910 is biased via R941 and
turned on. With the button pushed, however, the TR910 base is clamped to ground at D920
(O499) and turned off. At that time, the collector potential changes as follows:
Change in potential of TR910 collector
+B
AT button Pushed AT button released
+B ,,H,
It passes through C916 and C915. Also, pin@of
1C912 is connected to +B line at R939, therefore
the wave form as shown below will be generated.
At that time, the pulse level at changes from t
o
11
"H" ro "L". So, pins @ and
by putting the pulse into pin can be inverted
shown in the
TR91O collector
1c912 pin @
o "L"
O"L
+B ,,H,,
aforementioned f lip-f lop cirucuit. (Stop pulse).
The above operations occur in the case of step-
scan. ln auto tuning (standard or fine), however,
the TR910 collector is grounded bV S2-2 and no
pulse is generated. The stop pulse in auto tuning is
generated at TR109.
(A description is given separately.)
\+ t
t
2-1-4 Adjacentcircuits
Description of the muting control.
When the local oscillator is fluctuating during auto tuning or step scan, noise or impulse sounds
would be mixed with the regular signal. Therefore, the output signal is cut off by using the muting
f unction during auto tuning
The control signal prn @ of rcg12 is used for muting. The descriptions given in 2-1-1 , 2-1-2 and
2-1-3 can be summarized and figured as follows: (during step scan)
AT button pushed AT button released
lcel2 pin @
(Start pulse ¡nput pin)
lce12 pin @
(Stop pulse input pin)
rcel2pin@t@l
(Mut¡ng c¡rcuít control signal)
rcel2pin @ t@l
(To clock OSC sect¡on)
H
L
H
L
H
L
H
L
-14-
Q

PART II CIRCUIT FOR STARTiAND STOP PULSE GENERATION tN AUTO TUNING, AND ADJACENT CIRCUfË
pin@of lCgl 2 is connecred to the base of TR1 1 3 through R143//D108
{
o
+B
D1 08
B l43 TR1 14
To 1C912 Output
Lch
R1 43 TR4O2
TR111
TR1,I3 au to mo no
pink
no ¡se s3-3 R 146 TR4O3
Output
Fì ch
The oþeration of each transistor is shown in the following table
rce12 pin@t@l Stop Stop
TR 113 ON OFF ON
rR112 ON OFF ON
TR114 OFF ON OFF
rR402.403 OFF ON OFF
Output signal Present Muted Present
As shown in the above table, T8113 is OFF during tuning. To achieve this, it is required that Vf of
D108, be smaller than Ver of TR113.
Therefore a germanium diode must be used.
(lf a silicone diode is used, TR1'13 may sometimes fail to turn OFF.)
2-2 Operations with station selector at fine and standard
When the AT button is pushed with the selector set at f¡ne or standard position, the station will be
automatically selected. The fine position automatically selects stations stronger than 35 dB/75ç,
(about 55pV). (Stereo distortion factor of 0.2% or better) and the standard position selects those
stations stronger than 20 d7ll\ 0 (about 10¡V). (Stereo distortion factor f rom 02% to 1%).
These automatic tuning levels can be adjusted by VR 101 for f ine and VR 1 02 for standard
TR112 To
auto
button
I
I
I
- t5 -

PART II CIRCUIT FOR START AITÐ STOP PULSE GENERATION
tN AUTO TUNTNG, AND ADJACENT C¡RCUITS
2-2-1 Outline of auto tuning
MPX
The automatic tuning is done by the frequency codes of the programmable counter. When the auto
tuning button ís pushed, the clock pulse oscillator circuit operates and lC 4029C starts counting.
As the desired station is approached, a speed down signal is generated to lower the clock pulse
frequency. ln other words, the scanning speed is reduced. After that, the stop signal is generated at
the exact tuning point to stop the clock oscillation. Thus, the scanning stops and the signal is
received at the exact tuning point. This is the basic principle of auTo tuning. The detailed
description is given in the following.
TR909
R129
1o 4O29C
+ Vcc
t
o
o
ü
2-2-2
r-- Clock
.q4
AT button
TR 109
pulse oscillator circuit and adjacent circuits
-- - - - --r
6+Vcc
tc912 I D918
ITR908 Ð927 .-
/
R935 D91 6
D115
R 156
B 155
off fine
f ine
stand
s2-2
ard
r---
+Vcc
Latch
+Vcc C lock generâto r
c¡rcu¡t
_I
Stop signal TR105
¿J
3.1v z1
Speed down signal
TFì908 base
TFì908 em¡tter
o
3V
oo.6v
Front end l'F Amp.
Programmable counter Sp€ed down Stop
ABCDE ABCDE
Counte r 4O29C etc. Clock
generator
D9t 5
919
c91 3
D930
R938
R937
4,
VV
Wave of clock generator
ló -
o. Time t

PART IT CIRCUIT FOR STAR+SAND STOP PULSE GENERATION
' ¡N AUTO TUNING, AND ADJACENT CIRCUITS
r
,r
The clock pulse oscillator circuit consists of TRSOB and TRgOg, with which a wave form as shown
on the previous page can be obtained.
When the AT button is pushed, if appears at pin @ ot rcul, and pin @ becorn.s "H".
Then, TR90B turns ON. Therefore, the collector becomes equal in potential to the emitter and
TR909 turns ON. The collector of TRg09 is grounded and simil,arly the base potential of TRSOB
decreases. Further, TR90B keeps turning ON and therefore the emitter potential is reduced to a
level Vf (0.6V) higher than the base potential, and then the collector potential drops as well.
Accordingly, TF90B turns OFF and the base potential of TR908 rises to the original level.
But the emitter turns off as its potential does not immediately increase because of the time
constant. The repetition of these operations results in oscillation. During scanning, TRIOb is OFF
and the scanning speed at that time is determined by Cg'13 and (R938 + R156 + R12gl/lìg37.
When TR105 turns ON, D114 and D916 are reversely biased, therefore R156 and R129 are open
and the oscillation time constant is determined by C913 and R937. Accordingly, the oscillating
frequency is lowered causing the scan speed to slow down.
When TR109 turns ON at the exact tuning point, the latch of lCg12 is inverted, and DliB and
D915 are biased in forward direction, and the oscillation stops. The scan speed in step scan is
determinedbythetimeconstantof Cg13andF937. ThisisbecauseRlS6andRl2garegrounded
by S2-2.
2-2-g Extraction of tuning signal
TR1 05 TR106 TFt 109
tc102 Stop signal
D 105
R125 R127
R'l17
VR101
standard
Pin G) voltage Pin @ voltage
tv1
arrrszz @
voltage (DC)
lnput level IdBl o-¿or o +¿or
-300K Af
-4N377 p¡n @ output characterist¡c-
0
',I
;Af
-17-
D1o4
Speed down s¡gnal
F
fr
TRl 04
VR102 s2-1off
+300K
-4N377 pin @ output charactðrist¡c-

PART TT OPERATION OF THE TUNING COUNTER
TR105 collector
fo
Af
lspeed down s¡gnal]
TB109 collector
Af
lstop signall
3. Operation of the tuning counter
3-1 Operationaldescriptionof lG's
When the scan signal approaches, voltage is
generated at pin (9 of 4N377 having a wide-band
characteristic. Then, TR105 turns ON and the
collector becomes ground potential. With TR105
turned ON,TR106 turns OFF,and D'105 is reverse-
biased. At the same time, pin @ of 4N377 be-
comes OV at the exact tuning point as it is the
terminal of the muting signal. Also, the frequency
band is narrow as illustrated at left. Therefore,
TR104 turns OFF and D104 is reverse-biased at
the exact tuning point. Thus, TR109 turns ON,
only when D106 and D104are reverse-biased. This
results in emission of the stop signal.
LJ-
o
ID
o
The description of the operation of lC's is given prior to the actual circuit description. To fully
understand the functions and characteristics of the lC's,it isvery important to learn the contents in
this section.
SVI¡PD4029C Presettable up/down counter
This counter gives the frequency codes to the programmable frequency dividers 74L5192 and
pPD861C which play the major roles of the PLL synthesizer. The counter has two functions as
mentioned below.
It counts the clock pulses at the CK (decimal or hexadecimal input), and its output is the
binary code from O¡ - Oo and the carry from CO.
CK- Clock input terminal
When clock pulses enter this terminal, the counter in the 4029C starts
cou nti ng.
Cl- Carry in
When this terminal is "H", no counting is done even when CK has input.
Counting is done only with this terminal aT. "L".
OA - OD- The number of clock pulses counted by the counter is in binary or B.C.D. code
B/D- Binary/Decade
This terminal is to select the mode (hexadecimal or decimal) of the counter in
4029C.
The counter is decimal al "L" and hexadecimal at "H".
CO- Carry out
On completion of counting up (decimal or hexadecímal) or counting down of
the counter, clock pulses for one cycle are put out to (O).lLf
u/D- up/down
The counter counts down with this terminal at "L", and counts up at "H".
o
-18-
cl
CK
P/Ê.
oD oc oB oA
pPD4029e co
UlD
B/D
B
DC
t