Technologic Systems TS-7680 Quick start guide

Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7680 Documentation
1
B
Sept. 1, 2015
20
Board can be powered by 8-28 VDC or 24VAC
SiLab uC is powered up first, then
- USB Device to Console conversion
SiLab uC does these functions:
- Controls MX286 Sleep mode
- Can read Push Switch for Wake-up
- Controls MX286 power up sequence
- Measures Analog Power Rails
- Controls SuperCap charging
Comments:
UART0 --> BlueTooth or other
RS-232 RJ45 (2)
Modbus RJ45
Screw Term RS-485
UART4
Serial Port Usage
it controls the MX286 start up
All Parts are Industrial Temp
Rev.A --> B Changes
2) Changed NAND to eMMC
3) Changed to SiLab micro
5) Current Loop can be controlled
6) Added SPI Flash for booting
8) Added SuperCap Option
9) Bluetooth now has UART HS
10) Changed FPGA to MACH X02
1) Changed to Vertical battery holder
7) Added accelometer option
4) Changed RTC chip to ST Micro
MAX3100 Daughter Card (TTL)
UART1
UART2
UART3
MUX
- Can trun on Blue LED
11) Added CAN J1939 RC to both ports

ofSheetDesignerRev:
Title:
DateTechnologic Systems
2
TS-7680 SiLab uC and USB Device port
Sept. 1, 2015
B 20
USB Device Port and SiLab uC
USB Device Port
Blue LED
Push Switch
SiLab 4.7V
Program
USB
Scale = 5.57%
Scale = 44.6%
A/D full scale = 2.50V
24 mA max load
I2C
Scale = 50%
Scale = 50%
Analog
PWM
Scale = 50%
USB
Single
4GND
15V
2D-
3D+
5
FRAME
6
FRAME
P2
CONN_USB_B_RA_BLACK
2
3
1
4
TVS4
BGX50A_SOT143
C107
.1 uF
1
2LED6
Blue
1
2
3
4
SW1
SW_PUSH_RT_TH
D
S
G
2
6
1
Q5-A
2
7
RN12-B
1.5K
3
6
RN12-C
1.5K
4
5
RN12-D
1.5K
D
S
G5
3
4
Q5-B
R66
5.1 ohm
FB21
220 ohm
1
2
3
D11
C195
.1 uF
C196
.1 uF
R138
475K
C69
10 uF
SiLabs
A/D
5.25V Max
A/D
TXD
RXD
A/D
A/D
A/D
25
P1.1
10 DEBUG_DATA
30
TXD0_P0.4
15 P2.3
14 P2.4
26
P1.0
13 P2.5
8USB_VBUS
22
P1.4
21
P1.5
23
P1.3
5USB_DM
4USB_DP
12 P2.6
2
P0.0
33
PAD
18 P2.0
20
P1.6
7
PWR_IN
17 P2.1
31
P0.3
16 P2.2
6
REG_3.3V
29
RXD0_P0.5
27
P0.7_VREF
28
P0.6
24
P1.2
9DEBUG_CLK/RESET# 32
P0.2
1
P0.1
19
P1.7
11 P2.7 3
GND
U16
SILAB_C8051F383_QFN32
C223
.1 uF
C60
10 uF
C59
10 uF
R161
25.5K
R118
20.5K
2500 mV
2
3
1
U8
REF_AN431A_SOT23
R140
475
R142
28K
R167
9.1K
R168
9.1K
R169
9.1K
R170
9.1K SiL_3.3V
R116
20.5K
R117
20.5K
1 8
RN11-A
1.5K
5
4
RN20-D
10K
3
6
RN16-C
47K
4 5
RN16-D
47K
1 8
RN12-A
1.5K
USB_SILAB_M
USB_SILAB_P
PUSH_SW#
EN_BLUE_LED
SILAB_3.3V
MX286_BLUE_LED
EN_PWR_RAILS#
SILAB_3.3V
5V_BOOST
CPU_PSWITCH
USB_SILAB_M
USB_SILAB_P
CONSOLE_TXD
VIN
CONSOLE_RXD
SILAB_CLK
SILAB_DATA
SILAB_3.3V
5V_BOOST
I2C_DAT
I2C_CLK
EN_BLUE_LED
CPU_1.8V
CPU_CORE
CPU_3.3V
AUX_3.3V
CPU_RESET#
AN_SCAP_1
AN_SCAP_2
SILAB_PWM
AN_CHRG
RAM_1.8V
AN_VINT
USB_5V_DET
5V_BOOST
USB_5V_DET
SILAB_CLK
EN_TOP_OFF
EN_CHRG#
SILAB_DATA
EN_SILAB_REF
EN_SILAB_REF

Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7680 MX286 CPU
3
LCD
JTAG, I2C
NAND, PWM
MX286 ARM9 CPU
20
Sept. 1, 2015
B
UARTs, ADC
NC on
MX283
SD Card
SPI Boot
NC on
MX283
NC on
MX283
SD0
SD2
LCD_00 thru LCD_04
Control Boot Source
All JTAG have 47K internal PU except RTCK
NC on MX283
and 286
and 286
and 286
Boot
SPI
RESET#
4 CAN signals
and ball D7
MX286 adds
eMMC Interface
EN_SPI_BOOT_FLASH is set low by CPU
after done booting from SPI
Then SPI signals are changed to UART2
SD1
To FPGA
SD3
eMMC
1.8V
Hard strapped for SPI
and UART3 functions
These signals are on the same MX28
pins on both Rev.A and Rev.B
WIFI_IRQ
PUSH_SW#
FPGA_IRQ All MODBUS signals
DC_DIO4 thru DIO6
FPGA_29 LCD_00 thru D06
B14
ADC0_HS
C14
ADC6
D15
ADC5
D13
ADC4
D9
ADC3
C8
ADC2
C9
ADC1
C15
ADC0
J6
AUART0_CTS/DEBUG_RXD
J7
AUART0_RTS/DEBUG_TXD
G5
AUART0_RX
H5
AUART0_TX
K5 AUART1_CTS
J5 AUART1_RTS
L4
AUART1_RX
K4
AUART1_TX
H6 AUART2_CTS
H7 AUART2_RTS
F6 AUART2_RX
F5 AUART2_TX
L6 AUART3_CTS
K6 AUART3_RTS
M5 AUART3_RX
L5 AUART3_TX
U3-A
MX286_CPU_IND
R5
LCD_D23 T5
LCD_D22 U5
LCD_D21 R4
LCD_D20 T4
LCD_D19 U4
LCD_D18 R3
LCD_D17 T3
LCD_D16
U3
LCD_D15 U2
LCD_D14 T2
LCD_D13 T1
LCD_D12 R2
LCD_D11 R1
LCD_D10 P3
LCD_D09 P2
LCD_D08
P1
LCD_D07 N2
LCD_D06 M3
LCD_D05 M2
LCD_D04 L3
LCD_D03 L2
LCD_D02 K3
LCD_D01 K2
LCD_D00
P5
LCD_CS/ENABLE
N1 LCD_DOTCLK
N5 LCD_ENABLE
M1 LCD_HSYNC
P4
LCD_RD_E/VSYNCH
M6
LCD_RESET/VSYNCH
M4
LCD_RS/DOTCLK
L1 LCD_VSYNC
K1
LCD_WR_RWN/HSYNCH
U3-D
MX286_CPU_IND
Boot
SPI
F7
SAIF0_BITCLK/UART4_RXD/PWM5
G6
SAIF0_LRCLK/PWM4
G7
SAIF0_MCLK/PWM3
E7
SAIF0_SDATA0/UART4_TXD/PWM6
E8
SAIF1_SDATA0/PWM7
D7
SPDIF
A4
SSP0_CMD
B4
SSP0_DATA7/SSP2_SCK
D5
SSP0_DATA6/SSP2_CMD
C5
SSP0_DATA5/SSP2_D3
B5
SSP0_DATA4/SSP2_D0
A5
SSP0_DATA3
D6
SSP0_DATA2
C6
SSP0_DATA1
B6
SSP0_DATA0
D10
SSP0_DETECT
A6
SSP0_SCK
C1 SSP1_CMD
E1 SSP1_DATA3
D1 SSP1_DATA0
B1 SSP1_SCK
B3
SSP2_MISO/UART3_RXD
C3
SSP2_MOSI/UART2_TXD
A3
SSP2_SCK/UART2_RXD
D4
SSP2_SS2/SSP2_D2
D3
SSP2_SS1/SSP2_D1
C4
SSP2_SS0/UART3_TXD
B2 SSP3_MISO
C2 SSP3_MOSI
A2 SSP3_SCK
D2 SSP3_SS0
U3-F
MX286_CPU_IND
1 8
RN21-A
10K
3 6
RN18-C
47K
U7
GPMI_D03/SSP1_D3
R8
GPMI_D02/SSP1_D2
T8
GPMI_D01/SSP1_D1
U8
GPMI_D00/SSP1_D0
R6
SSP3_SCK
L8 CAN_RX0
M8 CAN_TX0
N8
GPMI_RDY1/SSP1_CMD
N6
GPMI_RDY0/USB0_ID
L9
SSP3_MOSI
P8
GPMI_WRN/SSP1_SCK
C7
I2C0_SCL
D8
I2C0_SDA
E14
JTAG_RTCK
E11
JTAG_TCK
E12
JTAG_TDI
E13
JTAG_TDO
D12
JTAG_TMS
D14
JTAG_TRST
T6
GPMI_D07
U6
GPMI_D06
R7
GPMI_D05
T7
GPMI_D04
P6
SSP3_CS1#
N7
SSP3_MISO
N9
SSP3_CS0#
M7 CAN_TX1
M9 CAN_RX1
P7
SSP3_CS2#
E10
PWM4
E9
PWM3
K8
PWM2/USB0_ID
L7
PWM1/DEBUG_TXD
K7
PWM0/DEBUG_RXD
U3-C
MX286_CPU_IND
4 5
RN19-D
47K
6
3
RN20-C
10K
LCD_D[00:23]
LCD_D00
LCD_D01
LCD_D02
LCD_D03
UART0_TXD
RXD2_SPI_CLK
TXD2_SPI_MOSI
RXD3_SPI_MISO
CPU_3.3V
SD0_CLK
SD0_CMD
SD0_D0
SD0_D1
SD0_D2
SD0_D3
YEL_LED#
SD2_D0
SD2_CLK
SD2_CMD
SD2_D1
SD2_D2
SD2_D3
UART0_RTS
UART1_TXD
FPGA_27
FPGA_23
FPGA_25
WIFI_IRQ
EN_HOST_USB_5V
EN_MODBUS_3V#
DC_DIO_5
FPGA_29
DC_DIO_6
MODBUS_FAULT
EN_MODBUS_24V
DC_DIO_4
MX286_BLUE_LED
PUSH_SW#
EN_CAN#
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
JP_SD_BOOT#
LCD_D04
LCD_D05
LCD_D06
JTAG_FPGA_TCK
JTAG_FPGA_TDO
JP_UBOOT#
I2C_CLK
I2C_DAT
CONSOLE_TXD
CONSOLE_RXD
EMMC_CMD
EMMC_D0
EMMC_D1
EMMC_D2
EMMC_D3
EMMC_CLK
FPGA_SPI_MOSI
TXD_CAN0
RXD_CAN0_3V
TXD_CAN1
RXD_CAN1_3V
EN_SPI_BOOT_FLASH
AUX_3.3V
FPGA_SPI_CLK
FPGA_SPI_MISO
GREEN_LED#
RED_LED#
FPGA_21
EN_SD_3.3V#
JTAG_FPGA_TDI
JTAG_FPGA_TMS
POWER_FAIL
FPGA_SPI_CS0#
UART4_RXD
FPGA_12MHZ
TXD3_SPI_CS#
FPGA_IRQ
UART1_RXD
FPGA_SPI_CS1#
UART0_RXD
UART0_CTS
UART4_TXD
ACCEL_INT
ACCEL_INT2

ofSheetDesignerRev:
Title:
Date
Technologic Systems
TS-7680 MX286 CPU Power
4
B
Sept. 1, 2015
20
PSWITCH can be driven to 3.3V if a series 10K res is used
Reg VDD1P5 goes to nothing
only feeds two 1.2K resistors
USB
10K PU
to 3.3V
1V
VDD4P2 is an output --
D16
VDD1P5
A13
VDD4P2_DCDC
E17
VDD5V
C13 VDDA1
F12 VDDD7
G12 VDDD6
K12 VDDD4
G11 VDDD3
G10 VDDD2
F11 VDDD1
F10 VDDD0
G13 VDDIO_EMI10
G17 VDDIO_EMI9
G15 VDDIO_EMI8
L13 VDDIO_EMI7
N15 VDDIO_EMI6
N13 VDDIO_EMI5
M12 VDDIO_EMI4
M11 VDDIO_EMI3
R13 VDDIO_EMI2
P11 VDDIO_EMI1
M10 VDDIO_EMI0
J13 VDDIO_EMIQ2
K15 VDDIO_EMIQ1
R15 VDDIO_EMIQ0
F9 VDDIO18_3
G9 VDDIO18_2
G8 VDDIO18_1
F8 VDDIO18_0
A7 VDDIO33_8
E16 VDDIO33_7
J10 VDDIO33_6
J9 VDDIO33_5
N3 VDDIO33_4
J8 VDDIO33_3
H8 VDDIO33_2
G3 VDDIO33_1
E6 VDDIO33_0
N17 VDDIO33_EMI A9
VSS_USB B11
VSSA2_A B13
VSSA1 C16
VSSD6 L11
VSSD5 L10
VSSD4 U1
VSSD3 J12
VSSD2 H12
VSSD1 A1
VSSD0 F14
VSSIO_EMI10 F16
VSSIO_EMI9 H14
VSSIO_EMI8 L12
VSSIO_EMI7 M16
VSSIO_EMI6 P16
VSSIO_EMI5 P14
VSSIO_EMI4 T14
VSSIO_EMI3 U17
VSSIO_EMI2 R12
VSSIO_EMI1 R10
VSSIO_EMI0 J15
VSSIO_EMIQ2 M14
VSSIO_EMIQ1 H16
VSSIO_EMIQ0 H10
VSSIO18_2 H9
VSSIO18_1 H11
VSSIO18_0 B7
VSSIO33_8 E15
VSSIO33_7 K11
VSSIO33_6 K10
VSSIO33_5 N4
VSSIO33_4 K9
VSSIO33_3 J11
VSSIO33_2 H3
VSSIO33_1 E5
VSSIO33_0
U3-G
MX286_CPU_IND
C41
15 pF
C42
15 pF
1.2V
1.8V
3.3V
0 = Boundary
1 = ETM
A15
BATTERY
B15
DCDC_BATT
A17 DCDC_GND
B17 DCDC_LN
A16 DCDC_LP
B16
DCDC_VDDA
D17
DCDC_VDDD
C17
DCDC_VDDIO
B9 DEBUG_JTAG
A11 PSWITCH
A14 RESETN
C10 TESTMODE
A10
USB0DM B10
USB0DP
B8
USB1DM A8
USB1DP
C12 XTAL_VDD
D11
XTALI_RTC
A12
XTALI
C11
XTALO_RTC
B12
XTALO
U3-H
MX286_CPU_IND
L5 15 uH
C165
.1 uF
C63
10 uF
C153
.1 uF
C154
.1 uF
C68
10 uF
C152
.1 uF
C151
.1 uF
C150
.1 uF
C149
.1 uF
C148
.1 uF
C147
.1 uF
C146
.1 uF
C145
.1 uF
C144
.1 uF
C143
.1 uF
C142
.1 uF
C141
.1 uF
C140
.1 uF
C139
.1 uF
C138
.1 uF
C137
.1 uF
C136
.1 uF
C135
.1 uF
C134
.1 uF
C133
.1 uF
C132
.1 uF
C131
.1 uF
C130
.1 uF
C129
.1 uF
C128
.1 uF
C125
.1 uF
C123
.1 uF
C119
.1 uF
C118
.1 uF
C117
.1 uF
C115
.1 uF
C114
.1 uF
C61
10 uF C157 .1 uF
C62
10 uF
C156
.1 uF
C65
10 uF
C155
.1 uF
R87
0.10 ohms
CORE
CP-1.8
CP-3.3
C54
22 uF
25V
R86
0.10 ohms
C55
22 uF
25V
C56
22 uF
25V
C57
22 uF
25V
C58
22 uF
25V
C185
.1 uF
D21
Y1
24 MHz
C186
.1 uF
C161
.1 uF
2 7
RN10-B
1.5K
1
8
RN18-A
47K
4 5
RN18-D
47K 2
7
RN18-B
47K
FB10
220 ohm
8
1
RN4-A
3.3K
CPU_1.8V
CPU_3.3V
CPU_CORE
CPU_3.3V
CPU_1.8V
CPU_CORE
USB_HOST_P
USB_HOST_M
USB_OTG_M
USB_OTG_P
VDD_4P2
VDD_4P2
CPU_RESET#
CPU_3.3V
CPU_1.8V
CPU_PSWITCH
SW_5V

ofSheetDesignerRev:
Title:
Date
Technologic Systems
TS-7680 DDR2 RAM
5
DDR2 SDRAM
MX286
64M x 16
128 MB
(128 or 256 MByte)
Length of this trace is
equal to [CLK + Data] lengths
20B
Sept. 1, 2015
NC
NC
256 MB
128M x 16
OR
Data = Average length of all data traces
C176
.1 uF C175 .1 uF C174 .1 uF C173 .1 uF C172 .1 uF C171 .1 uF C170 .1 uF
M8 A0
M3 A1
M7 A2
N2 A3
N8 A4
N3 A5
N7 A6
P2 A7
P8 A8
P3 A9
M2 A10
P7 A11
R2 A12
R8 A13
L2 BA0
L3 BA1
L1 BA2
J8 CK
K8 CK#
K2 CKE
L8 CS#
F3 LDM
B3 UDM
K7 RAS#
L7 CAS#
K3 WE#
A1
VDD0
E1
VDD1
J9
VDD2
M9
VDD3
R1
VDD4
J1
VDDL
J2 VREF
R3 A14
R7 A15
A2
NC0
K9 ODT
F1
DQ6 G2
DQ1 H7
DQ2 G8
DQ0 H1
DQ4 H9
DQ5 H3
DQ3 F9
DQ7 D1
DQ12 C2
DQ9 D7
DQ10 D3
DQ11 C8
DQ8 D9
DQ13 B9
DQ15 B1
DQ14
F7
LDQS E8
LDQS#
B7
UDQS A8
UDQS#
A9
VDDQ0 C1
VDDQ1 C3
VDDQ2 C7
VDDQ3 C9
VDDQ4 E9
VDDQ5 G1
VDDQ6 G3
VDDQ7 G7
VDDQ8 G9
VDDQ9
H8 VSSQ9 H2 VSSQ8
F8 VSSQ7 F2 VSSQ6
E7 VSSQ5
D8 VSSQ4 D2 VSSQ3
B8 VSSQ2 B2 VSSQ1 A7 VSSQ0
J7 VSSDL
P9 VSS4
N1 VSS3
J3 VSS2
E3 VSS1
A3 VSS0
E2
NC1
U19
DDR2_128MB_X16_ITEMP
C160
.1 uF
R51
7.87K
R52
7.87K
N10
EMI_A14 T9
EMI_A13 U11
EMI_A12 T10
EMI_A11 U13
EMI_A10 P10
EMI_A09 U9
EMI_A08 N11
EMI_A07 R9
EMI_A06 R11
EMI_A05 U10
EMI_A04 T11
EMI_A03 U14
EMI_A02 U12
EMI_A01 U15
EMI_A00
N12
EMI_BA2 T12
EMI_BA1 T16
EMI_BA0
U16
EMI_CASN
P12
EMI_CE0N
P9
EMI_CE1N
T13
EMI_CKE
L17
EMI_CLK
L16
EMI_CLKN
F17 EMI_D15
F13 EMI_D14
H17 EMI_D13
H13 EMI_D12
J14 EMI_D11
G14 EMI_D10
H15 EMI_D09
G16 EMI_D08
M17 EMI_D07
L14 EMI_D06
P17 EMI_D05
P13 EMI_D04
N14 EMI_D03
P15 EMI_D02
M13 EMI_D01
N16 EMI_D00
L15 EMI_DDR_OPEN_FB
K14 EMI_DDR_OPEN
F15 EMI_DQM1
M15 EMI_DQM0
K16 EMI_DQS0N
J16 EMI_DQS1N
J17 EMI_DQS1
K17 EMI_DQS0
T17 EMI_ODT1
R17 EMI_ODT0
R16
EMI_RASN
K13
EMI_VREF1
R14
EMI_VREF0
T15
EMI_WEN
U3-B
MX286_CPU_IND
C158
.1 uF
C177
.1 uF C178 .1 uF
C103
.1 uF C106 .1 uF
C104
.1 uF
R54
7.87K
R53
7.87K
RAM_1.8V
RAM_A[00:15]
RAM_A00
RAM_A01
RAM_A02
RAM_A03
RAM_A04
RAM_A05
RAM_A06
RAM_A07
RAM_A08
RAM_A09
RAM_A10
RAM_A11
RAM_A12
RAM_A13
RAM_BA0
RAM_BA1
RAM_BA2
RAM_CLK_P
RAM_CLK_M
RAM_CKE
RAM_CS#
RAM_DQM0
RAM_DQM1
RAM_RAS#
RAM_CAS#
RAM_WE#
RAM_1.8V
RAM_DQS0_P
RAM_DQS1_P
RAM_1.8V
RAM_ODT
RAM_D[00:15]
RAM_A14
CPU_1.8V
RAM_DQS0_M
RAM_DQS1_M
RAM_D07
RAM_D03
RAM_D06
RAM_D11
RAM_D14
RAM_D15
RAM_A00
RAM_A01
RAM_A02
RAM_A03
RAM_A04
RAM_A05
RAM_A06
RAM_A07
RAM_A08
RAM_A09
RAM_A10
RAM_A11
RAM_A12
RAM_A13
RAM_A14
RAM_D14
RAM_D15
RAM_BA2
RAM_BA1
RAM_BA0
RAM_CAS#
RAM_RAS#
RAM_WE#
RAM_CKE
RAM_CLK_P
RAM_CLK_M
RAM_ODT
RAM_DQM1
RAM_DQM0
RAM_DQS1_P
RAM_DQS0_P
RAM_DQS1_M
RAM_DQS0_M
RAM_CS#
RAM_D00
RAM_D01
RAM_D02
RAM_D03
RAM_D04
RAM_D05
RAM_D06
RAM_D07
RAM_D08
RAM_D09
RAM_D10
RAM_D11
RAM_D12
RAM_D13 RAM_D00
RAM_D02
RAM_D01
RAM_D05
RAM_D04
RAM_D13
RAM_D08
RAM_D12
RAM_D10
RAM_D09
RAM_1.8V

Technologic Systems Date
Title:
Rev: Designer Sheet of
5V Power Supply (2000 mA)
C81 must be very near U17
Power Input
8-28 VDC or AC
.063 hole
6
TS-7680 5V and Switched Power
Sept. 1, 2015
B 20
Switched Power
Rise time of both outputs
measured at ~ 1V/ms
USB and Daughter
1.225V
Scale = 44.6%
FB26 not pop if
SCap used
Switched 5V Power
C98
10 uF
50V
VIN
C80
.1 uF
C81
.1 uF
TVS18
43V
FB12
220 ohm
1
2
3
CN5
CONN_OSTOQ037501_BLACK
GND
C95
1 uF
FB16
220 ohm
6VDD
3EN_FET1
2EN_FET2
7GND
4
DRAIN_1
5
SOURCE_1
8
SOURCE_2
1
DRAIN_2
U22
SLG_DUAL_FET_SW_SMT8
C168
SW_5V
1 8
RN17-A
47K
2 7
RN17-B
47K
-
+
3
4
1
2
FW1
RECT_FW1A_DF10S_1000V
C99
470 uF
63V
FB15
220 ohm
3VIN
4VIN
1VCC
2SHUTDN#
11 SS
8RT
5SYNCH
9RAMP
17
SW
18
SW
19
PRE
15
IS
16
IS
12
OUT
7
FB
6
COMP
20
BOOST
14
PGND
13
PGND
10 AGND 21
PAD
U17
LM5005_SMT20
C49
22 nF
C48
22 nF
C44
330 pF
C43
330 pF
R115
20.5K
R78
41.2K
R146
1.58K
D3
C46
22 nF
C47
22 nF
R69
4.99K
C51
22 uF
25V
C52
22 uF
25V
C53
22 uF
25V
L7
33 uH
R64
5.1 ohm
R65
5.1 ohm 5V
FB20
220 ohm
R162
25.5K
R119
20.5K
FB26
220 ohm
6VDD
3EN_FET1
2EN_FET2
7GND
4
DRAIN_1
5
SOURCE_1
8
SOURCE_2
1
DRAIN_2
U11
SLG_DUAL_FET_SW_SMT8
1 8
RN16-A
47K
2 7
RN16-B
47K
D
S
G
2
6
1
Q45-A
D
S
G
5
3
4
Q45-B
V_INT
VIN
HOST_USB_5V
DC_5V
5V_BOOST
EN_DC_5V
EN_HOST_USB_5V
AN_VINT
5V_BOOST
5V_BOOST
SILAB_3.3V
SW_5V
EN_PWR_RAILS#

Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7680 AUX Power Reg, Boot Strap
20B
Sept. 1, 2015
7
Boot
3.3V
ETM off
TEST off
Boot Strap
Bias Res.
Source
LCD_3 LCD_0
0 0 1 0
1 0 0 1
SPI
SD Card
0 0 0 0 USB
Aux. 3.3V Reg
RC = 4 x e-6
Strapped
SPI Boot
0 1 0 0 NAND
RAM 1.8V Reg
RC = 4 x e-6
3.31V typ
1.81V typ
Select Boot
Daughter Card
Interface
0.4V = L
1.5V = H
600 mV
3VIN
1
GND
2EN
4
SW
5
GND
6
FB
7
PAD
U6
REG_1A_RT8016_DFN6
L2 3.3V
C64
10 uF
FB13
220 ohm
R172
9.1K
R82
41.2K C31
100 pF
12
3D6
DIODE_BAV99-2_SOT23
C66
10 uF
4 5
RN27-D
10K
3 6
RN27-C
10K
2 7
RN27-B
10K
1 8
RN27-A
10K
1 8
RN23-A
10K
2 7
RN23-B
10K
3 6
RN23-C
10K
4 5
RN23-D
10K
0.4V = L
1.5V = H
600 mV
3VIN
1
GND
2EN
4
SW
5
GND
6
FB
7
PAD
U5
REG_1A_RT8016_DFN6
L1 1.8V
C71
10 uF
FB25
220 ohm
R81
41.2K C30
100 pF C72
10 uF
R114
20.5K
2
7
RN21-B
10K
3
6
RN21-C
10K
14
12
10
8
6
4
2
11
USB-
9
7
5
GND
3
GND
1
13
USB+
16 5V 15
5V
HD1
HD_2X8_DC_2.54MM_TH
FB11
220 ohm
2 7
RN7-B
3.3K
R171
9.1K
LCD_D[00:23]
AUX_3.3V YEL_LED#
AUX_3.3V
CPU_3.3V
SW_5V
LCD_D01
RAM_1.8V
SW_5V
LCD_D00
LCD_D03
LCD_D02
LCD_D04
LCD_D05
LCD_D06
EN_1.8V_RAIL
EN_1.8V_RAIL
DC_RXD_5V
DC_DIO_6
DC_5V
DC_TXD_3V
POE_TX
POE_45
POE_RX
POE_78
USB_OTG_P
USB_OTG_M
DC_DIO_4
DC_DIO_5
VIN
AUX_3.3V

Technologic Systems Date
Title:
Rev: Designer Sheet of
8
TS-7680 Ethernet Switch
Sept. 1, 2015
B 20
Auto MDIX is supported
Polarity Correction also supported
1.2V
10/100 Ethernet 4-Port Switch
Strapped for
RMII MAC mode
with 3.3V Levels
MDI address A4 defaults to "1"
Port 1 LEDs
Port 0 LED
All Port 6 pins
have PU or PD bias
Requires Reset# asserted
for 10 ms after power
MX283
"0111" = RMII MAC mode
NC on
MX283
1.2V Regulator
R120
51 R121 51 R122 51 R123 51
C206
.1 uF
8 MHz max.
PHY 1
PHY 0
Input
and OD Output
Weak PU
40 MDIO
39 MDC
58
ROW_0_LED/SMI_ADD4
59
ROW_1_LED/NO_CPU
60
ROW_2_LED
61
COL_0_LED
63
COL_1_LED
64
COL_2_LED
1
COL_3_LED
5AVDD_PLL
50 P5_OUT_EN/PWR2.5V
53 P5_IN_D2/GPIO2
52 P5_IN_D3/GPIO3
44 P5_OUT_D3/MODE3
45 P5_OUT_D2/MODE2
46 P5_OUT_D1/MODE1
47 P5_OUT_D0/MODE0
49 P5_OUT_CLK
51 P5_IN_CLK
54 P5_IN_D1
55 P5_IN_D0
56 P5_IN_DV
34 VDD18_OUT
35 VDD18_IN
33 VDD_33
48 P5_VDDO
2VDD_CORE_0
17
P6_COL/GPIO5
57 VDD_CORE_2
41
INT#
43 P5_CRS/GPIO0
42 P5_COL/GPIO1/FIBER
62 EE_VDDO
36 VDD_CORE_IN_OUT
37 RESET#
38
VSS
30
P6_IN_D0
4XTAL_OUT
3XTAL_IN
7
P0_RX_P
8
P0_RX_M
10
P0_TX_P
11
P0_TX_M
16
P1_RX_P
15
P1_RX_M
13
P1_TX_P
12
P1_TX_M
18
P6_CRS/GPIO4
19
P6_OUT_D3/MODE3
21
P6_OUT_D1/MODE1
22
P6_OUT_D0/MODE0
27
P6_IN_D3/GPIO7
26
P6_IN_CLK
24
P6_OUT_CLK
23 P6_VDDO
28
P6_IN_D2/GPIO6
29
P6_IN_D1
31
P6_IN_DV
32 VDD_CORE_1
6
I_REF
9P0_AVDD
14 P1_AVDD
20
P6_OUT_D2/MODE2
25
P6_OUT_EN/PWR2.5V
65
GND_PAD
U20
88E6020_QFN64_IND
R68
4.99K
C202
.1 uF
C201
.1 uF
C200
.1 uF
C199
.1 uF
C209
.1 uF
C208
.1 uF
C207
.1 uF
C205
.1 uF
C204
.1 uF
C203
.1 uF
R126
51 R127 51
C198
.1 uF
R124
51 R125 51
C197
.1 uF
C194
.1 uF
C193
.1 uF
1 8
RN6-A
3.3K
2 7
RN6-B
3.3K
3 6
RN6-C
3.3K
4 5
RN6-D
3.3K
1
8
RN5-A
3.3K
2
7
RN5-B
3.3K
3
6
RN5-C
3.3K
4
5
RN5-D
3.3K
E2
ENET_CLK
J4 ENET0_COL
J3 ENET0_CRS
G4
ENET0_MDC
H4
ENET0_MDIO
F3 ENET0_RX_CLK
E4
ENET0_RX_EN
J2 ENET0_RXD3
J1 ENET0_RXD2
H2
ENET0_RXD1
H1
ENET0_RXD0
E3 ENET0_TX_CLK
F4
ENET0_TX_EN
G2 ENET0_TXD3
G1 ENET0_TXD2
F2
ENET0_TXD1
F1
ENET0_TXD0
U3-E
MX286_CPU_IND
1 8
RN14-A
1.5K
2 7
RN14-B
1.5K
1.0V = H
0.3V = L
Low = LP 3% LP
1.5-6.0V 1.20V
2% FT
1VIN
3EN
5
VOUT
2
GND
4ECO
U24
REG_NCP585D_1.2V_SOT23
C70
10 uF
AUX_3.3V
RAM_1.8V
RXD0
RXD1
RXD2
RXD3 MDIO
MDC
PORT1_ACT_LED
PORT0_ACT_LED
PORT1_RX_P
PORT1_RX_M
PORT1_TX_P
PORT1_TX_M
ETH_RESET#
PORT0_RX_P
PORT0_RX_M
PORT0_TX_P
PORT0_TX_M
RXD0
RXD1
RXD2
RXD3
ENET_CLK
RX_DV
TXD0
TXD1
TX_EN
PORT1_TX_P
PORT1_TX_M
PORT1_RX_P
PORT1_RX_M
PORT1_SPEED_LED
MDIO
MDC
RXD0
RXD1
RX_DV
TXD0
TXD1
TX_EN
ENET_CLK
1.2V
AUX_3.3V
AUX_3.3V
LED_ROW_0
PORT0_SPEED_LED
25MHZ_1.8V
RAM_1.8V 1.2V

Technologic Systems Date
Title:
Rev: Designer Sheet of
9
TS-7680 MagJacks
Sept. 1, 2015
B 20
Green
Yellow
Port # 1
10/100 MagJack
Green
Yellow
Port # 0
10/100 MagJack
4RX+
5RX-
6RX_CT
3TX_CT
1TX+
2TX-
7
POE_RX
9
POE_45
11 LLED+
12 LLED-
13 RLED+
14 RLED-
17
ALIGN
18
ALIGN
15
SHD
16
SHD
8
POE_TX
10
POE_78
T2
MAGJACK_POE_10_100
C163
.1 uF
R44
140
R46
140
4RX+
5RX-
6RX_CT
3TX_CT
1TX+
2TX-
7
POE_RX
9
POE_45
11 LLED+
12 LLED-
13 RLED+
14 RLED-
17
ALIGN
18
ALIGN
15
SHD
16
SHD
8
POE_TX
10
POE_78
T1
MAGJACK_POE_10_100
C101
.1 uF
R41
140
R40
140
RAM_1.8V
PORT1_TX_P
PORT1_TX_M
PORT1_RX_P
PORT1_RX_M
PORT1_SPEED_LED
PORT1_ACT_LED
RAM_1.8V
PORT0_RX_P
PORT0_RX_M
PORT0_TX_P
PORT0_TX_M
PORT0_SPEED_LED
PORT0_ACT_LED
LED_ROW_0 LED_ROW_0
POE_78
POE_45
POE_TX
POE_RX

ofSheetDesignerRev:
Title:
Date
Technologic Systems
10
TS-7680 NAND and SD Card
Micro SD Card Socket
Sept. 1, 2015
B 20
Flash Memory
eMMC 4GB
Edge Conn.
SPI Boot Flash
C122
7DATA_0
8DATA_1
1DATA_2
2DATA_3
5CLK
3COMMAND
4
VDD
6
GND
10
FRM2
9
FRM1
11
FRM3
12
FRM4
CN3
CONN_MICRO_SD
1 8
RN28-A
10K
2
7
RN28-B
10K
4
5
RN21-D
10K
1
MT7
MT125 1
MT8
MT125 1
MT9
MT125
G
S D
1
2 3
Q29
C102
.1 uF C105 .1 uF C108 .1 uF
C110
.1 uF C111 .1 uF
C112
.1 uF
C94
1 uF
1
8
RN30-A
10K
2
7
RN30-B
10K
3
6
RN30-C
10K
4
5
RN30-D
10K
R173
9.1K
A3 DATA_0
A4 DATA_1
A5 DATA_2
B2 DATA_3
M6 CLK
M5 COMMAND
E6
VCC
P6
GND
P4
GND
N5
GND
N2
GND
K8
GND
H10
GND
E7
GND
C4
GND
F5
VCC J10
VCC K9
VCC
C6
VCCQ
P3
VCCQ
N4
VCCQ
P5
VCCQ
B3 DATA_4
B4 DATA_5
B5 DATA_6
B6 DATA_7
K5 RESET#
C2 VDD_I
G5
GND
M4
VCCQ
A6 TOSH_GND
J5 TOSH_GND
U21
EMMC_MICRON_4GB_BG153_ITEMP
Edge
Conn.
A11 JTAG_PWR
B11 GND
A10 CONSOLE_TXD
A9 JTAG_TDO
A8 JTAG_TDI
A7 JTAG_TMS
A6 JTAG_TCK
A5 SPI_CPU_CS#
A4 SPI_MISO
A3 SPI_MOSI
A2 SPI_CLK
A1 GND
B1 SPI_PWR
B2 BOOT_SELECT
B3 SPI_DATA3
B4 SPI_DATA2
B5 SPI_FLASH_CS#
B6 OPTION
B7 UC_DATA
B8 UC_CLK
B9 RESET#
B10 CONSOLE_RXD
CN99
CON22_EDGE_PCIE
1CS#
5DIN_DQ0
6CLK 8
VCC
4
GND
7HOLD# _DQ3
3WP# _DQ2
2DOUT_DQ1
U13
FLASH_N25Q064_8MB_SOIC
C180
.1 uF
SD0_CMD
SD0_D3
SD0_CMD
SD0_CLK
SD0_D0
SD0_D1
SD0_D2
AUX_3.3V
EN_SD_3.3V#
AUX_3.3V
EMMC_CLK
EMMC_CMD
EMMC_D3
EMMC_D2
EMMC_D1
EMMC_D0
AUX_3.3V
AUX_3.3V
AUX_3.3V
RXD2_SPI_CLK
TXD2_SPI_MOSI
RXD3_SPI_MISO
EN_7690_SPI_FLASH#
JTAG_FPGA_TMS
JTAG_FPGA_TDI
JTAG_FPGA_TDO
SILAB_CLK
SILAB_DATA
JTAG_FPGA_TCK
SPI_OFF_BD_SEL#
AUX_3.3V
RXD2_SPI_CLK
TXD2_SPI_MOSI
RXD3_SPI_MISO
AUX_3.3V
SPI_ON_BD_CS#
SPI_OFF_BD_CS#

Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7680 RTC and Host USB
11B
Sept. 1, 2015
20
RTC and Host USB
SMT RA LEDs
External Host USB Port
ST Micro RTC
Boot Jumpers
2
7
RN4-B
3.3K
3
6
RN4-C
3.3K
R63
649
D20
R34
30
R45
140
R42
140 R43 140
1
2LED2
Yellow
1
2LED3
Green 1
2LED4
Red
PF1
PTC_1100MA_1812
C109
.1 uF
2
3
1
4
TVS3
BGX50A_SOT143
Vertical
Single
USB
4GND
15V
2D-
3D+
5
FRAME1
6
FRAME2
8
FRAME4
7
FRAME3
CN1
CONN_USB_A_RA_VERT_SINGLE
FB14
220 ohm
FB17
220 ohm
21
3 4
K1
6SCL
5SDA
1XIN
2XOUT
8
VCC
7OUT 3
BAT
4
GND
U15
M41T00S_RTC_SOIC8
12 pF
1 4
2 3
Y3
XTAL_32KHZ_SMT
C224
.1 uF
C225
.1 uF
2
7
RN19-B
47K
3
6
RN19-C
47K
AUX_3.3V
AUX_3.3V
GREEN_LED#
RED_LED#
YEL_LED#
HOST_USB_5V
SW_5V
USB_HOST_M
USB_HOST_P
I2C_CLK
I2C_DAT
AUX_3.3V
JP_SD_BOOT#
JP_UBOOT#
AUX_3.3V

ofSheetDesignerRev:
Title:
DateTechnologic Systems
12
TS-7680 RS-232 Ports
Sept. 1, 2015
B 20
RS-232 Ports and Daughter Card Headers
RS-232 Transceiver
Level shifter
3.3V < -- 5V
RS-232/CAN
STC RS-485 Driver
Dig. Input
Do not use
J1939 Shield
Option
19 OE
1DIR
2A1
3A2
4A3
5A4
18
B1
17
B2
16
B3
15
B4
6A5
7A6
8A7
9A8
14
B5
13
B6
12
B7
11
B8
20
VCC
10
GND
U27
74LVC245_TSSOP20
(CAN_H)
(CAN_L)
(CAN_GND)
8RTS
7CTS
6TXD
5RXD
4GND
2DCD
3DTR
1DSR/RI
9
SHLD
10
SHLD
J4
RJ45_RA_SHIELD_PJ031_EIA561_CAN
C162
.1 uF
4TXD
1RXD
3TXEN
2RXEN#
8
VCC
6
X+
7
X-
5
GND
U29
SP485EEN_SOIC8
R22
60.4
R23
60.4
4 5
RN29-D
10K
T1
T2
R1
R2
C1+
C1-
C2+
C2-
GND
Vcc
V+
V-
1
2
3
4
5
6
7
89
10
11
12 13
14
15
16
U14
SP202_SOIC16
C159
.1 uF
C126
.1 uF
C121
.1 uF
C116
.1 uF
C120
.1 uF
2
7
RN29-B
10K
3
6
RN29-C
10K
12
3D7
DIODE_BAV99-2_SOT23
1
8
RN24-A
10K
2 7
RN24-B
10K
36 RN24-C
10K
4
5
RN24-D
10K
1
8
RN29-A
10K
R70
1 ohm
C37
0.68 uF
R128
51
AUX_3.3V
RXD_CAN1_5V
RXD2_485_5V
DC_RXD_5V
RXD_CAN0_5V
RXD_CAN1_3V
RXD_CAN0_3V
CAN1_H
CAN1_L
TXEN3_485
SW_5V
RXD3_485_5V
485_PLUS
485_MINUS
RXD3_485_5V
SW_5V
SW_5V
SW_5V
DIG_IN
DIG_IN_5VDIG_IN_3V
DIG_IN_5V
COM2_RXD_232_3V
DC_RXD_3V
RXD2_485_3V
RXD3_485_3V
COM1_RXD_232_3V
COM1_TXD_232_3V
COM2_TXD_232_3V
TXD3_485
Remove for
J1939 Shield
Option

ofSheetDesignerRev:
Title:
Date
Technologic Systems
Mod Bus RS-485 and CAN Ports
RS-485 Driver
RJ45
Modbus
13
TS-7680 Modbus and CAN
Sept. 1, 2015
B 20
Power Switch
Modbus
CAN_0 Tranceiver
24V
CAN_1 Tranceiver
24V TJA1040 allows low
power 15 uA mode
C167
.1 uF
4TXD
1RXD
3TXEN
2RXEN#
8
VCC
6
X+
7
X-
5
GND
U28
SP485EEN_SOIC8
R27
60.4
R26
60.4 RS-485
8GND
712V-24V
612V-24V
5DATA-
4DATA+
2GND
3MODE
1GND
9
SHLD
10
SHLD
J6
RJ45_RA_SHIELD_PJ031
R61
649
R62
649
FB24
220 ohm
FB22
220 ohm
FB19
220 ohm
FB18
220 ohm
TVS9
30V
R21
60.4
R28
60.4
2
1
3
Q16
2
1
3
Q14
D12
PF3
1500 mA
3
6
RN13-C
1.5K
4
5
RN13-D
1.5K
D
S
G
2
6
1
Q3-A
3
6
RN17-C
47K
1 8
RN13-A
1.5K
2 7
RN13-B
1.5K
4RXD
1TXD
5VREF
8EN# 3
VCC
7
CANH
6
CANL
2
GND
U25
TJA1040_SOIC8
C164
.1 uF
21
3
TVS15
NUP2105L_SOT23
C127
.1 uF
R20
60.4
R19
60.4
3
6
RN11-C
1.5K
4
5
RN11-D
1.5K
4RXD
1TXD
5VREF
8EN# 3
VCC
7
CANH
6
CANL
2
GND
U26
TJA1040_SOIC8
C166
.1 uF
21
3
TVS16
NUP2105L_SOT23
C124
.1 uF
R25
60.4
R24
60.4
4 5
RN28-D
10K
3
2
1
4
Q9
2
1
3Q10
2
1
3
Q12
R67
4.99K
R103
100K
R104
100K
15V
1 2
3D54
ZENER_15V_SOT23
15V
1 2
3D53
ZENER_15V_SOT23
3
6
RN14-C
1.5K
4
5
RN14-D
1.5K
SW_5V
MODBUS_24V
RXD2_485_5V
VIN
MODBUS_24V
AUX_3.3V
MODBUS_FAULT
EN_MODBUS_3V#
EN_MODBUS_24V
SW_5V
RXD_CAN0_5V
TXD_CAN0
SW_5V
RXD_CAN1_5V
CAN1_H
CAN1_L
TXD_CAN1
TXEN2_485
EN_CAN#
EN_CAN#
AN5_CAN_H
AN4_CAN_L
TXD2_485

ofSheetDesignerRev:
Title:
DateTechnologic Systems
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VBAT must power up first
1.8V Levels
WiFi Radio
(Optional Feature)
Silicon
14
TS-7680 WIFI and DIO
Sept. 1, 2015
B 20
14V Supply
DAC
DIO_2
Sinks 500 mA
Max. Input = 30V
DIO_0
Sinks 500 mA
Max. Input = 30V
DIO_1
Sinks 500 mA
Max. Input = 30V
NC
1
VBAT
2BT_FUNC5
3WL_UART_DBG
4WLAN_IRQ
5BT_EN
6FM_EN
7WL_RS232_RX
8WL_RS232_TX
9FM_I2S_FSYNC
10 WL_EN
11
VIO
12
GND1
13
SDIO_D3
14
SDIO_D2
15
SDIO_D1
16
SDIO_D0
17
SDIO_CMD
18
SDIO_CLK
19 SLOW_CLK
20 FM_IRQ
21 FM_SDA
22 FM_SCL
23 FM_I2S_CLK
24 FM_I2S_DI
25 FM_I2S_DO
26 FM_AUD_RIN
27 FM_AUD_LIN
28 FMRFOUT
29 FMRFIN
30
GND2
31 FM_AUD_ROUT
32 FM_AUD_LOUT
33
AUD_FSYNC
34 HCI_RX
35 HCI_RTS
36 HCI_TX
37
AUD_CLK
38
AUD_OUT
39 HCI_CTS
40
AUD_IN
41 BT_FUNC2
42 BT_FUNC4
43
VDD_LDO_CLASS_1P5
44
GND3
45
GND4
46
GND5
47
GND6
48
ANT
49
GND7
50
GND8
51
GND9
52
GND10
53
GND11
54
GND12
55
GND13
56
GND14
K5
WIFI_MODULE_LSR
C219
.1 uF
C220
.1 uF
L6
COIL_2.7NH_0402
D9
3
2
1
4
Q8
15V
1 2
3
D52
ZENER_15V_SOT23
C77
.1 uF
G
S
DQ22 TVS8
30V
D19
40V
1
8
RN9-A
1.5K
2
7
RN9-B
1.5K
G
S
DQ21 TVS6
30V
D13
40V
1
8
RN20-A
10K
2
7
RN20-B
10K
G
S
DQ20 TVS7
30V
D18
40V
R97
Zero
R95
Zero
R99
Zero
5
4
RN10-D
1.5K
3 6
RN28-C
10K
2
7
RN8-B
3.3K
3
6
RN8-C
3.3K
4
5
RN8-D
3.3K
RAM_1.8V
SD2_D0
SD2_D1
SD2_D2
SD2_D3
SD2_CMD
SD2_CLK
WIFI_IRQ
SW_5V VIN
14V
DIO_2
AUX_3.3V
DIO_2_IN
DIO_0
AUX_3.3V
DIO_0_IN
DIO_1
AUX_3.3V
DIO_1_IN
WL_EN
EN_LS_OUT_0
EN_LS_OUT_1 EN_LS_OUT_2
SD2_CMDRAM_1.8V
BT_CTS
BT_EN
BT_RTS
BT_RXD
BT_TXD
WIFI_32KHZ_1.8V

Technologic Systems Date
Title:
Rev: Designer Sheet of
15
TS-7680 FPGA
Sept. 1, 2015
B 20
FPGA required for:
- Auto-485 for two UARTs
- PWMs for DACs
- MUX for all UARTs
- BlueTooth Level Shifting
- Additional I/O
- HD4 Daughter Card (Future)
UART2 and UART3 changed to SPI
when Booting from SPI
R126 pop when WiFi is
MACH XO2 FPGA
1.8V
Bank 5
SPI Boot
or
UARTs
From CN99
Inputs
Boot
Flash
SPI Bus
From
MX286
(50 MHz)
Daughter Card
1
8
RN7-A
3.3K
4
5
RN7-D
3.3K
3
6
RN7-C
3.3K
C187
.1 uF C184 .1 uF
C192
.1 uF C190 .1 uF C189 .1 uF
C191
.1 uF
C183
.1 uF C181 .1 uF C169 .1 uF
C182
.1 uF
C188
.1 uF
R159
2.0K
R158
2.0K
R157
2.0K
JTAG
A7 IO_B0
C5 VCC_IO_0
H2 IO_B4
N8 IO_B2
K3 IO_B3
N6 IO_B2
G14
IO_B1
B12
IO_B0
K13
IO_B1
D12 IO_B1
A2 IO_B0
N7 IO_B2
B5 IO_B0
H3
IO_B4
G3
IO_B4
A4 TDO
C4 IO_B0
L13
GND
M1
IO_B3
P14 VCC_CORE
C2
IO_B5
H14 VCC_IO_1
M8
IO_B2
D2
GND
M3
IO_B2
A5
GND
J1 IO_B4
B11
GND
F1 IO_B4
N5 IO_B2
B10 VCC_IO_0
G12
IO_B1
B8 IO_B0_SDA
N2 IO_B2
C13
IO_B1
J2 IO_B4
M9 IO_B2
K1 IO_B3
A1 VCC_CORE
A9 IO_B0
P7 IO_B2
A13
DONE_IO_B0
A14 VCC_CORE
B9
IO_B0
D14 VCC_IO_1
C14
IO_B1
C1
IO_B5
D1
IO_B5
J13
IO_B1
P10
GND
L14
IO_B1
P12
IO_B2
P1 VCC_IO_2
B14
IO_B1
M13
IO_B1
E2
IO_B5
E12
IO_B1
G13
IO_B1
N4 IO_B2_SPI_SO
C7 NC
N1 VCC_CORE
F13
IO_B1
B1
IO_B5
C11
IO_B0
P9
IO_B2
F14
IO_B1
F12
IO_B1
M12
IO_B1
N11 VCC_IO_2
A12
IO_B0
N9
IO_B2
J14
IO_B1
M11
IO_B2
N12
IO_B2_SPI_SN
A11
IO_B0
N10
IO_B2
M7
IO_B2
D3 VCC_IO_5
A3
IO_B0
M4
IO_B2_MCLK
C9
IO_B0
B13
INIT# _IO_B0
P3
IO_B2_CSS
L2
GND
K12 IO_B1
L1 VCC_IO_3
N14
IO_B1
L12 VCC_IO_1
N3
IO_B2
K2
IO_B3
B3 IO_B0
C8
IO_B0_SCL
N13
IO_B1
H1 IO_B4
G2
GND
E13
IO_B1
A10
IO_B0
E14
IO_B1
M10
IO_B2
C6 IO_B0
M5 IO_B2
B2
IO_B5
F2
IO_B5
H13
GND
A6 TMS
B6 TCK
G1 VCC_IO_4
B7 IO_B0
P8 IO_B2
M2 IO_B3
M6 VCC_IO_2
P13
IO_B2_SPI_SI
J3
IO_B3
F3
IO_B4
H12
IO_B1
C12 IO_B0
P4 IO_B2
D13
GND
P5
GND
B4 TDI
A8 VCC_IO_0
L3 IO_B3
J12 IO_B1
P6 IO_B2
M14
IO_B1
P11
IO_B2
P2
IO_B2
K14
IO_B1
C10 PROG# _IO_B0
E3
IO_B5
E1
IO_B5
C3
IO_B5
U7
LATTICE_MACHXO_4000LUT_CB132
C179
.1 uF
2
7
RN11-B
1.5K
AUX_3.3V
AUX_3.3V
AUX_3.3V
250KHZ_PH0
FPGA_29
FPGA_31
FPGA_32
FPGA_34
DAC_PWM_3
RAM_1.8V
WL_EN
AUX_3.3V
JTAG_FPGA_TDO
JTAG_FPGA_TDI
JTAG_FPGA_TMS
JTAG_FPGA_TCK
RXD2_SPI_CLK
FPGA_SPI_CLK
FPGA_SPI_MOSI
RXD3_SPI_MISO
UART0_TXD
UART0_RTS
EN_7690_SPI_FLASH#
EN_SPI_BOOT_FLASH
AUX_3.3V
I2C_CLK
ETH_RESET#
FPGA_SPI_MISO
SPI_OFF_BD_SEL#
SPI_ON_BD_CS#
DIO_0_IN
TXEN3_485
UART1_TXD
EN_LS_OUT_2
DIO_2_IN
DIG_IN_3V
DC_TXD_3V
EN_RELAY_1
EN_RELAY_2
25MHZ_1.8V
BT_CTS
BT_EN
BT_RTS
BT_RXD
BT_TXD
ENET_CLK
FPGA_SPI_CS0#
WIFI_32KHZ_1.8V
250KHZ_PH1
DAC_PWM_1
FPGA_23
FPGA_25
FPGA_26
FPGA_27
FPGA_28
FPGA_30
FPGA_33
FPGA_35
DIO_1_IN
EN_LS_OUT_1
COM2_RXD_232_3V
DAC_PWM_2
DC_RXD_3V
RXD2_485_3V
RXD3_485_3V
UART4_RXD
TXD2_SPI_MOSI
EN_LS_OUT_0
FPGA_12MHZ
TXD3_SPI_CS#
EN_CL_0_1
EN_PU_AD0
EN_PU_AD1
EN_PU_AD2
EN_PU_AD3
TXEN2_485
CPU_RESET#
DAC_PWM_0
EN_CL_2_3
COM1_RXD_232_3V
COM1_TXD_232_3V
COM2_TXD_232_3V
FPGA_IRQ
UART1_RXD
FPGA_SPI_CS1#
I2C_DAT
UART0_RXD
SPI_OFF_BD_CS#
TXD2_485
TXD3_485
UART0_CTS
UART4_TXD
EN_DC_5V

Technologic Systems Date
Title:
Rev: Designer Sheet of
Relays
16
TS-7680 DACs and Relays
Sept. 1, 2015
B 20
Gain = 3.3
0-10V Out
150 Hz low pass filter
Gain = 3.3
0-10V Out
150 Hz low pass filter
Gain = 3.3
0-10V Out
150 Hz low pass filter
Gain = 3.3
0-10V Out
150 Hz low pass filter
10-bit DACs
1
2
3
5
4
K2
RELAY_SPDT_5V_5A_TH
1
2
3
D10
DIODE_BAT54-CC_SOT23
D
S
G
2
6
1
Q4-A
D
S
G
5
3
4
Q4-B
+
-
2
31
11
4
U4-A
R75
41.2K
C82
.1 uF
R107
100K
C215
.1 uF
C214
.1 uF
R33
30
C33
3.3 nF
R32
30
1
2
3
5
4
K3
RELAY_SPDT_5V_5A_TH
D
S
G
2
6
1
Q6-A
D
S
G
5
3
4
Q6-B
R74
41.2K
R105
100K
C213
.1 uF
C212
.1 uF
C34
3.3 nF
R31
30
+
-
6
57
U4-B
+
-
9
10 8
U4-C
+
-
13
12 14
U4-D
R76
41.2K
R106
100K
C211
.1 uF
C210
.1 uF
C35
3.3 nF
R30
30
R77
41.2K
R108
100K
C217
.1 uF
C218
.1 uF
C36
3.3 nF
R29
30
DAC3
DAC2
3
6
RN9-C
1.5K
4
5
RN9-D
1.5K
R92
Zero
R91
Zero
4 5
RN25-D
10K
36 RN25-C
10K
2 7
RN25-B
10K
18 RN25-A
10K
3 6
RN26-C
10K
45 RN26-D
10K
1 8
RN26-A
10K
27 RN26-B
10K
SW_5V
SW_5V
14V
DAC_0
EN_RELAY_1
RELAY_1_NO
RELAY_1_NC
RELAY_1_COM
SW_5V
EN_RELAY_2
RELAY_2_NO
RELAY_2_NC
RELAY_2_COM
DAC_1
DAC_2
DAC_3
DAC_PWM_3
DAC_PWM_1
DAC_PWM_2
DAC_PWM_0

ofSheetDesignerRev:
Title:
Date
Technologic Systems
17
TS-7680 Analog
Sept. 1, 2015
B 20
Analog In Channels
0-10V Input
0-10VInput
0-10V Input
0-10VInput
24V
Bipolar Analog Inputs
-5V to +5V Input Range
By adjusting resistor values
All A/D Inputs can be converted
to Bipolar, but must remove FETs
2
1
3
Q11
4
5
RN15-D
1.5K
2
7
RN15-B
1.5K
3
6
RN15-C
1.5K
1
8
RN15-A
1.5K
1 8
RN22-A
10K
3 6
RN22-C
10K
2 7
RN22-B
10K
4 5
RN22-D
10K
D14
40V
R80
41.2K
R50
7.87K
C221
.1 uF R38
240
G
S
DQ25
R98
Zero
2
1
3
Q13
D15
40V
R73
41.2K
R56
7.87K
C216
.1 uF R37
240
G
S
DQ26
R96
Zero
2
1
3
Q15
D16
40V
R79
41.2K
R57
7.87K
C222
.1 uF R35
240
G
S
DQ24
R94
Zero
2
1
3
Q17
D17
40V
R83
41.2K
R58
7.87K
C113
.1 uF R36
240
G
S
DQ23
R93
Zero
21
3
TVS14
NUP2105L_SOT23
21
3
TVS13
NUP2105L_SOT23
R85
41.2K
R55
7.87K
C78
.1 uF
R84
41.2K
R59
7.87K
C79
.1 uF
R102
100K R101 100K
R134
475K
R135
475K
R137
475K
R136
475K
AUX_3.3V
ADC0
EN_CL_0_1
AN_DIN_0
AUX_3.3V
ADC1
EN_CL_0_1
AN_DIN_1
AUX_3.3V
ADC2
EN_CL_2_3
AN_DIN_2
AUX_3.3V
ADC3
EN_CL_2_3
AN_DIN_3
ADC4 AN4_CAN_L ADC5 AN5_CAN_H
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
EN_PU_AD0
EN_PU_AD1
EN_PU_AD2
EN_PU_AD3

Technologic Systems Date
Title:
Rev: Designer Sheet of
SuperCap 20 Second Power Hold
20 seconds assumes 3 watt load
18
TS-7680 Super Cap Circuit
Sept. 1, 2015
B 20
(Optional Feature)
Super Cap
(20 sec.)
Supper Cap
Charging
Circuit
Boost
Regulator
Super Cap
Monitoring
SW_5V
AUX_3.3V
EN_CHRG#
SILAB_PWM
EN_TOP_OFF
5V_BOOST
POWER_FAIL
AN_SCAP_2
AN_SCAP_1
AN_CHRG

Technologic Systems Date
Title:
Rev: Designer Sheet of
19
TS-7680 5V Boost and Accelometer
Sept. 1, 2015
B 20
Accelerometer
(Optional Feature)
C228
.1 uF
C50
22 nF
4SCL
6SDA
8NC
5
GND
10
GND
12
GND
11 INT1
9INT2
7I2C_LSB
2
CAP
1
VDIO
16 NC
15 NC
13 NC
3DNC
14
VDD
U23
ACCEL_MMA8451_QFN16
AUX_3.3V
I2C_CLK
I2C_DAT
ACCEL_INT
ACCEL_INT2

ofSheetDesignerRev:
Title:
Date
Technologic Systems
Top Row Bottom Row
Left Left
20
TS-7680 Screw Term. Connectors
Sept. 1, 2015
B 20
DC Header
Right Right
24 Screw Term. Positions
FPGA_22 thru FPGA_35 go to FPGA (14)
FPGA_21, 23, 25, 27, 29 go to MX286 (5)
17 STC positions go to HD4
J1939 Shield
Option
FPGA_29 to SiLab uC
1
2
3
4
5
6
7
8
9
10
11
12
P1-A
13
14
15
16
17
18
19
20
21
22
23
24
P1-B
R89
Zero
R90
Zero
R88
Zero
16
14
12
10
8
6
4
2
15
13
11
9
7
5
3
1
18
20
22
24
34
26
28
30
32
17
19
21
23
25
27
29
31
33
36
38
35
37
HD4
HD_19X2_2.54MM
R71
1 ohm
C38
0.68 uF
RELAY_1_NO
RELAY_1_COM
RELAY_1_NC
RELAY_2_NC
RELAY_2_COM
RELAY_2_NO
AN_DIN_0
AN_DIN_1
AN_DIN_2
AN_DIN_3
485_PLUS
485_MINUS
DIO_0
AN4_CAN_L
AN5_CAN_H
DAC_2
DAC_3
DAC_2
DAC_1
DAC_0
P1_19
P1_18
AN_DIN_1
AN_DIN_0
250KHZ_PH0
VIN
SW_5V
AUX_3.3V
DIO_1
DIO_2
DAC_0
DAC_1
DIG_IN
TXD_CAN0
RXD_CAN0_5V
P1_20
DIO_1
DIO_0
AN_DIN_3
AN_DIN_2 DIO_2
DAC_3
FPGA_23
FPGA_25
FPGA_27
FPGA_29
FPGA_31FPGA_32
FPGA_34
P1_20
P1_19
P1_18
FPGA_21250KHZ_PH1
FPGA_26
FPGA_28
FPGA_30
FPGA_33
FPGA_35