Technologic Systems TS-7558 Quick start guide

Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7558 CPU, Ethernet, POR
1
25MHz
SN74LVC2G04DCKR
POR
OD Output
Link / Activity
Left LED (Green)
10/100 Ethernet
Reset
Latch EC-MJKF4602-PA08
Green
Yellow
TS-7558
May 20, 2011
12A
Res. PU
GPIO_A26
GPIO_A27
GPIO_A28
GPIO_A29
43 LED0/GPIO_A22
44 LED1/GPIO_A23
45 LED2/GPIO_A24
11 USB0_DP
12 USB0_DM
19 USB1_DP
18 USB1_DM
16 HOST_USB_RES
5INT28/USB_INT
127 DEV_USB_DP
126 DEV_USB_DM
125 DEV_USB_RES
107 UART_TXD0
108 UART_RXD0
113 UART0/GPIO_A2
49
RAM_QS0
118 SPI_CS0#
119 SPI_CS1#
117 SPI_CLK
116 SPI_MOSI
115 SPI_MISO
7SCL/GPIO_A14
6SDA/GPIO_A13
10 I2SCK/GPIO_A17
9I2SWS/GPIO_A16
8I2SSD/GPIO_A15
114 I2SDR/GPIO_A3
112 INT30/GPIO_A1
111 INT29/GPIO_A0
31 CLK_32768KHZ
120 CLK_OUT
35 V25_CONTROL
34 V125_CONTROL
30 NC
122 VFS_PGM
4TEST_MODE_EN
106 SYS_RESET#
104 JTAG_TCK
101 JTAG_TMS
55
RAM_DM0
80
RAM_WR#
78
RAM_RAS#
79
RAM_CAS#
50
RAM_CS#
51
RAM_CKE
52
RAM_CLK#
53
RAM_CLK
36 V18_CONTROL
54
RAM_DM1
83
RAM_ADD12
76
RAM_BA1
77
RAM_BA0
66 REF_IN_1.25V
84
RAM_ADD11
95
RAM_ADD0
57
RAM_D14
105 JTAG_DIN
100 JTAG_DO
56
RAM_D15
92
RAM_ADD3
60
RAM_D11
41 XTAL_25_OUT
99 JTAG_RST#
89
RAM_ADD6 88
RAM_ADD7
109
VDD_CORE_18
123
DEV_AN_33
33
VDD_AN_POW_33 13
VDD_HOST_AN33
15
HOST_PLL_18
121
VDD_CORE_18
38
SYS_PLL_18
23
VDD_AN_ETH33 29
VDD_AN_ETH33
75
VDD_RAM_25
64
VDD_RAM_25
103
VDD_33
39
VDD_33
2
VDD_33
20
VDD_CORE_18 32
VDD_CORE_18 47
VDD_CORE_18 82
VDD_CORE_18 98
VDD_CORE_18
94
RAM_ADD1
102 GND
48
RAM_QS1
110 GND
27
RX+ 28
RX-
85
RAM_ADD10
24
TX+
91
RAM_ADD4
25
TX-
59
RAM_D12
42 XTAL_25_IN
61
RAM_D10
74
RAM_D0 73
RAM_D1 72
RAM_D2
70
RAM_D4
87
RAM_ADD8
22
REF_RES
71
RAM_D3
67
RAM_D7
63
RAM_D8
69
RAM_D5
90
RAM_ADD5
68
RAM_D6
86
RAM_ADD9
97 GND 65 GND 40 GND
124 GND_USBD_AN
62
RAM_D9
81 GND 46 GND 37 GND 17 GND_HOST_AN 14 GND_HOST_AN
1GND_DEV_AN
96 GND
93
RAM_ADD2
3GND
26 GND_AN_ETH 21 GND_AN_ETH
58
RAM_D13
128
VCCA_U2O_33
U6
STAR_8132
Y2
XTAL-HC49
C37
15 pF
C38
15 pF
GNDVCC
3
2
1
4
5
6
U9
DUAL04
R26
680K C103
10 nF
R27
680K
3D
1CLK
6CLR#
5
VCC
4
Q
2
GND
U3
74LVC1G175
C72
.1 uF
2VCC
3GND
1
RESET#
U5
ST1001S-2.9V
R24
226 1%
R45
12.0K
R38
510
R33
11.5K
4RX+
5RX-
6RX_CT
3TX_CT
1TX+
2TX-
7
POE_RX
9
POE_45
11 LLED+
12 LLED-
13 RLED+
14 RLED-
17
ALIGN
18
ALIGN
15
SHD
16
SHD
8
POE_TX
10
POE_78
ETH
RJ_POE_4602
C105
10 nF
R104
100
R105
100
R19
226 1%
R20
226 1%
C75
.1 uF C76 .1 uF
FB8
C77
.1 uF C78 .1 uF
R39
510
R76
1.00K
C97
.1 uF
R85
0.0
R81
0.0
C44
.1 uF
C43
.1 uF
3.3V
FPGA_25MHZ
32KHZ
CPU_CLKOUT
JTAG_DOUT
GPIO_A23
GPIO_A22
GPIO_A17
GPIO_A16
GPIO_A15
GPIO_A3
JTAG_CLK
GPIO_A1
GPIO_A0
INT28
SDA
SCL
SPI_MISO
SPI_MOSI
SPI_CLK
GPIO_A29
GPIO_A28
CPU_UART_TXD
CPU_UART_RXD
USB_HOST1_DM
USB_HOST1_DP
USB_HOST0_DM
USB_HOST0_DP
3.3V
WD_RESET#
3.3V
UN-RESET
LOW_VOLT# CPU_TCK
JTAG_TMS
JTAG_DIN
1.2V
CONTROL_25
RAM_WR#
RAM_RAS#
RAM_CAS#
RAM_CS#
RAM_CKE
RAM_CLK#
RAM_CLK
RAM_BA0
RAM_BA1
RAM_DM0
RAM_DM1
RAM_QS0
RAM_QS1
ADD_[00:12]
ADD_00
ADD_01
ADD_02
ADD_03
ADD_04
ADD_05
ADD_06
ADD_07
ADD_08
ADD_09
ADD_10
ADD_11
ADD_12
DATA_[00:15]
DATA_00
DATA_01
DATA_02
DATA_03
DATA_04
DATA_05
DATA_06
DATA_07
DATA_08
DATA_09
DATA_10
DATA_11
DATA_12
DATA_13
DATA_14
DATA_15
1.8V
FRAME
3.3V
ETH_LEFT_LED#
ETH_RIGHT_LED#
3.3V
2.5V
ETH_3.3V
3.3V
EN_SD_POWER
SD_POWER#
POE_RX
POE_TX
POE_45
POE_78

Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7558 FPGA, JTAG Header
2
Pull-up and pull-down resistors
are 6 to 30K ohms
Set CONFIG_MODE to NONE
This allows all pins to be used
XP2-5 has:
9 blocks of 1Kx18 Block RAM
12 18x18 Multipliers
5K LUTS 2 PLLs
100 I/O with 144 pin package
"instant ON" = about 1.5 mS
input PLL clock = 10 MHz min
Power Supplies can be sequenced in any order
All I/O lines are tri-stated during power cycling
but must be monotonic
Page 37 of Data Sheet (Hot Socketing)
FPGA with 5000 LUTs
Interrupts
I2C
SPI_CS0#
I2S
SPI_CS1#
CLK+
CLK-
LED0
LED1
RLM
Console always is enabled
MODE1 and MODE2 states
are latched when
CPU_RESET# is deasserted
MODE1 and MODE2
have 4.7K resistor
pull-ups on WM-7550
JTAG
Header
26-pin
Mode 1 Mode 2 Boots from
1 1 NAND Flash
0 1
SD Card1 0
0 0
Off-board Flash
Off-board Flash
Use 680 ohm resistor
to GND to set low
Pin 54 Pin 138
(weak PD)
(weak PU)
TS-7500
TS-7550
WM-7551
TS-7552
TS-4500
1 1
1 1
00
1 0
Pin 71
0
7552 and 7553 FPGA pin 93 = MISO
Pin 37
1
1
1
1
0
00
1
1
1
0
Board ID bits
TS-7553 1 0 10
TS-7554 0 0 10
TS-7558 0 1 1
0
Hex
F
B
C
D
9
8
A
0
May 20, 2011
12A
54 and 71
biased low
must be
FPGA pins
139 must be
biased high
FPGA pin
40 IO
17 IO
27 IO
78 IO_CLK
90 IO
119 IO_CLK
65 IO
80 JTAG_DIN
81 JTAG_CLK
82 JTAG_DOUT
79 JTAG_TMS
3GND1
12 GND2 34 GND3 51 GND5 41 GND4 64 GND6 68 GND7 75 GND8 86 GND9 97 GND10
106 GND11 111 GND12 126 GND13
102
IO
104
IO
91
IO
72 IO
29
IO
115 IO
39 IO
28 IO_CLK
110 IO
1IO
15 IO
113 IO
13 OUT_CSSPIN
30 IO_CLK
129
IO
37 IO
2IO
32 IO
38 IO
9IN_CFG1
109 IO
7IN_PROGRAM#
69
IO
114 IO_CLK
116 IO_CLK
137 IO
141
IO
87
IO_CLK
88
IO_CLK
131
IO
47
IO
31
IO
43
IO
20
IO_INIT#
143
IO
5
IO
77
IO_CLK
138
IO
18
IO
6
IO
36
IO
11
IN_CSSPIS
46
IO
89
IO
122
IO
61
IO_CLK
19
IO
73
IO
132
IO
55
IO
35
IO
121
IO
52
IO
22
IO_CLK
44
IO
124
IO
16
IO_CCLK
142
IO
66
IO
8
IO_DONE
21
IO_CLK
53
IO
133
IO
96
IP
74
IO
99
IO
93
IO
58
IO_CLK 98
IO
144 IO
70
IO
45
IO
57
IO
120
IO_CLK
48
IO
23 VCC_AUX1
60 VCC_AUX2
85 VCC_AUX3
117 VCC_AUX4
24 VCC_INT1
59 VCC_INT2
84 VCC_INT3
118 VCC_INT4
100
IO
101
IO
107
IO
108
IO
10
IO
62
IO_CLK
103
IO
125
IO
71
IO
56
IO_CLK
54
IO
134
IO
130
IO
92
IO
127
IO
135 GND14 139 GND15
63 VCCO_4
42 VCCO_5
49 VCCO_5
33 VCCO_6
4VCCO_7
14 VCCO_7
83 VCC_JTAG
140 VCC_PLL_0
67 VCC_PLL_1
94 IO
50 IO
123 IO
25 TOE
26 CFG0
112 VCCO_1
128 VCCO_0
95 VCCO_2
105 VCCO_2
76 VCCO_3
136 VCCO_0
U8
LATTICE_XP2_144
R25
226 1%
1 2
RN2-A
4.7K
3
4
RN2-B
4.7K
R21
226 1%
R22
226 1%
R23
226 1%
RedGreen
31
42
LED1
DUAL_RTA_LED
12 SPI_MOSI
10 3.3V
8RXD
6TCK
4TDI
2TMS
11
SPI_CS#
9
SPI_MISO
7
MODE1/TXD
5
MODE2/DIO
3
GND
1
TDO
14 SPI_CLK 13
DIO_13
16 RESET# 15
DIO_15
18 DIO_18
20 DIO_20
22 DIO_22
24 DIO_24
26 DIO_26
17
DIO_17
19
DIO_19
21
DIO_21
23
DIO_23
25
DIO_25
HD1
HD_JTAG26_2009
FB4
R18
226 1%
1.2V
3.3V
JTAG_DOUT
JTAG_DIN
JTAG_CLK
JTAG_TMS
UN-RESET
WD_RESET#
NAND_CS#
NAND_WR#
NAND_ALE
NAND_CLE
NAND_BUSY#
NAND_WP#
FPGA_25MHZ
INT28
CPU_UART_TXD
CPU_UART_RXD
SPI_CLK
SPI_MOSI
SPI_MISO
RTC_SDA
RTC_SCL
GPIO_A0
GPIO_A1
SDA
SCL
GPIO_A3
GPIO_A15
GPIO_A16
GPIO_A17
JTAG_TMS
JTAG_DIN
GPIO_A28
GPIO_A29
ETH_LEFT_LED#
ETH_RIGHT_LED#
32KHZ
GPIO_A23
GPIO_A22
FPGA_CONFIG#
3.3V
NAND_D[0:7]
NAND_RD#
JTAG_DIN
MODE2
JTAG_TMS
JTAG_DOUT
3.3V
JTAG_CLK
CONSOLE_RXD CONSOLE_TXD
BOOT_SPI_CLK
BOOT_SPI_MOSI BOOT_SPI_CS#
BOOT_SPI_MISO
WD_RESET#
MODE2
CONSOLE_TXD
CONSOLE_RXD
BOOT_SPI_CS#
BOOT_SPI_MISO
BOOT_SPI_MOSI
BOOT_SPI_CLK
SCL
SDA
DIO_17
DIO_19
DIO_21
DIO_23DIO_24
DIO_22
DIO_20
DIO_18
EN_SD_POWER
PUSH_SW# SD_D0
SD_D1
SD_D2
SD_D3
SD_CMD
SD_CLK
NAND_D0
NAND_D1
NAND_D2
NAND_D3
NAND_D4
NAND_D5
NAND_D6
NAND_D7
EN_USB_POWER
CAN_TXD
CAN_RXD
485_TXEN
485_TXD
485_RXD
UART2_RXD
UART1_RXD
UART1_TXD
UART2_TXD
5V
EN_OUT1#
EN_OUT2#
EN_OUT3#
EN_OUT4#
ADC_CLK
ADC_DATA
ADC_CS#
ADC_MUX_A0
ADC_MUX_A1
ADC_MUX_A2
CL_CH2_EN
CL_CH3_EN
CL_CH4_EN
ADC_GAIN_2X
BUF_IN_1
BUF_IN_2
BUF_IN_3
BUF_IN_4
BUF_IN_5
BUF_IN_6
BUF_IN_7
BUF_IN_8
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
DIO_23
CL_CH1_EN
DIO_24
DIO_25
DIO_25

Technologic Systems Date
Title:
Rev: Designer Sheet of
3
TS-7558 RAM, RTC, Flash, SD card
DDR1 SDRAM
I2C bus
12 pF
RTC
The DDR clock differential pair is the most critical trace on the entire board
The data lines in each byte lane can be swapped on the RAM chip for optimal layout
The trace length of each data line (in a single byte lane) and the respective
QS and DM signals must be matched to within 2.5 mm
Address and Command signals can be grouped together, but must be isolated
from data and M_DSQ and M_DM signals (by at least .5 mm)
Or run them on different layer
Example: D0 and D5 can be swapped, but not D7 and D8
DDR RAM Notes
NAND Flash
512 Mbyte
64 Mbyte
Micro SD Card Socket
RN4 is 4.7K !
12A
May 20, 2011
60 mohm
(I2C)
C67
.1 uF
29 A0
30 A1
31 A2
32 A3
35 A4
36 A5
37 A6
38 A7
39 A8
40 A9
28 A10
41 A11
42 A12
26 BA0
27 BA1
23 RAS#
22 CAS#
21 WE#
44 CKE
45 CLK
24 CS#
1
VCCINT 18
VCCINT
14 NC 3
VCCIO 9
VCCIO 55
VCCIO 61
VCCIO
2
DQ0 4
DQ1 5
DQ2 7
DQ3 8
DQ4 10
DQ5 11
DQ6 13
DQ7
54
DQ8 56
DQ9 57
DQ10 59
DQ11 60
DQ12 62
DQ13 63
DQ14 65
DQ15
6
GNDIO 12
GNDIO
34
GND 48
GND
52
GNDIO 58
GNDIO
47 UDM
49 VREF
50 DNU
51
UDQS
53 NC
66
GND
64
GNDIO
16
LDQS
17 NC/A13
19 DNU
20 LDM
25
NC 43
NC
46 CLK#
33
VCCINT
15
VCCIO
U10
DDR1_RAM
C82
.1 uF
C61
.1 uF C62 .1 uF C63 .1 uF C64 .1 uF C65 .1 uF C66 .1 uF
R106
100
R102
100
R103
100
1 2
RN1-A
4.7K
3 4
RN1-B
4.7K
5 6
RN1-C
4.7K
7 8
RN1-D
4.7K
5
6
RN2-C
4.7K
7
8
RN2-D
4.7K
1 2
RN3-A
4.7K
3 4
RN3-B
4.7K
5 6
RN3-C
4.7K
7 8
RN3-D
4.7K
6SCL
5SDA
1XIN
2XOUT
8
VCC
7OUT 3
BAT
4
GND
U12
M41T00S
1 4
2 3
Y1
XTAL_SMT_8X3
C83
.1 uF
K1
R75
1.00K
1 2
RN4-A
2.2K
3
4
RN4-B
2.2K
5 6
RN4-C
2.2K
7
8
RN4-D
2.2K
C120
10 nF
R51
2.00K
9CS#
8RD#
18 WR#
17 ALE
16 CMD
19 WP#
12
VCC1 37
VCC2
29
D0 30
D1 31
D2 32
D3 41
D4 42
D5 43
D6 44
D7
13
GND2 36
GND3
7BUSY#
6
GND1
U13
NAND_FLASH2
C93
.1 uF
7DATA_0
8DATA_1
1DATA_2
2DATA_3
5CLK
3COMMAND
4
VDD
6
GND
10
FRM2
9
FRM1
11
FRM3
12
FRM4
CN7
CONN_MICRO_SD
D
S
G
1
2
3
Q1
DMP2305
R77
1.0K
R43
12.0K C70
.1 uF
R136
6.04K
R135
6.04K
R134
6.04K
C45
.1 uF
ADD_00
ADD_01
ADD_02
ADD_03
ADD_04
ADD_05
ADD_06
ADD_07
ADD_08
ADD_09
ADD_10
ADD_11
ADD_12
RAM_BA0
RAM_BA1
RAM_RAS#
RAM_CAS#
RAM_WR#
RAM_CS#
RAM_DM0
RAM_DM1
RAM_QS0
RAM_QS1
RAM_CKE
RAM_CLK#
RAM_CLK
2.5V
DATA_07
1.2V
DATA_[00:15]
ADD_[00:12] 1.2V
DATA_06
DATA_05
DATA_04
DATA_03
DATA_02
DATA_01
DATA_00
DATA_08
DATA_09
DATA_10
DATA_11
DATA_12
DATA_13
DATA_14
DATA_15
CONSOLE_TXD
CONSOLE_RXD
3.3V
JTAG_TMS
SPI_MOSI
CPU_TCK
JTAG_DIN
NAND_BUSY#
2.5V
UN-RESET
CPU_CLKOUT
SCL
RTC_SCL
RTC_SDA
3.3V
3.3V
MODE2
NAND_WP#
3.3V
NAND_ALE
NAND_CLE
NAND_CS#
NAND_RD#
NAND_WR# NAND_D0
NAND_D1
NAND_D2
NAND_D3
NAND_D4
NAND_D5
NAND_D6
NAND_D7
NAND_BUSY#
PUSH_SW#
SD_POWER#
SD_D0
SD_D1
SD_D2
SD_D3
SD_CMD
SD_CLK
3.3V
3.3V JTAG_CLK
FPGA_CONFIG#
SDA

Technologic Systems Date
Title:
Rev: Designer Sheet of4RLM
TS-7558 Power Supplies
2.5V Regulator
Est. 100 mA load
1.84V nominal
1.8V Regulator
Measured 420 mA load
1.2V Reg.
LDO
FPGA Core
DFN package
3.32V nominal
3.3V Regulator
DFN package
May 20, 2011
A 12
Analog 3.3V
Ethernet
ETH_3.3V
C71
.1 uF
C101
10 nF
C102
10 nF
C100
10 nF
2
1
3
Q20
R101
100
C69
.1 uF
C74
.1 uF
C81
.1 uF
C80
.1 uF C110
10 nF
C111
10 nF
C109
10 nF
C51
.1 uF
C52
.1 uF
C53
.1 uF C54
.1 uF C55
.1 uF
C56
.1 uF C57 .1 uF C58 .1 uF C59 .1 uF C114
10 nF
C116
10 nF
C118
10 nF
C119
10 nF
C115
10 nF
C117
10 nF
C60
.1 uF
C84
.1 uF C85 .1 uF C86 .1 uF C87 .1 uF C88 .1 uF C112
10 nF
C113
10 nF
C79
.1 uF C121
10 nF
C73
.1 uF C107
10 nF
C108
10 nF
C106
10 nF
R50
2.00K
R44
12.0K
C27
10 uF
C25
10 uF
C26
10 uF
FB6
R87
11.0K
R58
15K
R99
1 ohm
L2
COIL3.3UH
2% FT
1.20V1.5-6.0V
3% LP
Low = LP
1VIN
3EN
5
VOUT
2
GND
4ECO
U7
NCP584-1.2V
FB10
5VIN
4PIN
6EN
3
SW
2
PGND
1
FB
7
AGND
U19
FAN2002
C28
10 uF
FB7
R57
15K
L3
COIL3.3UH
5VIN
4PIN
6EN
3
SW
2
PGND
1
FB
7
AGND
U17
FAN2002
R91
4.75K
R47
17.4K
R54
0.20
C24
10 uF
R55
0.20
C23
10 uF
C49
.1 uF
C31
10 uF
6.3V
2%
1.8-6.0V
1VIN
3EN
5
VOUT
2
GND
4NC
U16
XC6221B332MR
C94
.1 uF
C30
10 uF
6.3V
C29
10 uF
6.3V
R98
4.7ohm
1.2V
LOW_VOLT#
1.8V
3.3V
3.3V
CONTROL_25
3.3V
2.5V
3.3V
5V
1.8V
5V 3.3V
3.3V
ETH_3.3V
5V

Technologic Systems
Title:
Rev: Designer Sheet of
5V Power Supply (2.0 Amps)
1SMB30AT3G
600W
Power
Conn.
5
TS-7558 5V Power
5.0V to 30V
Input Power
122 mohm typ.
VIN
Date: May 20, 2011
12A
50 mohm 40V 5V
PF3
PTC_1.5A_33V
FB3
FB5
C18
10 uF
50V
FB9
C158
.1 uF
50V
1.25V
4.5V-42V
8VIN
4GND
7
VCC
1
ADJ
2RT
3
FB
6
FET_GATE
5
CUR_SENSE
9PAD
U21
LM25085MY
D
S
G
12
3
Q4
DMP4051
D2
L4
15 uH
C40
.47 uF
16V
R70
91.0K
C32
3.3 nF
C33
3.3 nF
R113
54.9K
C20
10 uF
6.3V
C99
470 uF
6.3V
R61
3.24K
R60
3.24K
C156
.1 uF
50V
C155
.1 uF
50V
C157
.1 uF
50V
TVS14
TVS-30V
R88
10K
VIN
5V
POWER+
POWER-

Technologic Systems Date
Title:
Rev: Designer Sheet of
6
RS-485 Driver
CAN Tranceiver
CAN Term
24V
26V clamp
COM
DB9M
RS-232 Transceiver
Level shifter
RLM
TS-7558 COM port, CAN, RS-485
May 20, 2011
12A
5V3.3V
485 Term
19 OE
1DIR
2A1
3A2
4A3
5A4
18
B1
17
B2
16
B3
15
B4
6A5
7A6
8A7
9A8
14
B5
13
B6
12
B7
11
B8
20
VCC
10
GND
U15
74LVC245
R34
124
21
3
TVS19
NUP2105L
DB-9M
6TX-_(DSR)
4RX+ _(DTR)
9RX-_(RI)
1TX+ _(DCD)
3TXD
7RTS
5GND
2RXD
8CTS
11
FRAME2
10
FRAME1
J6
CON-DB9
V-
V+
Vcc
GND
C2-
C2+
C1-
C1+
R2
R1
T2
T1
1
2
3
4
5
6
7
89
10
11
12 13
14
15
16
U14
SP202
SIPEX
C50
.1 uF
C96
.1 uF
C90
.1 uF
C92
.1 uF
C91
.1 uF
R66
3.24K R67 3.24K
C104
10 nF
4TXD
1RXD
3TXEN
2RXEN#
8
VCC
6
X+
7
X-
5
GND
U18
ISL8485_5V
R64
3.24K
R65
3.24K
R48
17.4K
C89
.1 uF
4RXD
1TXD
5VREF
8SEL 3
VCC
7
CANH
6
CANL
2
GND
U11
TJA1050
R151
6.04K
R150
6.04K
R149
6.04K
R148
6.04K
R82
0.0
R35
124
RXD_485_5V
485_TXD
485_TXEN
5V
3.3V
RXD_485_5V
UART1_RXD
485_RXD
5V
CAN_TXD
CAN_RXD_5V
5V
UART1_TXD
UART2_TXD
CAN_H
CAN_L
UART2_RXD
CAN_RXD CAN_RXD_5V
FRAME
CAN_H
CAN_L
5V
SINK_1#
SINK_2#
SINK_3#
SINK_4# EN_OUT4#
EN_OUT3#
EN_OUT2#
EN_OUT1#
3.3V

ofSheetDesignerRev:
Title:
Date
Technologic Systems
TS-7558 USB, Temp Sensor
RLM 7
SD Boot
Force Boot
to SD card
12
May 20, 2011
A
Dual USB Host
USB Power Switch
60 mohm
Temp Sensor
LM73CIMK-0
Push Switch
Change memory
16 MB Phase
U24 is not populated
USB
Dual
4
1
2
3
5
6
7
8
9
FRAME 10
FRAME
11
FRAME 12
FRAME
J3
CONN_USB_DUAL
FB11
FB12
R42
12.0K
C48
.1 uF
C68
.1 uF
2
D1
3GND
1V+
4
D2
TVS4
BGX50A
R41
12.0K
D
S
G
1
2
3
Q3
DMP2305
1
ADD
6SDA
4SCL
3
VCC
5ALERT
2
GND
U20
LM73
C95
.1 uF
1
2
3
4
SW1
PUSHSW_RT
C46
.1 uF
2
D1
3GND
1V+
4
D2
TVS5
BGX50A
16 CLK
15 D_DQ0
8Q_DQ1
7CS#
9W# _DQ2
1HOLD# _DQ3
2
VCC
3
DNU1 4
DNU2 5
DNU3 6
DNU4 11
DNU5 12
DNU6 13
DNU7 14
DNU8
10
GND
U24
PCM_SPI_128MBIT
C41
.1 uF
R78
1.00K
MODE2
FRAME
USB_5V
5V
USB_5V 5V
SDA
SCL
3.3V
USB_5V_ON#
FRAME
PUSH_SW#
5V
USB_HOST1_DM
USB_HOST1_DP
USB_HOST0_DM
USB_HOST0_DP
3.3V
DIO_17
DIO_18
DIO_19
DIO_20
3.3V

Technologic Systems Date
Title:
Rev: Designer Sheet of
8
TS-7558 Isolated Digital Outputs
May 20, 2011
A 12
8 mA
70V
80V
ISO_OUT # 1
Vf = 1.2V typ.
70V
80V
ISO_OUT # 2
Vf = 1.2V typ.
70V
80V
ISO_OUT # 3
Vf = 1.2V typ.
70V
80V
ISO_OUT # 4
Vf = 1.2V typ.
8 mA
8 mA
8 mA
5V 3.3V
4 Isolated Outputs
Buffer for Isolated Inputs
200 mA at 40V max.
Outputs rated for
1
2
4
3
OP11
FOD817D
TVS21
TVS-43V
1
2
4
3
OP12
FOD817D
TVS22
TVS-43V
1
2
4
3
OP10
FOD817D
TVS23
TVS-43V
1
2
4
3
OP9
FOD817D
TVS24
TVS-43V
R181
240
R183
240
R185
240
R187
240
2
1
3Q33
TRAN_ZXTN620MA
2
1
3Q32
TRAN_ZXTN620MA
2
1
3Q31
TRAN_ZXTN620MA
2
1
3Q30
TRAN_ZXTN620MA
R180
240
R182
240
R184
240
R186
240
19 OE
1DIR
2A1
3A2
4A3
5A4
18
B1
17
B2
16
B3
15
B4
6A5
7A6
8A7
9A8
14
B5
13
B6
12
B7
11
B8
20
VCC
10
GND
U22
74LVC245
OUT_P1
OUT_N1
3.3V
SINK_1#
OUT_P2
OUT_N2
3.3V
OUT_P3
OUT_N3
3.3V
OUT_P4
OUT_N4
3.3V
SINK_2#
SINK_3#
SINK_4#
BUF_IN_8IN_5V_8
IN_5V_2
IN_5V_7 BUF_IN_7
BUF_IN_6IN_5V_6
IN_5V_1
IN_5V_3
IN_5V_4
3.3V
BUF_IN_1
BUF_IN_2
BUF_IN_3
BUF_IN_4
IN_5V_5 BUF_IN_5

ofSheetDesignerRev:
Title:
Technologic Systems
9
TS-7558 Isolated Digital Inputs
A
ISO_IN # 1
ISO_IN # 2
FOD817DSD
BC857C
BC857C
ISO_IN # 3
BC857C
ISO_IN # 4
ISO_IN # 5
FOD817DSD
BC857C
BC857C
ISO_IN # 6
BC857C
ISO_IN # 7
ISO_IN # 8
FOD817DSD
BC857C
BC857C
Isolated Inputs 32V tolerant 50 KHz Bandwidth
Date: May 20, 2011
12
Logic high = 3V-30V
1
2
4
3
OP1
FOD817D
R194
25.5K
R142
6.04K
1
2
4
3
OP2
FOD817D
2
1
3
Q15
1
2
3
D30
BAV99-2
R170
140
R152
649
TVS6
TVS-30V
R161
25.5K
R140
6.04K
2
1
3
Q16
1
2
3
D31
BAV99-2
R171
140
R153
649
1
2
4
3
OP3
FOD817D
R162
25.5K
R141
6.04K
2
1
3
Q17
1
2
3
D32
BAV99-2
R172
140
R154
649
TVS7
TVS-30V
TVS8
TVS-30V
1
2
4
3
OP4
FOD817D
R163
25.5K
R143
6.04K
1
2
4
3
OP5
FOD817D
2
1
3
Q18
1
2
3
D33
BAV99-2
R173
140
R155
649
TVS9
TVS-30V
R164
25.5K
R144
6.04K
2
1
3
Q19
1
2
3
D34
BAV99-2
R174
140
R156
649
1
2
4
3
OP6
FOD817D
R165
25.5K
R145
6.04K
2
1
3
Q12
1
2
3
D35
BAV99-2
R175
140
R157
649
TVS10
TVS-30V
TVS11
TVS-30V
1
2
4
3
OP7
FOD817D
R166
25.5K
R146
6.04K
1
2
4
3
OP8
FOD817D
2
1
3
Q13
1
2
3
D36
BAV99-2
R176
140
R158
649
TVS12
TVS-30V
R167
25.5K
R147
6.04K
2
1
3
Q14
1
2
3
D37
BAV99-2
R177
140
R159
649
TVS13
TVS-30V
5V
IN_P1
IN_N1
IN_5V_1
5V
IN_5V_2
IN_P2
IN_N2
5V
IN_5V_3
IN_P3
IN_N3
5V
IN_P4
IN_N4
IN_5V_4
5V
IN_5V_5
IN_P5
IN_N5
5V
IN_5V_6
IN_P6
IN_N6
5V
IN_P7
IN_N7
IN_5V_7
5V
IN_5V_8
IN_P8
IN_N8

Technologic Systems
Title:
Rev: Designer Sheet of
10
TS-7558 ADC
A
Date: May 20, 2011
12
12-bit ADC
3.300V 0.5% tolerance
0-3.3V levels
Precision 3.3V Reg.
4 Channels of 12-bit A/D ADC notes
typ. MUX ON resistance = 120 ohm
typ. Delta between chan = 10 ohm
Reading channel 0 allows
calibrating out most error
Input Imedance = 70 Kohm
TVS adds 1000-3000 pF
Op Amp gain = 1 or 2
Gain = 2 for 0-5V range
For I2C ADC
R115-R118 not normally Populated
11
S0
10
S1
9
S2
6
EN#
3
Z
13 Y0
12 Y3
1Y4
5Y5
15 Y2
14 Y1
2Y6
4Y7 7
VEE
8
GND
16 VCC
U27
74HCT4051
1VIN
3EN
5
3.3V
4
NC
2
GND
U23
LP2980A-3.3
4
CLK
6
CS#
5
DATA
3VIN
1
VA
2
GND
U25
ADC121S021
R97
4.7ohm
C21
10 uF
6.3V
R53
0.20
C22
10 uF
R95
4.75K
R94
4.75K
G
S
D
D
S
G5
2
6
1
3
4
Q5
DUAL_NCHAN
R132
43.2K
R52
2.00K
R126
47.00K
R125
47.00K
R127
47.00K
R124
47.00K R128
47.00K
R123
47.00K
R121
47.00K
R120
47.00K
R109
220
G
S
D
D
S
G
5
2
6
1
3
4
Q7
DUAL_NCHAN
R110
220 R111
220
G
S
D
D
S
G
5
2
6
1
3
4
Q8
DUAL_NCHAN
R112
220
R131
43.2K
R122
47.00K
R92
4.75K
R93
4.75K
TVS15
TVS-30V
TVS16
TVS-30V
TVS17
TVS-30V
TVS18
TVS-30V C47
.1 uF
R90
4.75K
R74
1.00K
-
+
3
14
2
5
U4 LMV321_DCK
C98
.1 uF
R68
3.24K
R69
3.24K
R130
43.2K
R115
3.24K R116 3.24K R117 3.24K R118 3.24K
R30
221K
ADC_MUX_A0
ADC_MUX_A1
ADC_MUX_A2
ADC_CLK
ADC_CS#
ADC_DATA
5V
ADC_GAIN_2X
ADC_CH1
CL_CH1_EN
ADC_CH2
CL_CH3_EN
ADC_CH3
ADC_CH4
CL_CH2_EN CL_CH4_EN
VIN
ADC_CH1 ADC_CH2 ADC_CH3 ADC_CH4
EN_USB_POWER
USB_5V_ON#
3.3V
ADC_CLK
ADC_CS#
5V
AN_5V
AN_5V

TS-7558 Screw Terminals
May 20, 2011
1211A
Technologic Systems Date
Title:
Rev: Designer Sheet of
2x20 positions of Screw Terminals
Top Row Bottom Row
Left
Right
Left
Right
R80 is not populated
R80
0.0
R84
0.0
1
2
3
4
5
6
7
8
9
10
P1-A
11
12
13
14
15
16
17
18
19
20
P1-B
1
2
3
4
5
6
7
8
9
10
P2-A
11
12
13
14
15
16
17
18
19
20
P2-B R83
0.0
IN_P1
IN_N1
IN_P2
IN_N2
IN_P3
IN_N3
IN_P4
IN_N4
IN_P5
IN_N5
IN_P6
IN_N6
IN_P7
IN_N7
IN_P8
IN_N8
OUT_P1
OUT_N1
OUT_P2
OUT_N2
OUT_P3
OUT_N3
OUT_P4
OUT_N4
ADC_CH1
ADC_CH2
ADC_CH3
ADC_CH4
FRAME
POWER-
POWER+
POWER-

Technologic Systems Date
Title:
Rev: Designer Sheet of
12
TS-7558 POE
May 20, 2011
A 12
5uF (min) Input Filter
12V
150V
80V
POE Side Isolated 24V Out
48V DC Input
48VDC IN
200 KHz typ.
$2.36 @ 100
Direct from LinearTech
Nominal
Full Wave
Rectifiers GND
6.5V typ.
1.2V typ drop
24V nominal
POE_24V
POE13F-24L
C147
1000 pF
2KV
FB14
C142
.1 uF
100V
C132
1uF
100V
C133
1uF
100V
TVS40
TVS-58V
13 VPORTP
6NC
5RCLASS
12 SIGDISA
7VPORTN
10 POUT
1PGND
8PGND
4
PVCC
3
NGATE
14
SENSE
2
ITHRUN
11
PWRGD#
15
VFB
16
PGND
9
PGND
U28
LTC4267-1
R199
45.3 1%
1
2
11
12
10
3
8
7
6
5
4
NC 9
NC
T1
XFORM_POE13F-50L
R200
0.10 R201
0.10 R202
0.10
2
1
3
Q11
1
2
3
6
5
4
Q9
TRANS_FET_FDC2512
TVS41
TVS-58V
1
2
3
D41
BAV99
1
2
3
D40
BAV99
FB13
1.24V
3
5
4
2
1
U29
TLV431_SOT23-5
+
-
3
4
1
2
FW2
RECT_FW1A
+
-
3
4
1
2
FW1
RECT_FW1A
K
A
LED2
LED
Green
C42
.1 uF
C141
.1 uF
100V
C140
.1 uF
100V
C153
1 uF
25V
R137
6.04K
R138
6.04K
R139
6.04K
R191
25.5K R192 25.5K
C148
33 nF
C130
15 uF
100V
C34
100 uF
50V
C149
100 pF
D3
R31
221K
R32
221K
R198
45.3 1%
R40
12.0K
2
1
3Q10
R193
25.5K
R72
64.9K
C17
10 uF
50V
1
2
4
3
OP18
LTV357
R160
649
9V
POE_GND
9V
POE_GND
POE_+
POE_-
POE_+
POE_-
POE_RX
POE_TX
POE_45
POE_78
POE_GND
VIN