TEI FDC-3 User manual

••
FDC·3 li-
CARD USER'S GUIDE .. Et

FDC-3
FLOPPY-DISK
CONTROLLER
USER MANUAL

CON TEN T
IIKTRODUCTION
1.1 General
1.2 Physical Description
II INSTALLATION
III THEORY OF OPERATION
3.1 Address Decoder
3.2 Drive-Select Latch
3.3 Function-Select Logic
3.4 Bidirectional Bus Buffers
3.5 Read/Write Clock Generation
3.6 1791 Controller
3.7 Miscellaneous Logic
3.8 Jumper Selection of Various Functions
IV SOFTWARE CONSIDERATIONS
4.1 FDC-3 Card
4.2 1791 Device
V HARDWARE CONSIDERATIO~S
5.1 Drive Configuration
5.2 Signal-Cable Connections
VI USER REPAIR GUIDE
1-1
1-1
2-1
3-1
3-1
3-1
3-1
3-3
3-5
3-7
3-9
4-1
4-1
5-1
5-1
6-1
A TEl,
A.l
A.2
A.3
INC. T/DOS DISKETTE READ/WRITE ERROR INDICATIONS
General
Commands
Error-Recovery Procedures
FIG U RES
A-I
A-I
P.-4
1-1 TEl, Inc. FDC-3 Floppy-Disk Controller
3-1 FDC-3 Card Block Diagram
3-2 1791 Device Block Diagram
3-3 FDC-3 Card Address Jumper Selection
3-4 Drive-Ready Delay Jumper Selection
6-1 Card Ejector, Left SidE
TAB L E S
5-1 Regular Drive Signal Connections
5-2 Miniature Drive Signal Connections
A-I Type ICommand Codes
A-2 Type II Command Codes
A-3 Type III Command Codes
1-0
3-0
3-4
3-8
3-10
6-0
5-2
5-3
A-I
A~2
A-2
i

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•

SECTION I
INTRODUCTION
1.1 GENERAL
The TEl, Inc. FDC-3 Floppy-Disk Controller combines the 1791 LSI
floppy-disk controller device and supporting logic to control up to
eight standard drives and up to three mini drives - single or double-
sided, single or double density. The 1791 device allows software
selection of both density and number of sides for ease in changing
system conf iguration.
The FDC-3 Floppy-Disk
compatible formats;
automatic track-seek
detection.
Controller also effers such features as IBM-
buffered control, data, and status lines,
with verification; and CRC generation and
The TEl, Inc. FDC-3 Floppy-Disk Controller was specifically designed
to operate reliably in a TEl, Inc. ComFuter System using TEl, Inc.
system components. Although the FDC-3 Floppy-Disk Controller may work
properly in another manufacturer's computer, or with another
manufacturer's components, TEl, Inc. cannot guarantee that it will do
so.
1.2 PHYSICAL DESCRIPTION
The FDC-3 Controller card (Figure 1-1) consists of 31 integratec
circuits, plus supporting components; 50-pin socket for standard (8")
diskette-drive signal cable; and a 34-pin socket for miniature (5.25")
drive signal cable; all mounted on a 5" x 10" (127-mm x254-mill)
fiberglass double-sided etched-circuit board complete with a standard
S-IOO bus connector that has gold-plated contacts for reliability and
long life.
1-1

SECTION II
INSTALLATIOK
1) Turn System power off.
CAUTION! NEVER INSTALL OR REMOVE ACIRCUIT CARD WITH POWER ON!
2) Install card in any card slot. If the FDC-3 card replaces an FDC-
2
card, install in same slot to avoid having to move cables.
Note that the edge-connector location prevents plugging the card
in backwards.
3) Plug signal cable(s) into FDC-3 card. Cable from standard (8")
drive(s) plugs into large connector. Cable from miniature
(5.25") drive(s) plugs into small connector. Be sure
connector (s) firmly seated.
4) Turn System on, with all drive doors open. If T/DOS Version 1.44
(or lower) information appears (after CRT warmup) with drive
doors open, FDC-3 card will not work properly.
5) Place System diskette(l) in drive A(2), close drive door, wait
for memory-size prompt, then enter size (in K) for desired
program, or press RETURN to load maximum size automatically.
6) Check CRT Display. If T/DOS Version 2.0 (or higher) installed,
System is ready for operation.
(1) Consult local documentation, Supervisor, or Dealer for correct
diskette insertion method on your System. Diskette should not be
Wr i te-Protected, if recording on disk et te requi red.
(2)TEI, Inc. Systems with eight function keys on keyboard, can load
T/DOS Version 2.0 (or higher) from drives B, C, or D, if desired.
Press key 8 to load from drive B, key 7 to load from drive C, keys 7
and 8 to load from drive D.
2-1

DRIVE
a
Dr ive #
/Datil
Reset
....
i'
Read/Write
Drive-Select
~
,-
1791
v
Clk
Clock
Raw Dat
Latch
i'
Generator
v
Rd Clk
i'
Earlv
-
~ ..
Lat0
-
Do
Bid i rectional
/
Dal
....
Write Data
....
DI
Buss Driver
......
,-
::.
Write Gate
Di rect ion
~
"
Step
....
Head Load
"
'/
Head Loadedl Delay
1
......
Address
"
A2-A7
---
,
Write Fault ~ Decoder
A2
'/
F
I'
-----0
I . /
Write Protect
MatrIx
G
Index Pulse
AD. Al
.....
......
".
1/
Ready
I
......
I
Delav
SINP
R/W
.....
SOUT
Function
".
1/
Track. 0
PD BIN
Select
PWR
Logic
Figure 3-1
FDC-3 Floppy-Disk Controller Card Block Diagram

SECTION III
THEORY OF OPERATION
The TEl, Inc. FDC-3 Floppy-Disk Controller Card (Figure 3-1) contains
an Address Decoder, Drive-Select Latch, Function-Select Latch,
Bidirectional Bus Buffers, crystal-controlled Read/Write Clock
Generator with Digital phase-Locked loop, type 1791 MOS LSI
controller, and miscellaneous logic.
3.1 ADDRESS DECODER
The basic FDC-3 address is XXOY to XXFY (hex) where xx is "don't-care"
(high-order address byte not decoded on FDC-3 card), 0 to F is jumper-
selected on the FDC-3 card, and Y is partly jumpered and partly
software-controlled to direct the accompa~ying data byte to the proper
card or 1791 device register (Section 3.6).
Comparator Z26 and gates in Z24 and Z25 form the FDC-3 address
decoder. The three-row by five-column matrix between Z26 and the card
edge enables the jumper selection described above (and in Section
3.8) •
When the CPU sends date. to the address Lelected by the jumpers, the
Address Decoder enables the card to receive or transmit data.
3.2 DRIVE-SELECT LATCH
Z30 and gates in Z24 and Z25 form an eight-bit latch for the selected
drive numbers, type (mini or standard), side number, density, and
reset.
Data on the data bus (low order byte with TEl, Inc. CPU-85 card)
enters the latch when the operating system executes an OUT instruction
to the FDC-3 address, with address bit A2 high. Bits Al and AO are
ignored.
3.3 FUNCTION-SELECT LOGIC
Ga tes in Z 9, Z24 and Z25 decode CPU commands to the FDC-3 to steer or
condition onboard logic to receive or transmit the proper data.
3.4 BIDIRECTIONAL BUS BUFFERS
Z28
and Z29 are four-bic bidirectional bus driver/receivers.
3-1

3.5 READ/WRITE CLOCK GENERATION
The Read/Write Clock Generator performs the dual function of (1)
Accurately separating incoming data and clocks in either FM mode
(single density) or MFH mode (double density); and (2) Supplying write
clocks for either recording mode.
This logic consists of a crystal-controlled Oscillator, Dividers,
Write-Data Delay Generator, multiplexer-controlled Buffers, and
Digital Phase-Locked Loop.
3.5.1
OSCILLATOR
R24, R25, Xl, and two sections of Z16 form a 16-~Hz oscillator. The
oscillator output clocks the Divider log~c.
3.5.2
DIVIDERS AND MULTIPLEXED BUFFER
Z12 divides the 16-MHz oscillator signal to generate 2, 4 and 8 MHz.
Z14 enables cne of the four buffers in Z13, steered by density ana
drive signals. The selected buffer passe~ the selected frequency --2,
4, 8, or 16 MHz-- to the Digital Phase-Lc'cked Loop.
3.5.3
WRITE-DA'I'A DELAY GENERATOR AND BUFFER
Z5 delays the Write Data signal one, three or five 16-MHz clock times
as required for write precompensation. Z14 enables one of the four
buffers in Z6, steered by Early and Late outputs from the 1791 device.
3.5.4
DIGITAL PHASE-LOCKED LOOP
Zl, Z2, Z4, ZlO, 211 and Z16 form a Digital Phase-Locked loop. This
circuit receives combined data and clock transitions from the drive
electronics and accurately separates the clock pulses from the data
pulses.
ZIA and Z2A
clock. Z2B
transition.
Clock.
synchronize incoming signal transitions with the FDC-3
and gates in Z10 output short pulses for each input
These pulses clock Zll and Z4 which output the Read
ZlB, Z2B, and buffers in Z16 and Z17 sel~ct the 1791 device clock.
3-3

~----,-----t
+
0.,. ... OUT
ttuHERS
-,
t+r1
It•1•
DATA ,-,r)-"'~'A·~('
r
SECiOA
~I
r-
TRACt(
K-
$TATUS
MEG FlE(~
REG REG REG
•iI
,
d;
I
.::; ......
i
L--
MAW READ
51.11' r
__ EG
:
:IAcU
W~~EO~S~T" 4-
!
1-1--
I,
.. ~ OPEC'OR
:,
ReL.IC.
i
rl,---C_"" '_0uc_ll---· -----J
~':'.Q---r-----I
-_ .... _----
--~._--
--~--
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--~':.._-
--~-
ro,
N1;:"u'i'4
·,,"'ftlFACf
(O",,"'F:lO ..
P, •
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-
WP
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O'$IC.
REAO'"
I",TEAF·CT
CO""TIlIO~
STEP
DIllie
EARLY
LoAT!,
MG
",0
'" T
FD1791 BLOCK DIAGRAM
Figure 3-2 1791 Device Block Diagraffi
~-4

3.6 1791 CONTROLLER
The 1791 Controller is an r~os LSI device that contains logic to select
a disk track, then reco!o data on that track or read data already
recorded.
The 1791 device (Figure 3-2) consists cf a buffered Data Register,
Data Shift Register, Sector Register, Command Register, Track-Number
Register, Status Register, CRC Logic, Address-Detect Logic
Arithmetic/Logic Unit (ALU), Computer-Interface Logic, and Drive-
Interface Logic.
3.6.1
DATA REGISTER
This bidirectional register receives data or commands from the CPU and
transmits data to the CPU.
3.6.2 DATA SHIF7 REGISTER
This register receives eignt bits of serial data from the drive, then
outputs it as one byte to the Dcta Regis~er; or receives a byte from
the Data Register and transmits it as serial data to the drive.
3.6.3
SECTOR REGISTER
This eight-bit register holes the address of the desired sector.
3.6.4
COMMAND REGISTER
This eight-bit register holds the command currently being executed by
the 1791 device. The device has 11 cOffiffiands of four types (Section
IV) •
3.6.5
TRACK-NUMBER REGISTER
This eight-bit register holds the number of the track over which the
Read/Write head is currently positioned. Step and Direction commands
from the Drive-Interface logic increment or decrement the register.
3.6.6
STA?US REGISTER
This eight-bit register holds drive status such as ready, write-
protected, etc.; and coremand-result status. Refer to Appendix A.
3-5

3.6.7
CRC LOGIC
Thi~ logic generates a unique 16-bi t chec.(-word for each data transfer
[rolil the: CPU, and records that word along with the data. When the date..
is read out, it again passes through the CRC logic. If the check-word
generated during the read operation does not match the recorded check-
word, the 1791 device enters a CRC error bit in its Status register
and stops the Read operation.
3.6.8
ADDRESS-DETECT LOGIC
This logic detects ID, dat~, or index marks during operation.
3.6.9
ARITHNETIC/LOGIC UNIT
The ALU increments or decrements registers as required.
3.6.10
COMPUTER-INTERFACE AND ;)RIVE-INT::RFACE LOGIC
The Computer-Interface logic rec2ives all control signals from the CPU
and selects register data flow accordingly. The Drive-Interface
logic processEs status signals f~om the disk drive and control signals
from the Computer-Interface logic to control data transfer to and from
the drive.
A Prograremed Logic Array (PLN stores the program that controls both
the Computer-Interfac~ and Drive-Interface logic blocks.
3.7
3.7.1
MISCELLANEOUS LOGIC
HEAD-LOAD DELAY
Z21 generates a noninal 40-millisecond delay pulse, timed by C18 a,.c.
R5, each time the 1791 device generates the Head-Load signal. This
pulse applied to the 1791 device's HLT input prevents any transfer
until the drive head settles on the diskette surface.
3.7.2 DRIVE-READY LOGIC
3.7.2.1 Miniature Drive
Z20 counts index pulses generated by the drive electronics each time
the diskette index-hole passes a sensor in the drive. Upon reaching
the desired number (Section 1.<;); Z20 outputs a RDY signal for the
1791 device.
3-7

3.7.2.2 Regular Drive
The drive electronics generates RDY/ or. interface connector pin 22
upon detection of the second index pulse after drive door closed.
Z26-4
A3
*
Z26-6
A4
*
Z26-10
AS
*
Z26-12
A6
*
Z26-14
A7
*
Ground
+5 VDC
\
1 I I 1 I
*-----------*-----------*-----------*-----------* I
1
I
*-----------*-----------*-----------*-----------*/
Figure 3-3 FDC-3 Card Address Jumpering, Wiring Side of Card Up
TABLE 3-2
FDC-3 ADDRESS JUMPER SELECTION
===================================
I I A7 I A6 I AS 1 A4 I
1-----1------1------1------1------1
o
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
o
c
o
o
o
o
o
o
1
1
1
1
1
1
1
1
o
o
o
o
1
1
1
1
o
o
o
o
1
1
1
1
J
o
1
1
a
)
1
1
oJ
o
1
1
o
a
1
1
o
1
a
1
a
1
o
1
o
1
a
1
o
1
a
1
===================================
*If A3 strapped high, the low order address byte varies from 8 to F;
if low, from 0-7.
3-8

3.8 JUMPER SELECTION OF VARIOUS FUNCTIONS
The FDC-3 card has jumper selection for address, interrupts, drive-
ready delay, and Write Fault.
The FDC-3 card leaves the factory with etched jumpers selecting these
functions for proper operation with the TEl, Inc. Disk Operating
System (T/DOS). Changing any of these jumpers may result in improper
T/DOS operation.
3.8.1
FDC-3 ADDRESS
Recall from SectiCin 3.1 that the basic FDC-3 address is XXOY to XXFY
(hex). Jumpers insE::rted in the matrix between Z26 and the card edge
connector (Figure 3-3) and the System software determine the specific
FDC-3 address, OY to FY.
The card leaves the factory wtl A7 conn ~cted to +5 VDC <logic 1> and
A6-A3 connected to ground (logic 0). This forms address 8X, where X
consists of A3 at logic 0 and A2 - AO software-selected from 0-7,
which results in a final address of 80 to 87.
To select a different address, refer ~o Table 3-2, determine the
address connection, c~refully cut the factory jumpers to Z26 (as
required), then solder jumpers from thE +5VDC or ground rows to the
226 inputs.
3.8.2 END-OF-COMMAND INTERRUPT
with the etched jumper just above 5-100 bus pin 9 intact, the 1791
device generates a VISI interrupt signal ~t the end of each command.
3.8.3 DATA REQUEST INTERRUPT
With the etched jumper just above pin 10 intact, the 1791 devicE::
generates aVI61 (Data Request) interrupt signal if (1) Data Register
full during Read, or (2) Data Register enpty during vlrite.
3.8.4
WRI'::'E FAUL'I'
If thE:: user's drive supplies a Write-Fault signal (WF/), connecting a
jumper between points "H" and "F" below the large signal-cable
connector causes the 1791 device to stop the Write operation and set
the Write-Fault status bit upon detectio~ of the Fault signal.
3-9

3.8.5
DRIVE-READY DELAY SELECTION
with the etched jumper (on back side of board) connected to Z20, pin
11 (Figure 3-4), the 1791 device receives a Ready signal after the
sixth diskette rotation (sixth index pulse received).
To select the fifth, seventh, or eighth rotation instead, turn the
board wiring side up, locate the group of empty holes shown in detail
(as asterisks) in Figure 3-4 (approximately 3n (7.5 cm) straight down
from left edge of large signal connector), cut the etched jumper, then
solder a jumper from the single hole to the hole above pin 10 for
selection of the fifth rotation, to the hole above pin 12 for
selection of the seventh rotation, or to the hole above pin 13 for
selection of the eighth rotation.
o0
Z20
o0
*
/
/
-------Etched
jumper
****
IIII
0000 0
10 11
12
13
0000 0
Figure 3-4 Drive-Ready Delay Jumper Selection, Wiring Side
3-10

SECTION IV
SOFTWARE CONSIDERATIONS
4.1 FDC-3 CARD
The FDC-3 card requires three programming steps: Drive Selection,
Drive Initialization, and Data Transfer. The TEl, Inc. Operating
System, T/DOS Version 2.0 (or higher), performs these functions as
required for program operation. Note that T/DOS Versions 2.0 - 2.XX
support amaximum of four diskette drives.
4.2 1791 DEVICE
The 1791 LSI device responds to 11 commands of four types. Type I
cowmands cause hea.d anG/or stepper motor action. Type II commands
read or write data fromlto a selected sector. Type III commands read
an address or data fron, i:l. track or write data onto a trock. The
single Type IV command controls the device's interrupt capabilities.
As stated for the FDC-3 card, T/DOS supplies these commands as needed
for program operation.
Refer to Appenaix A for a discussion oE 1791 device commonds ana
stc:.tus codes.
4-1

SECTION V
HARDWARE CONSIDERATIONS
5.1 DRIVE CONFIGURATION
Each drive in a TEl, Inc. Computer System must be physically
configured according to its System designation. Configuration occurs
during System checkout.
Drive selection during program operation is software-controlled.
5.2
5.2.]
SIGNAL-CABLE CONNECTIONS
REGULJl.R DRIVES
Table 5-1 sho\Vs signal connections tor regular drives <large
connector).
5.2.2
MINIATURE DRIVES
Table 5-2 sr,ows signal connee tions f( r miniaL. re driveE (small
connector).
5-1

TABLE 5-1
REGULAR DRIVE SIGNAL CO~NECTIONS
==========================================================
I Pin I FUNCTION I Pin I FUNCTION I
1-------1-------------- 1-------1------------------------1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I Ground
I Spare
1 Ground
I Write Fault
I Ground
I Track 44-76
1 Ground
I Spare
1 Ground
I Spare
1 Ground
INot Used
I Ground
I Side Select
I Ground
I In Use*
I Ground
IHead Load
I Ground
I Index
I Ground
I Ready
1 Ground
I Spare
I Ground
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Enable Drive Select 11
Ground I
Drive Select 2 1
Ground I
Drive Select 3 I
Ground I
Drive Select 4 1
Ground I
Direction 1
Ground I
St2P I
Ground I
Write Data I
Ground I
Write Gate I
Ground I
Spare I
Ground I
Write Protect I
Ground I
Raw Data I
Ground I
Separated Data I
Ground j
Se?arated Clock I
5-2
==============================================~======= =====
*Door Light

TABLE
5-2
XINIATURE
DRIVE SIGNAL
'::ONNECTION
===================================:=====================
Pin 1
FUNCTION I I
Pin 1
FUNCTION
I
-------1----------------1 1-------1--------------------1
1
IGrouna
I I 18 I
Direction
2
ISpare
1I
19 I
Ground
3IGround II
20 I
Step
4
ISpare I I 21
I
Ground
5IGround I
22 I
write Data
6
ISpare
1 23
I
Ground
7IGround I
24 1
Write Gate
8 IInd~x
1
25 I Ground
9IGround I
26
1
Track 0
10 IDr i ve
1 Select
I27 1
Ground
11
IGround I
28 1
vir i te
Protect
12
IDrive
2 Select
I 29
I Ground
13
IGrounCi I
30
I
Raw
Data
14 IDrive
3
Select
I 31 I
Ground
15
IGrounci I
32
I
Side
Select
16 IHotor On
I 33
IGround
17
IGroun(; I
34 I
=======~===;======.===~=;============================= ===
5-3

SECTION VI
USER REPAIR GUIDE
TEl, Inc. designed and built your FDC-3 Floppy-Disk Controller Card
for extreme reliability. Before returning the card for repair,
please check the following items:
1) Does power-supply fan run and memory-size prompt appear on
screen when System turned on and Operating System diskette
loaded into crive? If not, check computer AC connection
and fuse. TURN POWER OFF AND UNPLUG LINE CORD FIRST.
2) Is card seated properly? Turn power off, pull up Of.
ins10e edg~ of both card ejectors (Figure 6-1)
·simultaneously to unseat card, then press firmly back into
socket.
If card still does not function properly, unplug signal
cable(s), unseat card as described above, remove unseated
card carefLllly from Computer, then place card on a clean,
firnl surface and GENTLY burnish each contact on both sides
of the S-IOO bus edge connector with a pencil eraser. Do
not use a power eraser or an art gum eraser. Replace card
in Computer, then reconnect signal cable(s). Be sure to
seat both card and co~nector(s) firmly.
3) Is each diske~te-drive signal cable seated properly? Turn
power off, press firmly in on cable connector.
4) Does problem exist for one diskette only? If so, copy as
much material as possible from defective diskette to good
diskette and discar6 bad diskette.
5) In multidrive Syste~s, does problem exist for one drive
only? Check that motor in problem drive turns by looking
into drive wi~h door open.
If all above items check and FDC-3 card still aoes not function
correctly, please contact:
Custom~r Support Coordinator
TEl, Inc.
5075 South Loop East
HOLlston, TX 77033 USA
[phone]
Tv~: 910-881-3639
6-1