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Section
3-7LS
Operators
OPERATING
INSTRUCTIONS
Introduction
This section contains; a simplified
block
diagram
description, function
of
the
front
panel controls and
connectors, an operational
check-out
and familiarization
procedure, and a section devoted
to
the use and applica-
tion
of
the instrument. Service information
is
contained in
the Service Instruction manual.
FUNCTIONAL
BLOCK
DESCRIPTION
Functional
Block
Description
The 7L5
is
a swept
front
end spectrum analyzer with
selectable front-end
plug-in
modules that
permit
the user
to
obtain calibrated display
for
a number
of
different
impedances (i.e., 50 ohm, 600 ohm, etc.). The plug-in
module contains; selectable attenuation, the first mixer,
and an
input
buffer
selector that trades attenuation
for
IF
gain. Signal attenuation in the plug-in and gain
of
the IF
processing chain are
controlled
by a reference level logic
circuit
in the 7L5 which provides calibrated settings in
1 dB
or
10
dB
steps overa range
of
approximately 146
dB
(depending on the plug-in module). A simplified
block
diagram
is
shown in Fig. 3-1.
The input signal
to
the 7L5
is
mixed with thefrequency
of
the main oscillator and the IF
of
10.7 MHz
is
fed
to
and
amplified by the 10.7 MHz
IF
amplifier.
Sincethe7L5
input
frequency range is 0
to
5 MHz, the main oscillator
is
tuned
and swept from 10.7
to
15.7 MHz. The frequency
of
the
main
oscillator
is controlled by
two
secondary (A and B)
oscillators that use a synthesizer technique
to
tune and
phase lock their frequencies. The sweep frequency
con-
trol
circuit
drives the oscillators according
to
thesettings
of
front
panel DOT FREQUENCY and FREQUENCY
SPAN/DIV controls.
@
The 10.7 MHz IF is processed through bandpass filters
and amplifiers and then mixed with the
output
from a
10.450oscillator,
to
down-convert
the 10.7 MHztoan IF
of
250 kHz. Gain
of
the 250 kHz amplifier
is
controlled bythe
reference level logic
circuit
which establishes the amount
of
attenuation in the plug-in module and gain
for
the
250 kHz IF and Log amplifiers. The reference level
is
selectable in 1
dB
and
10
dB steps.
The 250 kHz IF signal
is
processed throughthevariable
resolution filter circuits
for
bandwidth selections
of
10 Hz
to
30 kHz. Thesignal
is
again amplified, detected, and the
video
is
sent through
amplifier
circuits that provide the
10
dB/div, 2 dB/div, and linear gain characteristics.
The video signal is then fed
to
the display processing
circuits where the signal
is
eitherstored and displayed,or,
if the storage mode
is
not
selected, the signal
is
passed
directly through the vertical
output
amplifier to the
mainframe circuit.
If
either
or
both the DISPLAY A
or
DISPLAY B latches are enabled, the signal
is
converted to
digital data, stored in A
or
B memory,then converted back
~
to
analog data and processed through the
output
amplifiers
to
the mainframe. The vertical information
is
digitized and stored at 512 horizontal address locations
across the screen. Therefore, the horizontal sweep infor-
mation
is
converted
to
digital data
for
storage, then
converted back to an analog signal
for
display. The
horizontal sweep ramp
is
processed the same
as
the
vertical signal. The vertical (video) information can be
averaged
or
peak detected.
3·1