Tektronix DD 501 User manual

Tektronix, Inc.
P.O. Box 500
Beaverton, Oregon
070-1818-01
Product Group 75
IbktfDnix-
COMMITTED TO EXCELLENCE
PLEASE CHECK FOR CHANGE INFORMATION
AT THE REAR OF THIS MANUAL.
INSTRUCTION MANUAL
97077 Serial Number
First Printing SEP 1974
Revised APR 1982

|Gopynght ©1974, t975 Tektironix, Inc/7VII rights reserv^d/^'
iContents of this publcatfon may not be reproduced in
Iany forrh withoutthe written permission of Tektronix, Inc.
Products of Tektronix, inc. and its Subsidiaries are
;• covered by arid f^eign patenta and/or pendBng.-,
5patents. ''''*
'TEKTRONIX, TEK, SCo|&MOBlLE,:ind- ^are^
regtstf^, trademarks cl itektronix, Jnc. •TELECluiPr
registered trademark of Tektronix 'U.K.
,i4rolted. ;
.
Printed in U.S.A. Specification and price change
privileges are reserved.

DD 501
TABLE OF CONTENTS
Page
SECTION 1OPERATING INSTRUCTIONS
Installation 1-1
Signal Connection 1-1
Triggering 1-1
Counted Burst 1-2
FRONT-PANEL CONTROLS, CONNECTORS,
AND INDICATORS 1-4
SECTION 2SPECIFICATION
SECTION 3THEORY OF OPERATION
BLOCK DIAGRAM DESCRIPTION 3-1
CIRCUIT OPERATION
TRIGGER CIRCUIT 13-2
COUNTER CIRCUIT (SN B020530-up) 23-2
COUNTER CIRCUIT (SN B020529 and below) 23-5
POWER SUPPLY &TRIGGER INDICATOR 33-7
SECTION 4MAINTENANCE
FUSE REPLACEMENT 4-1
TABLE 4-2. Rear Connector Pin Assignments 4-1
REPACKAGING FOR SHIPMENT 4-2
SECTION 5PERFORMANCE CHECK/CALIBRATION
PRELIMINARY INFORMATION 5-1
Test Equipment Required 5-1
INDEX TO PERFORMANCE CHECK/CALIBRATION 5-3
START AND EVENTS INPUT 5-4
START AND EVENTS TRIGGERING 5-6
SECTION 6ELECTRICAL PARTS LIST
OPTIONS
SECTION 7DIAGRAMS
SECTION 8MECHANICAL PARTS LIST
CHANGE INFORMATION
REV CAUG 1979

Section 1—DD 501
OPERATING INSTRUCTIONS
INTRODUCTION
The DD 501 Digital Delay is an events counting plug-in unit designed for use in aTM 500-Series Power Module
mainframe. Separate external trigger signals are connected to the EVENTS and START INPUT connectors which allows up
to 99999 events to be counted. The plug-in unit counts apredetermined number of events, from 0to 99999, which are
selected by the front-panel thumb-wheel switches. The last event counted generates atrigger pulse to the DLY’D TRIG
OUT connector on the front panel.
Installation
The DD 501 is calibrated and ready for use when
received. It is designed to operate in any compartment of a
TM 500-Series Power Module only. To install, align the
upper and lower rails of the DD 501 with the Power
Module tracks and fully insert it. The front will be flush
with the front of the Power Module when the DD 501 is
fully inserted.
To remove the DD 501, pull on the latch at the bottom of
the front panel and the DD 501 will unlatch. Continue
pulling on the latch to slide the DD 501 out of the Power
Module. See Fig. 1-1.
Signal Connection
The DD 501 utilizes dc coupling into the EVENTS and
START trigger INPUT connectors. In general, probes
offer the most convenient means of connecting signals to
the DD 501 trigger inputs. Tektronix probes are shielded
to prevent pickup of electrostatic interference. A10X
attenuation probe offers ahigh input impedance and
allows the circuit under test to perform very close to
normal operating conditions. Also, a10X probe attenuates
the input signal 10 times.
Tektronix probes are designed to monitor the signal
source with minimum circuit loading. The use of aprobe
will, however, limit the maximum trigger frequency range.
To obtain maximum trigger bandwidth when using
probes, select aprobe capable of compensating the input
capacitance. Observe thegrounding considerations given
in the probe manual. The probe-to-connector adapters
and the bayonet-ground tip provide the best frequency
response.
In high-frequency applications, which require max-
imum overall bandwidth, use acoaxial cable terminated at
the output end in the characteristic impedance of the
source. To maintain the high-frequency characteristics of
the appiied signal, use high-quality, low-loss cable.
Resistive coaxial attenuators can be used to minimize
reflection if the applied signal has suitable amplitude.
High-level, low-frequency signals can be connected
directly to the external trigger inputs with short, unshield-
ed leads. When this method is used, establish acommon
ground between the DD 501 and the associated equip-
ment. The common ground provided by the line cords is
usually inadequate. If interference is excessive with
unshielded leads, use acoaxial cable or probe.
The front-panel output signal from the DLY’D TRIG
OUT connector should be connected to other equipment
with 50 ohm coaxial cable. The cable should determinated
in 50 ohms to maintain the risetime and falltime
characteristics of the signal.
Triggering
The input signal may have awide variety of shapes and
amplitudes, many of which are unsuitable as delay-
initiating triggers. For this reason, these signals are first
RELEASE
LATCH
:1818^0
Fig. 1-1. Release latch.
REV BAUG 1979 1-1

Operating Instructions—DD 501
applied to atrigger circuit where they are converted to
pulses of uniform amplitude and shape. This makes it
possible to start the delay with apulse that has aconstant
size, eliminating variations of the delay circuit operation
caused by changing input signals. The trigger controls
provide ameans to select the START and EVENT pulses at
any voltage level on either slope of the waveform.
The trigger SLOPE and LEVEL controls determine the
slope and voltage of the input signal where the trigger
circuit responds. Generally, the best point on awaveform
for triggering is where the slope is steep, and therefore
usually free of noise. Assuming asine-wave input
waveform, the steepest slope occurs at the zero-crossing
point. This is the point selected for triggering with the
LEVEL control is set to 0(center). Amore positive or
negative point on the waveform is selected as the LEVEL
control is rotated clockwise or counterclockwise respec-
tively from 0(toward +or -symbols on panel).
Before setting the trigger level, the desired slope
should be selected. Adjust the START LEVEL control to
the desired start trigger point. Then adjust the EVENTS
LEVEL control to trigger the events pulse either
simultaneously or after the start trigger pulse. The
relationship between start and events triggering is
monitored at the START and EVENTS TRIG VIEW con-
nectors.
Either LEVEL control can be preset to afixed voltage
level by adjusting the front-panel PRESET adjustment.
Rotate either LEVEL control fully clockwise (into the
detent), and set the PRESET screwdriver adjustment to
the desired triggering voltage level.
Counted Burst
This application permits preselecting the number of
output pulses from the PG 508. The event is initiated by an
externally applied signal or pulse, 5ns or longer. The time
duration of this signal or pulse has no effect on the output
from the PG 508.
To use this feature, place the DD 501 in the delay
interval mode of operation by moving the wire strap as
shown in Fig. 1-2 or changing connections, depending on
the DD 501 available. Connect the PG 508 and the DD 501
as shown in Fig. 1-3. Use ten inch or shorter cables for
interconnecting the two units to reduce delays.
Make certain the PG 508 TRIG/GATE IN input
impedance is set for 50 fi. Set the controls of the PG 508
for the desired output waveform with the PG 508 in FREE
RUN. Do not use the SQ WAVE mode. Place the PG 508 in
the +SLOPE, SYNC GATE mode and set the TRIG/GATE
LEVEL control at the 2o’clock position. Select EVENTS +
SLOPE, START -f SLOPE and place the EVENTS and
START LEVEL controls at the 2o’clock position on the
DD 501. The three TRIG’D lights on the DD 501 and the
TRIG’D/GATED light on the PG 508 will be off until the
DD 501 istriggered. Upon receipt ofatrigger, all lights will
illuminate. If not, check the setup and slightly adjust the
LEVEL controls as necessary.
Set the EVENTS DELAY COUNT on the DD 501 for one
less than the desired number of counts up to PG 508
repetition rates of about 20 MHz. See below for further
information. If necessary, asingletriggermay beobtained
by rotating the DD 501 START LEVEL control throughthe
0position, with no external trigger applied. Asingle trigger
may also be obtained by using the TEKTRONIX manual
(One Shot) Trigger Generator, Tektronix Part Number
016-0597-00. All other DD 501 and PG 508 operating
controls function normally.
"S’
2
^
I
WE
ifl
|gi
aQaEHui
00HQS0B.
Connect pins 1and 3for delay interval out for counted burst. Pins 1and 2provide normal delayed trigger out.
2044-29
Fig. 1-2. Location of trigger jumpers in DD 501 for selecting trigger or delay interval output.
1-2 REV BAUG 1979

Operating Instructions—DD 501
Fig. 1-3. PG 508-DD 501 Interconnections for counted burst operation.
Due to propagation delays in the PG 508, DD 501 and
the interconnecting cables, one or more pulses in addition
to the desired number are generated when the PG 508
repetition rates are set between 20 MHz and 50 MHz.
These extra pulses are consistent for any given frequency
irrespective of the desired EVENTS DELAY COUNT
setting. To determine the number of extra pulses for a
given PG 508 period, set the PG 508 and the DD 501
controls as previously described. Now adjust the PG 508
TRIG/GATE LEVEL or the DD 501 EVENTS LEVEL forthe
same number of extra pulses at DD 501 EVENTS DELAY
COUNT setting of zero and nine.
Fig. 1-4. Typical propagation delays using PG 508 with DD 501 in counted burst mode at 50 MHz repetition rate.
REV BAUG 1979 1-3

Operating Instructions—DD 501
FRONT-PANEL CONTROLS,
CONNECTORS, AND INDICATORS
NOTE
See Fig. 1-3 for location and brief description of
front-panel controls, connectors, and indicators.
EVENTS DELAY COUNT Switch
The EVENTS DELAY COUNT switch is a5decade,
digital readout switch that increases or decreases the
count at which adelayed pulse will occur. This switch
selects the number of events to be counted. The delay
count is displayed on the front-panel switch readout. The
DLY’D TRIG OUT signal is delayed 1count more than the
EVENTS DELAY COUNT switch setting: that is, aswitch
setting of 00000 will count 1event pulse, or aswitch setting
of 99999 will count 100,000 event pulses to produce a
DLY’D TRIG OUT pulse.
INPUT Connectors
Individual front-panel connectors are provided for
connecting the external trigger signals to the EVENTS and
START trigger preamplifiers.
EVENTS and START SLOPE Switches
Determine the amplitude point on the trigger signal at
which the circuit triggers. In the fully clockwise detent
position, the circuit triggers at the amplitude point on the
trigger signal selected by the PRESET screwdriver adjust-
ment.
LEVEL IN/OUT Connectors
Individual front-panel pin jacks are provided to monitor
the EVENTS and START dc level at which the triggering
occurs.
EVENTS TRIC’D Indicator
Provides avisible indication that the Events circuit has
received atrigger, and that an adequate trigger signal is
applied.
START TRIC’D Indicator
Provides avisible indication that the Start gate circuit
has received atrigger, and is open, ready for the events
count to begin.
RESET Pushbutton
Afront-panel RESET button Is provided to clear the
EVENTS counter and reset the START circuit. The next
START pulse will restart the EVENTS count at 00001 .The
RESET pushbutton allows the operator to reset the
counter and start circuit when in longterm count cycles or
when afalse trigger occurs.
1-4 REV BAUG 1979

Operating Instructions—DD 501
POWER. Pilot Light indicates power
applied.
TRIG'D. Indicates EVENTS circuit has
received atrigger.
SLOPE, Selects EVENTS trigger
polarity.
LEVEL. Selects the amplitude point
where the EVENTS circuit triggers.
PRESET. Allows trigger point to be
preset (LEVEL clockwise in detent).
LEVEL IN/OUT. Provides an output to
monitor the dc level at which the
EVENTS trigger occurs.
INPUT. Provides ameans of connecting
the external trigger signal to the
EVENTS trigger preamplifier.
TRIG'D. Indicates adelayed trigger
output has occured.
DLY'D TRIG OUT. Provides an output
of the delayed trigger pulses.
[
[
[
[
[
[
[
[
EVENTS DELAY COUNT. Selects
number of events to be counted.
RESET. Restarts count cycle.
TRIG'D. Indicates START gate
triggering.
SLOPE. Selects START trigger polarity.
LEVEL. Selects the amplitude point
where the START circuit triggers.
PRESET. Allows trigger point to be
preset (LEVEL clockwise in detent).
LEVEL IN/OUT. Provides an output to
monitor the dc level at which the START
trigger occurs.
INPUT. Provides ameans of connecting
the external trigger signal to the START
trigger preamplifier.
TRIG VIEW. Allows viewing of shaped
trigger pulses to START latch circuit.
TRIG VIEW. Allows viewing of shaped
trigger pulses to EVENTS counting
circuit.
1S18-7A
Fig. 1-5. DD 501 front panel controls and connectors.
@AUG 1979 1-5

Operating Instructions—DD 501
TRIG VIEW Connectors
Individual front-panel probe-tip connectors are
provided for monitoring the EVENTS and the START
trigger pulse waveforms. The TRIG VIEW output signals
are arepresentation of the input trigger signals repetition
rates. The TRIG VIEWoutput pulse width is determined by
the input waveshape and the triggering voltage level. For
example, the sinewave EVENTS INPUT signal, triggered
at the amplitude point shown in Fig. 1-6, produces an
output trigger width of 5microseconds. Consequently,
varying the trigger amplitude point on the input waveform
will vary the output pulse width proportionally.
DYL’D TRIG OUT Connector
Provides ameans of applying the shaped delayed
trigger pulsesto associated equipment. Output signals are
generated as positive-going rectangular pulses coinci-
dent with the end of the delay interval. The DLY'D TRIG
OUT pulse width will be identical to the Schmitt-trigger
pulse width, which can be monitored at the front-panel
TRIG VIEW connector.
The display shown in Fig. 1-7 illustrates the relationship
between the EVENTS INPUT signal, TRIG VIEW pulse,
and the DLY’D TRIG OUT pulse, with the EVENTS DELAY
COUNT switch set at 00002.
DELAYED TRIG’D Light
Provides avisible indication when adelayed trigger
output has occurred.
Fig. 1-6 Delayed output pulse width vs. events input-signal Fig. 1-7. Time and pulse-width relationships between input and
trigger voltage level. output signals.
1-6 @AUG 1979

Section 2—DD 501
SPECIFICATION
INTRODUCTION
The following electrical characteristics are valid over the stated environmental range for instruments calibrated at an
ambient temperature of +20° Cto +30° C, and after a5-minute warmup unless otherwise noted.
Limits and tolerances given in the Supplemental Information column are provided for user information only, and
should not be interpreted as Performance Requirements.
TABLE 2-1
Electrical Characteristics
Characteristic Performance Requirement Supplemental Information
EVENTS and START
Input Resistance and
Capacitance
1MO paralleled with 20 pF (variable)
Slope +or —,selectable
Sensitivity 85 mV p-p minimum at 30 MHz; 120 mV
p-p minimum at 65 MHz.
Trigger Level Range -1.0 Vto +1.0 V
Frequency Response 0to 65 MHz
Pulse Width (minimum) 5ns
TRIG VIEW Output At least 0.5 VPermits viewing of all shaped triggers
Source Impedance 200 Qor less
Trigger LEVEL IN/OUT Monitor
Jack
Probe-tip jack—aliows monitoring
comparator voltage of preset or trigger
level to within 25 mV.
Source Impedance Approximately 1kQ
TRIG’D Indicator
EVENTS Visual indication of triggering
START Visual indication that start gate is open
LEVEL Controls
0Volt Trigger Level Within 30° of mechanical zero
START Pulse Lead Time Simultaneous or ahead of the EVENTS
pulse
Recycle Time 50 ns or less Paralleling START and EVENTS
INPUTS determines maximum -h N+1
frequency
REV. A, NOV 1975 2-1

Specification—DD 501
Table 2-1 (cont)
Characteristic Performance Requirement Supplemental Information
RESET Resets start gate and events counter
circuits
EVENTS
Deiay Count Range 0to 99999
Throughput Time 30 ns or less
Deiayed Trigger Out
Pulse Width (max) Up to 6ns greater than the events
pulse width
Amplitude At least 1Vinto 50 ohms From +0.8 to +2.2 Vinto 3TTL loads
(approximately 5mA)
Source Impedance Logic 1approximately 50 ohms
Logic 0approximately 200 ohms
TRIG’D Indicator Indicates trigger out
Physical Characteristics
Size Fits all TM 500-Series power module
plug-in compartments. (See Fig. 2-1.)
Weight 716.5 grams (1.58 pounds)
Environmental Characteristics
Refer to the specification for the associated power moduie.
2-2 REV. A, NOV 1975

Fig.
2-1.
DD
501
Dimensional
Drawing.
Specification—
DD
501

Section 3—DD 501
THEORY OF OPERATION
INTRODUCTION
This section of the manuai describes the circuitry used in the DD 501 Digitai Delay. The description begins with a
discussion of the instrument, using the block diagram shown in Section 7. Next, each major circuit is described, using the
biock diagram to show the relationship between stages in each major circuit. Detaiied schematics of each circuit are
located in the Diagrams section at the back of this manual; refer to these schematics throughout the foliowing circuit
description for specific electricai values and relationships.
BLOCK DIAGRAM DESCRIPTION
Trigger Circuit
The function of each biock in the Events trigger circuit
is identicai to the function of the Start trigger circuit,
therefore, only the Start portion of the Trigger circuit wiil
be discussed.
AStart trigger signai is connected from an externai
source to the Start INPUT connector J120. The Start
Trigger Preamp presents ahigh-impedance input and
iow-impedance output to the input trigger signai.
The iow-impedance output trigger from the Start
Trigger Preamp drives the Start Trigger Levei Com-
parator. The front-panel LEVEL control in the comparator
circuit selects adc reference point on the trigger
waveform. The dc reference voltage selected triggers the
Start Schmitt Trigger circuit. The front-panel SLOPE
switch selects the positive- or negative-going slope on the
Schmitt square-wave trigger for the dc reference point.
Counter Circuit
The first trigger pulse to reach the Start Trigger enables
the Least Significant Digit Counter circuit. This allows the
counter to start counting the events pulses from the
Events Delay circuit.
The EVENTS DELAY COUNT switch setting deter-
mines the number of events pulses to be counted. Assume
an EVENTS DELAY COUNT switch setting of 00010 in the
following discussion. The switch setting of 00010
programs the counters to 99989. After the first events
pulse the four most significant dig its are stored in the Most
Significant Digits Latch. The Most Significant Digits
Counter Reset generates a50 nanosecond pulse and
resets the Most Significant Digits Counters. After 10
events pulses have been counted, the counters will be set
at 99999. The eleventh events pulse transfers one count
through the Final Count Detector to the Dly’d Trig Output
Amplifier and resets the Least Significant Digit Counter.
The Final Count Detector resets the Most Significant
Digits Latch and the Start Trigger Gate. The counters and
latches are now reset to 99989, ready to begin another
count.
The Manual Reset circuitry allows the operator to clear
and reset all counters and latches' with afront-panel
switch during acount cycle.
Power Supply and Triggering indicator
The Start Trigger Lamp Multi is a50 millisecond
multivibrator which performs two functions. It allows the
START TRIG’D indicator to remain on long enough for
viewing during high-frequency start pulses and holds the
START TRIG'D indicator on whenever the Start Trigger
Gate is open.
The Events Delay circuit enables the Events Trigger
Lamp Multi (50 millisecond multivibrator) to drive the
EVENTS TRIG’D indicator.
The count output pulse from the Final Count Detector
is amplified in the Dly’D Trig’d Output Amplifier. The Dly’d
Trig’d Lamp Multi is a50 millisecond multivibrator that
enables the Dly’d Trig’d Lamp Driver to remain visible
during high-frequency pulse output signals.
The +5 Volt Regulator supplies power for all integrated
circuits and the POWER indicator.
The -15 Volt Regulator supplies power for all other
circuit functions.
REV. A. NOV 1975 3-1

Theory of Operation—DD 501
CIRCUIT OPERATION
Introduction
This section provides adetailed description of the
electrical operation and relationship of the circuits in the
DD 501 .The theory of operation for circuits unique to this
instrument is described in detail in this discussion.
Circuits which are commonly used in the electronics
industry are not described in detail. If more information is
desired on these commonly used circuits, refer to the
following textbooks:
Gordon V. Deboo, "Integrated Circuits and
Semiconductor Devices", McGraw-Hill, New York,
1971.
Lloyd P. Hunter (Ed.), "Handbook of Semiconductor
Electronics", third edition, McGraw-Hill, New York,
1970.
Jacob Millman and Herbert Taub, "Pulse, Digital,
and Switching Waveforms", McGraw-Hill, New York,
1965.
TRIGGER CIRCUIT ^
NOTE
The Events input and Start input Trigger circuits are
identical. Refer to the block diagram. Only the Start
Input Trigger circuit is described in detail
throughout the Trigger circuit discussion.
Start Trigger Preamp
Source followers Q128A, Q128B (matched FET’s) and
emitter follower Q130 compose this stage. Input signals
to the preamp are dc coupled with a1megohm input
resistance. Input protection diodes CR123 and CR126
clamp the gate of Q128A when the signal at the input
connector exceeds approximately +or -5 volts. The dc
level on the base of Q130 is set by Input Zero Set
adjustment R129. The trigger output of Q130 provides
drive to the base of trigger level comparator Q135.
Start Trigger Levei Comparator
Differential comparator Q135, Q140 and emitter
follower Q160 compose this stage. Trigger signals from
Q130 drive the base of Q135. Adc reference voltage,
established by divider network R166, R167, R168, and
R169, is fed through LEVEL control R170(orwith R170set
fully clockwise into detent, through PRESET control
R175) to the base of emitter follower Q160. The output of
Q160 drives the base of Start Trigger Level Comparator
Q140. The dc reference voltage level at the base of Q140
determines the dc voltage point on the signal at the base of
Q135 where the Start Schmitt, U144B, will generate a
trigger. The LEVEL in/out pin jack allows the dc trigger
point to be monitored externally.
Start Schmitt Trigger
Push-pull Schmitt Trigger U144B comprises this stage.
Trigger signals are coupled from Q135 and 0140 to pins 9
and 10 of U144B. Input sensitivity (hystersis) is establish-
ed by resistor pairs R136, R144, R142, and R146. Resistors
R144 and R146 provide feedback for U144B. The output
from Schmitt trigger U144B provides drive to the inputs of
slope selectors U144A and U144C.
Slope Selector
Signal gates U144A and U144C compose this stage. Pin
11 of U144A supplies aHI state signal to SLOPE switch
S170. The minus slope output from pin 2of U144A will
occur only when pin 4of U144A is at aHI state. The plus
slope output from pin 15 of U144C will occur only when
pin 13 of U144C is at a HI state.
The positive output signals from U44A and U44C drive
the Events Trigger Deiay circuit, pins 6and 7of U280B (SN
B020530-up: Count Gate circuit, pin 5of U273).
The positive output signals from U144A and U144C
drive the Start Trigger Gate (pin 6of U230A).
The TRIG VIEW connectors allow viewing of trigger
outputs from the SLOPE switch.
COUNTER CIRCUIT ^
(SN B020530-UP) ^
Block Description
As shown in Fig. 3-1, the method used to count Events
is to pre-load the 9’s complement of the desired event
number into aset of counters, then increment the
counters until each counter contains a9. As an example, if
it is desired to provide adelayed trigger output at the
4,512th Event after the selected Start pulse, the
thumbwheels are set to 451 2, but the BCD output from the
thumbwheels into the counters would be 99999 —04512 =
95487.
Three things are necessary to start the counters
operating; aStart pulse, an Event pulse, and the RESET
button must be pressed. Once the counters have been
started, anew count cycle is initiated on the first Start
pulse after the counters have reached the desired count.
3-2 REV. A, NOV 1975

Theory of Operation—DD 501
1818-13
Fig. 3-1. Counter Control Block Diagram.
When the RESET button is pressed, the Load Strobe
circuitry goes active and loads the thumbwheel outputs
into the four MSD counters. Pressing RESET also ac-
tivates the Counter Control circuitry to the extent that the
Counter Advance circuitry is activated, but the LSD load
gates are not activated on the first count! ng cycle after the
RESET button is pressed. During the first counting cycle,
the number existing in the LSD counter at the time the
RESET button is pressed is repeatedly incremented and
the overflows increment the four MSD counters until the
count in the MSD counters is9999. Atthat point, the 99999
Detector circuitry inhibits any more overflows from the
LSD counter to the MSD counters. The MSD thumbwheel
outputs are now re-loaded into the MSD counters. The
LSD counter continues to count Events until its count
reaches 9; at this point the 99999 Detector circuitry signals
the Counter Control circuitry to activate the LSD Load
Gates to load the proper LSD. Thus, during the first
counting cycle, the Delayed Trigger output can be off by
as much as8events (except instruments SN B022222and
above, which will have no error inthefirst counting cycle),
but at the end of the first counting cycle after the RESET
button is pressed, the correct number is loaded into the
LSD counter and all following counting cycles will deliver
adelayed trigger pulse when the desired triggering event
is reached.
Logic Description
When the RESET button is pressed, flipflop U230A (see
Fig. 3-2) is reset and the lowfrom its Qoutput inhibits AND
gate U273A. Nothing more happens until aStart pulse is
received at the clock input of U230A. When the start pulse
is received, U230A sets with its Qoutput going high. AND
gate U210B remains inhibited because the 99999 Detector
output from U21 OC is low, soflipflop U230B and the rest of
the LSD Load circuitry remains inhibited during the first
counting cycle after the RESET button is pressed.
However, note that when U230A is set by the Start pulse,
AND gate U273A is activated on each Event pulse and
increments LSD counter U271 through AND gate U273B
as long as 99999 is high (99999 remains high until all the
counters are incremented to 9, or 1001 in BCD). Thus,
during the first counting cycle after the RESET button is
pressed, the Counter circuitry is incremented, but LSD
Counter U271 does not get loaded with the 9’s comple-
ment from the LSD thumbwheel. The first count cycle can
be off by as much as 8counts (except instruments
SN B022222 and above, which will have no error in thefirst
count cycle).
At the end of the first count cycle, the 99999 Detector
activates AND gate U210B pin 6(U230A has remained set
since the Start pulse was received and is holding ahigh on
U210B pin 7). With both of its inputs high, U210B is
activated and the high from its output on pin 3puts ahigh
on the Dinputs of flipflops LI230B and U274. When the
next Event pulse arrives, both flipflops set. The Qoutput of
U230B clocks flipflop U232B, which sets. The Qoutput of
U274 resets U230A, and inhibits U210B. At the same time,
the Qoutput of U274 causes U274 to reset itself. The
REV BJAN 1980 3-3

Fig.
3-2
Counter
Control
Logic
Diagram
Ca)
FROM
THUMBWHEELS
START FROM
U144A DIAG
SA QA
SB LSD
^10
COUNTER
SC
U271
SD
>CQO
:
|9
m
<
>
z
o
<
Theory
of
Operation—
DD
501

Theory of Operation—DD 501
instant that the Event pulse goes low, U230B is reset by its
own low Qoutput and the low Event signal, through NAND
gate U240B.
When flipflop U232B is set by an Event pulse as
explained in the preceding paragraph, it promptly resets
itself with the high from its Qoutput. As it resets, the
positive-going edge from its Qoutput sets flipflop U232A,
which, in turn, activates the LSD Load gates in U272.
U232A promptly resets itself with its own Qoutput, but has
remained set long enough to load the LSD counter.
With the arrival of the second Start pulse, flipflop
U230A again sets and enables AND gates U273A and
U273B to pass the Event pulses to the LSD counter. This
counting cycle and all following cycles (until RESET is
again pressed) starts with the correct 9’s complement
loaded Into the LSD counter.
When the count in the LSD counter reaches lOOOa.the
output on pin 2of U271 goes high (see Fig. 3-2). The high
from U271 pin 2is inverted to alow by U215D and is
applied to one input of OR gate U215C. Since the 9’s
decoder has not detected all 9s, its output is high, which
causes pin 12 of U240C to be low; pin 13 of U240C is held
low by flipflop U215A/B at this time. Therefore, the other
input to U215C is alow from U240C, so the output of
U21 5C goes low and biases transistor Q280 on. The output
of U271 pin 2remains high for 2Events, then goes low; the
resulting negative-going signal at the collector of Q280
increments U265, the 10‘ counter.
As each counter overflows, it increments the next.
When the count reaches 99999, the output of U290 pin 8
goes low. The low from U290 causes the output of OR gate
U200 to go low and set flipflop U340B. The Qoutput of
U340B goes low and re-loads the thumbwheels into the
four MSD counter. (After adelay determined by C204,
transistor Q205 resets U340B.) The low from U290 is also
inverted by Q290 and applied through inverter U240D to
one input of NOR gate U240A. With lows on both its inputs,
the output of U240A pin 2goes high and resets the flipflop
consisting of U215A and U215B. The output of U215A pin
2goes high and (through OR gate U240C) activates AND
gate U210A. The output of U210A pin 2activates
AND/NAND gate U210C, which firstly inhibits U273 and
stops the Events from incrementing the LSD counter, and
secondly enables AND gate U210B. U210B Is now ac-
tivated and the LSD is re-loaded as previously explained.
When U210B is activated, it puts ahigh on the Dinputs
of U230B and U274. U274 resets U230A and thereby
removes the activating input from U210B. The Qoutput of
U230B causes the LSD from the thumbwheels to be loaded
into U271 as previously explained. The Qoutput of U230B
activates negative-input NAND gate U240B, whose output
resets the flipflop consisting of U215A and U215B. The
output of U240B also resets U230B.
With the counters re-loaded, the output of 99999
Detector U290 goes high. The high from U290, after
inversion by Q290, removes the activating inputs from OR
gate U240C and AND gate U210A. As aresult, the inverted
output of U210C goes high and enables U273D to pass
Event pulses to increment the LSD counter. With the
arrival of the next Start and Event pulses, AND gates
U273A and U273D are again activated and pass the Event
pulses to increment the LSD counter. Fig. 3-3 is atiming
diagram of the events that occur during the processing of
acount.
COUNTER CIRCUIT ^
(SN B020529 and below)
start Trigger Gate
Flipflop U230A comprises this stage. AHI state at pin 4
of U230A produces aHI on pin 3and disables counter
U270. Aplus trigger at pin 6of U230A produces aLO on
pin 3, thereby enabling counter U270 and inverter Q330.
Events Delay
Inverter U280B, NOR gate U280A and OR gate U280C
compose this stage. Positive-going triggers from U44A or
U44C drive pins 6and 7of U280B. A LO from pin 3of
U280B drives pin 4of U280A and inverter Q320. Pin 5of
U280A is normally LO and is driven HI during counter
reset. When pin 4of U280A is LO, pin 12of U280C is driven
HI allowing the HI output from pin 9to enable U240B,and
U270 starts counting.
The overall delay through this stage is approximately 6
nanoseconds to ensure that the start trigger has occurred
before the events are counted.
Least Significant Digit Counter
Programmed decade counter U270 comprises this
stage. Pins 7, 10, and 13 determine the operation of the
counter: pin 7LO to preset, pin 10 LO to enable counting,
and pin 13 (during apositive transition) to initiate acount.
The front panel thumbwheel switch, S410E, loads the
program input to pins 5, 6, 11, and 12 with a9’s
complement In binary coded decimal form. The 9's
complement of anumber can be defined as the value that
must be added to the number to yield 9. For example, the
9’s complement of 7is 2. When at a9count, pins 3and 1
4
of U270 yield HI state outputs.
REV. A, NOV 1975 3-5

Fig.
3-3.
Counter
Control
Timing.
U
cn
U230A pin 2
(derived from
START trigger.)
U44A pin 2
(derived from
EVENT trigger.) _n_n
COUNT BEGINS AT 99988 89
U271 pin 12
(CLOCK)
U272 pin 2
(8 BIT)
U271 pin 15
(1 BIT)
U240 pin 9
(99990 detected)
U210A pin 2
90
U210C pin 15
U210C pin 9
(99999 detected)
U210B pin 3
U230B pin 15
(pin 14 processed
as OUTPUT pulse.)
U274 pin 2
U232B pin 15
U232A pin 2
1818-15
Theory
of
Operation—
DD
501

Theory of Operation—DD 501
Least Significant Digit Detector
AND gate U210C, an AND gate with an inverting output
compose this stage. This stage detects only the BCD 9
count from the output of counter U270. When the most
significant digits have all been counted, or there are none
to be counted, pin 4of U210A is driven HI. At an 8count,
pin 5of U210A is driven HI, pin 2drives pin 13of U210C HI.
At a 9 count pin 12 is driven HI and pin 9drives pin 7 of
U270 LO, thereby enabling pin 7of the counter. Pin 15 of
U210C drives pin 6of U210B HI.
Carry Gate
Inverter U215D, OR gate U215C, and translator Q280
compose this stage. A LO state enables U215D and the
resultant HI output enables pin 13 of U215C. With pin 12of
U215C LO, pin 9drives the base of 0280 HI. With pin 12 HI,
the signals at pin 13 will not pass on to the base of 0280.
When the collector of 0280 goes LO, the negative-going
LO triggers pin 8of U265. 0280 takes the ECL level signal
from pin 9of U215C and provides an inverted, TTL
compatible signal for U265.
Most Significant Digits Counters
Four programmed decade counters, U250, U255, U260,
and U265 compose this stage. All four of the counting
devices use pin 1for preset, and pin 8to increment the
count on afalling (negative-going) LO. The front panel
thumbwheel switch, S410A, B, C, D, and Eprovides the
preset inputs to pins 4, 10, 3, and 11 with a9’s complement
in binary coded decimal form. The 9’s complement of a
number can be defined as the value that must be added to
the number to yield 9. For example, the 9’s complement of
7is 2. A9count produces aHI state on all pins 5and 12.
Most Significant Digits Detector
Eight-input NAND gate U290 comprises this stage.
This stage detects the BCD 9count from the most
significant digit counters. One or more inputs of U290 are
driven LO by the most significant digits counters will
produce aHI state at pin 8. When all inputs of U290 are
driven HI, pin 8of U290 enables pin 2 of U200 and sets the
base of 0290 to aLO state.
Most Significant Digits Counter Reset
OR gate U200, monostable multivibrator U340B, and
0205 compose this stage. When U290 drives pin 2of U200
LO, pin 3places pin 10 of U340B LO. AHi state pulse from
pin 9of U340B sets pin 1of U200 HI for approximately 50
nanoseconds, and the U200 50 nanosecond pulse sets pin
10 of U340B HI.
In the quiescent state, the collector of 0205 is HI with
pin 9LO and pin 8HI of U340B. Apositive-going trigger
applied to pin 11of U340B changes pin 8LO and pin 9HI.
With C204 charged positive at pin 8(when the change of
state occurs) the base of 0205 is placed at approximately
“5 volts. With pin 9HI, 0204 is charged positive through
R204 with atime constant of approximately 50
nanoseconds. When the junction of 0204 and R204
charges to about -1-0.6 volt, 0205 is turned on. This places
pin 13 of U340B LO, and resets U340B to the quiescent
state.
Most Significant Digits Latch
Translator 0290, inverter U240D, OR gate U240C, and
bistable multivibrator U240A, U215A, and U215B com-
pose this stage. Pin 8of LI290 goes low, thereby setting pin
12 of U240C and pin 10, 11 of inverter U240D HI. Pin 9of
U240C goes to aHI state and enables U215C and U210A.
Inverter U240D disables U240A with aLO state at pin 4of
U240A. The output of U240A enables U215B which drives
the output of U215B LO and the output of U215A HI. The
output of U215A will go LO as the input (pin 5) goes HI.
Final Count Detector
AND gate U21 OB, NOR gate U240B, and flipflop U230B
compose this stage. AND gate U210B is enabled by the HI
state output at pin 2of U230A and pin 15 of U210C,
thereby establishing aHI output to pin 10, U230B. Pin 6of
U240B is HI and pin 3is LO and remains LO until an events
trigger pulse drives pin 7HI and the positive-going pulse
triggers pin 11 of U230B. Flipfiop U230B output changes
state with the positive-going trigger to pin 11,driving pin
14 LO and pin 15 HI. The LO output to 0340 base is the
delayed trigger output signal. The HI output from pin 15of
U230B resets start trigger gate U230A. When the negative-
going transition of the events trigger pulse from U280C
drives pin 7of U240B LO, pin 3output drives pin 13 of
U230B HI, and resets U230B.
Manual Reset
Translator 0200, inverter U280D and buffer U210D
compose this stage. Front panel pushbutton RESET
switch S240 grounds LO for manual reset. ALO on pins 10
and 11of U280D produces areset pulse to pin 5of U280A,
pin 13 of U280C, pins 10 and 11 of U210D and the base of
0200. As the reset pulse from U280D drives the base of
0200 HI, the collector assumes aLO state. As the collector
changes to HI, the positive-going HI triggers pin 11 of
U340B, Pins 10 and 11 of U210D are driven HI and pin 14
resets U230A.
POWER SUPPLY &TRIGGER INDICATOR
Start Trigger Lamp Multivibrator
Inverter 0330 and monostable multivibrator U325B and
0335 compose this stage. When the base of 0330 is driven
3-7