Teledyne Lecroy PCI Express Gen4 OCP NIC 3.0 Interposer User manual

PCI Express®Gen4 OCP NIC 3.0
Interposer
User Manual and Quick Start Guide
Components
The interposer package includes the following components:
• PCI Express Gen4 OCP NIC 3.0 Interposer
• DC Power Adapter (+12V @ 5A)
• External latch bracket
• External lever
• User Manual and Quick Start Guide
(this document)
Introduction
Use this document for quick installation and setup.
Teledyne LeCroy’s PCI Express Gen4 OCP NIC 3.0 Interposer provides a quick and simple means for protocol analysis of
Gen4 OCP NIC 3.0 small form factor devices based on PCI Express (PCIe®) protocols. The Gen4 OCP NIC 3.0 Interposer
Card, used with the Summit T4 family of Protocol Analyzers, enables PCIe bus traffic between a host backplane and Gen4
OCP NIC 3.0 form factor device to be monitored, captured, and recorded for protocol analysis. The interposer supports data
rates of 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s, side band signals such as PERST#, WAKE# and SMBus (SMBCLK,
SMBDAT). The Gen4 OCP NIC 3.0 Interposer supports link widths up to x16.
PCI Express Gen4 OCP NIC 3.0 Interposer
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Inspect the received shipping container for any damage. Unpack the container and account for each of the system
components listed on the accompanying packing list. Visually inspect each component for absence of damage.
In the event of damage, notify the shipper and Teledyne LeCroy. Retain all shipping materials for shipper’s inspection.

Connections
Perform the following steps to connect the Interposer (see the image below):
1. Set the SW2 DIP switch to the desired positions to set the Host configuration according to the table below
(see Section “4” on page iii).
2. Slide the Gen4 OCP NIC 3.0 device into the device bracket and carefully push it into it’s mating connector on the Gen4 OCP NIC 3.0 Interposer.
Connect the Summit T416 Analyzer (or other compatible Teledyne LeCroy analyzer) to the interposer using two Gen4 Y cables
(PE021UCA-X).
3. Make sure the interposer is properly latched to the server. See Section “6” on page v.
4. Connect the analyzer to a host computer system using the USB port on the front panel of the Summit analyzer.
5. If not already done, install the PCIe Protocol Analysis software on the host machine.
6. Connect 12V DC using the AC adapter supplied with the interposer. Make sure that the AC adapter is powered on.
7. Power on the analyzer.
8. Launch the PCIe Protocol Analysis application, setup the appropriate recording options and start a recording. For more information see the Summit
T4 PCI Express Multi-Lane Protocol Analyzer User Manual, Gen4 OCP NIC 3.0 Interposer Configurations.
9. Install the Interposer into the host system connector.
10. Power on the host machine.
11. Use the PCIe Protocol Analysis application to monitor, record and view PCI Express traffic passing through the Gen4 OCP NIC 3.0 Interposer.
Note: For step 9, if testing for hot plug, run recording first from the PCIe Protocol Analysis software then install the interposer into the host system connector.
Make sure the interposer is properly latched to the server. See Section 6.
Connecting the PCI Express Gen4 OCP NIC 3.0 Interposer to a Summit T416 Analyzer
Gen4 Y Cable
Upstream
PE021UCA-X
Summit T416 Analyzer
OCP NIC 3.0 Host Slot
12V DC from
adapter supplied
External Clock
Inputs MMCX
(Optional Connection)
Device Under Test
(OCP NIC 3.0)
Lane Activity LEDs
SW2: Clock
Configuration
selection
SW1: DUT Power
Status LEDs
SW4: Link Width
selection switch
SW3: NC-SI PHY
Reset
Part of Bottom Cover
which holds DUT
Long Channel
Gen4 Y Cable
Downstream
PE021UCA-X
A
A
B
B
J8: Sideband
Signal header
A
C
B
D
To upstream connection
in the analyzer
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Configuration and other Switch Settings
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SW1: DUT Power Status LED on Interposer
This switch connects the DUT power Indication LEDs to the bus power. It is located near teh Lane Activity LEDS.
SW2: Clock Configuration Selection
The Host Type configuration used by the analyzer to record PCI Express traffic is configurable according to below table. DIP switches
and tables for the Host Type configuration are located on the front side of the interposer.
SW3: NC-SI PHY Reset Pushbutton SW4: Active Width Control Pushbutton
J8: Sideband Signal Header
Header
Pin
Number
Sideband
Signal
Name
Header
Pin
Number
Sideband
Signal
Name
Header
Pin
Number
Sideband
Signal
Name
Header
Pin
Number
Sideband
Signal
Name
1 BIF0# 6 PERST1# 11 PRSNTB0# 16 AUX_PWR_EN
2 SLOT_SMCLK 7 PERST0# 12 PRSNTB3# 17 NIC_PWR_GOOD
3 BIF1# 8 PERST3# 13 PRSNTA# 18 SMBRST#
4 SLOT_SMDAT 9 PERST2# 14 PRSNTB1# 19 PWRBRK0#
5 BIF2# 10 PRSNTB2# 15 MAIN_PWR_EN 20 WAKE#
SW1: DUT Power Status LEDs
ON LED Connected (Default)
OFF LED Disconnected
Note: This switch connects the DUT power indication LEDs to the bus power. In some systems with
Hot-Plug management the Power Indication LEDs on the interposer may prevent the host system
from turning ON bus power to the device, if this happens disconnect the LEDs using SW1 to allow
proper bus power operation.
SW2: Clock Configuration
1234HOSTTYPE
ON ON ON OFF SINGLE HOST x16 (Default)
ON ON OFF ON DUAL HOST x8
ON OFF ON ON QUAD HOST x4
OFF ON ON ON N/A
Pushbutton reset switch SW3 is used for NC-SI RBT
Interface PHY device reset.
Default position: Open
Pushbutton SW4 is used to turn off the terminations
and remove all loads on the unused interposer
receivers depending on the maximum number of
lanes to be analyzed. Press the pushbutton switch
(SW4) to move to the next active width as indicated
by the LEDs (next to the switch) on the interposer.
This is useful for devices that require terminations
not to be present in order to train to a lower link
width. The Active Width can be also controlled from
the PCIe Protocol Analysis.
Default position: x16
Note: Even though the Active Width may be lower than
x16, it may be possible that the Signal Detect LEDs for
higher lanes are ON if those lanes are transmitting signal.

Test Po in ts
Test Point Number Test Point Name Test Point Number Test Point Name Test Point Number Test Point Name
TP-1 3.3 V HOST TP-30 RBT_ARB_IN TP-40 LD#
TP-2 12V Host TP-31 12V FROM DC JACK TP-41 SLOT_ID1
TP-23 USBDATAP TP-32 SLOT_ID0 TP-42 DATA_OUT
TP-24 USBDATAN TP-34 CLK TP-43 DATA_IN
TP-27 3.65V FROM 12V TP-38 PHY MDC TP-44 RBT_ARB_OUT
TP-28 GND TP-39 PHY MDIO TP-49 3.3V IO
TP-29 GND
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Securing the Interposer to a Server
There are three different methods of securing the interposer to the server:
•Using the built in Internal Latch
•Using the External latch bracket
•Using the Lever latch
The Gen4 OCP NIC 3.0 Interposer can be used with servers designed with an internal latch mechanism. Just slide the
interposer in to the OCP slowly and the internal latch will lock in place. No External latch bracket or Lever latch needs to be
attached to the interposer. See diagram below:
External Latch Bracket Installation
For servers that provide a screw-on mechanism as a way to secure devices, an External latch bracket has been supplied
with the Interposer and can be attached as shown in the following diagrams:
Notches for Internal Latch
Attachment point for the bracket
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Insert the Phillips head screw through the bracket flange and attach it to the server. Slide the Interposer into the server. Then
align the External latch bracket’s thumb screw to the screw hole in the Interposer as shown below:
Insert and tighten the large thumb screw to secure the flange and Interposer to the server chassis. See diagram below.
Lever Latch Installation
If the server has been designed to use a Lever latch, a Lever latch has been supplied with the Interposer and can be attached
to the interposer as shown in the following diagrams. The first step to install the Lever latch is flip the interposer on its back
to access the bottom cover. Locate the top right screw on the bottom cover as shown in the following diagram.
Screw to attach
the flange to the server
Thumb screw to
attach the flange to
the interposer
Bottom cover Top Right
Screw

Remove the top right screw from the bottom cover along with a spacer that it was holding in place. Keep these parts close
by for re-installation with the Lever latch as shown in the diagram below:
Slide the Lever latch into position, along with the spacer. The spacer goes next to the PCB. The Lever latch goes between
the spacer and the bottom cover. Then install the Phillips head screw through the hole in the bottom cover, the hole in the
Lever latch and then through the spacer. Tighten the Phillips head screw. Then slide the interposer into the OCP slot with
the Lever latch mechanism loose. Once the interposer is in place, swivel the Lever latch in place and tighten the thumbscrew.
Lever latch
Spacer
Screw
Bottom cover
Lever Latch Installed

Trademarks and Servicemarks
Teledyne LeCroy, PCIe Protocol Suite, PCIe Protocol Analysis and
Summit T416 and Summit T48 are trademarks of Teledyne LeCroy.
All other trademarks are property of their respective companies.
Changes
Product specifications are subject to change without notice.
Teledyne LeCroy reserves the right to revise the information in this
document without notice or penalty.
Copyright
© 2020 Teledyne LeCroy, Inc. All rights reserved. Part Number: 932104-00 Rev A
This document may be printed and reproduced without additional permission, but all copies should contain this copyright notice.
Teledyne LeCroy Customer Support
Online Download
Periodically check the Teledyne LeCroy Protocol Solutions Group
web site for software updates and other support related to this
product. Software updates are available to users with a current
Maintenance Agreement.
Web: teledynelecroy.com/tm/software/PCIe
E-mail: [email protected]
Support: teledynelecroy.com/support/contact
Environmental Conditions
• Temperature: Operating 41° F to 104° F (5° C to 40° C)
• Temperature: Non-Operating -4° F to 140° F (-20° C to 60° C)
• Humidity: Operating 5% to 80% RH (non-condensing) @ <= 86° F or <= 30° C
• Humidity: Operating 50% max RH (non-condensing) @ 104° F or 40° C
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