Teledyne Lecroy PCI Express 3.0 Mid-Bus Probe Setup guide

PCI Express 3.0 Mid-Bus Probe
Installation and Usage Manual
ForusewithSummit™T3‐16 / T3‐8 / T34Systems
Generated: January8,2018,13:08

TeledyneLeCroy
ii PCIe3.0Mid‐BusProbeInstallationandUsageGuide
TeledyneLeCroyProtocolSolutionsGroup
TrademarksandServicemarks
TeledyneLeCroy,CATCTrace,PETracer,PCIeProtocolSuite,PCIeProtocolAnalysis,PETracerSummit,SummitT34,
SummitT3‐8,SummitT3‐16,UniversalProtocolAnalyzerSystem,UPAS,andBusEnginearetrademarksofTeledyne
LeCroy.
MicrosoftandWindowsareregisteredtrademarksofMicrosoftCorporation.
IntelandPentiumareregisteredtrademarksofIntelCorporation.
Allothertrademarksandregisteredtrademarksarepropertyoftheirrespectiveowners.
THESPECIFICATIONSANDINFORMATIONREGARDINGTHEPRODUCTSINTHISMANUALARESUBJECTTOCHANGE
WITHOUTNOTICE.ALLINFORMATION,EXAMPLESANDRECOMMENDATIONSINTHISMANUALAREBELIEVEDTOBE
ACCURATEBUTAREREPRESENTEDWITHOUTWARRANTYOFANYKIND,EXPRESSORIMPLIED.USERSAREFULLY
RESPONSIBLEFORTHEIRAPPLICATIONOFANYPRODUCTS.
THESOFTWARELICENSEANDLIMITEDWARRANTYFORTHEACCOMPANYINGPRODUCTARESETFORTHIN
INFORMATIONTHATSHIPPEDWITHTHEPRODUCTANDAREINCORPORATEDHEREINBYTHISREFERENCE.IFYOU
AREUNABLETOLOCATETHESOFTWARELICENSEORLIMITEDWARRANTY,CONTACTTeledyneLeCroyFORACOPY.
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Thisdocumentmaybeprintedandreproducedwithoutadditionalpermission,butallcopiesshouldcontainthiscopy‐
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PCIe3.0Mid‐BusProbeInstallationandUsageGuide iii
Contents
Chapter 1: Introduction...........................................................................................1
1.1 Interposers .............................................................................................................................. 1
1.2 Specialty Probes..................................................................................................................... 1
1.3 PCIe Protocol Suite Analyzer Hardware and Software ....................................................... 1
1.4 Multi-Lead / Mid-Bus Probes ................................................................................................. 2
1.4.1 Complete Kits .........................................................................................................................................3
1.4.2 Individual Components..........................................................................................................................4
Chapter 2: Probe Components ..............................................................................7
2.1 Probe Components................................................................................................................. 7
Chapter 3: Mechanical Design ...............................................................................9
3.1 Probe Footprints..................................................................................................................... 9
3.2 Mid-bus Probe Retention ..................................................................................................... 11
3.3 Probe Connection to Analyzer ............................................................................................ 13
3.4 Probe Keepout Volume ........................................................................................................ 13
3.5 Reference Clock Probe Attachment.................................................................................... 13
3.6 Daisy Chain Cable (for x16 applications) ........................................................................... 14
Chapter 4: Electrical Design.................................................................................17
4.1 Probe Loading Effect............................................................................................................ 17
4.2 Probed Signal Electrical Requirements.............................................................................. 18
4.3 Overview of Probe - Pin Assignments................................................................................ 18
4.4 Pin Assignments for Full-size Probe Connectors ............................................................. 19
4.5 Pin Assignments for Half-Size Probe Connectors ............................................................ 31

TeledyneLeCroy
iv PCIe3.0Mid‐BusProbeInstallationandUsageGuide
Chapter 5: Installation ..........................................................................................37
5.1 Installation Steps for Mid-Bus Probe Pod and Related Components.............................. 37
5.2 Reference Clock Cable......................................................................................................... 40
5.3 Daisy-Chain Cable ................................................................................................................ 41
Chapter 6: Dual Probe Pod Setup Using External Clocking .............................43
Chapter 7: Recording Traffic................................................................................45
Chapter 8: Ordering Information .........................................................................47
Chapter 9: Updates and Licensing ......................................................................51
9.1 Updating the Analyzer.......................................................................................................... 51
9.2 License Keys......................................................................................................................... 51
9.3 License Information.............................................................................................................. 51
Appendix A: How to Contact Teledyne LeCroy..................................................53
Appendix B: China Restriction of Hazardous Substances Table.....................55

PCIe3.0Mid‐BusProbeInstallationandUsageGuide 1
Chapter1
Introduction
TeledyneLeCroyoffersawidevarietyofwaystoconnectPCIExpressprotocolanalyzersto
productsundertest.Therearefourcommonmethods:
Interposers
SpecialtyProbes
PCIeProtocolSuiteAnalyzerHardwareandSoftware
Mid‐BusProbesandMulti‐leadProbes
1.1 Interposers
IftheproductusesastandardPCIExpresscardconnector,aninterposerisusedwhichis
insertedbetweenthePCIeCardandthecardslot.Theinterposertapsoffthedatatraffic
toallowtheanalyzertomonitorandrecordtrafficwithminimalperturbationofthe
electricalinterface.
1.2 Specialty Probes
Specialtyprobesareusedwithspecificcardconfigurations,andareusedinthesame
mannerasaninterposercard(infactaspecialtyprobeisaninterposercarddesignedfora
specificinterface).TeledyneLeCroysupportsarangeofspecialtyprobesincluding
ExpressCard,AMC,XMC,MiniCard,ExternalCable,ExpressModule,HPBladeServerand
SFF8639interfaces.
1.3 PCIe Protocol Suite Analyzer Hardware and Software
Designedfordevelopersandvalidators,theTeledyneLeCroySummit T3‐16™isaGen1/
Gen2/Gen3PCIExpressadvancedverificationsystem.
Byleveragingyearsofexperienceinprotocolanalysistoolsforemergingmarkets,
Summit T3‐16blendssophisticatedfunctionalitywithpracticalfeaturestospeedthe
developmentofPCI Express™IPcores,semiconductors,bridges,switches,add‐inboards,
andsystems.

TeledyneLeCroy Multi‐Lead / Mid‐BusProbes
2 PCIe3.0Mid‐BusProbeInstallationandUsageGuide
1.4 Multi-Lead / Mid-Bus Probes
Themulti‐leadprobeallowsindividualconnectionstoeachbustraceontheboard.Ifthe
producthasanembeddedPCIExpressbus(e.g.,abuswhichrunsbetweenchipsonthe
samecircuitboard),theneitheramid‐busprobeoramulti‐leadprobecanbeused.The
mid‐busproberequiresaconnectionfootprint(seebelow)tobedesignedintotheboard.
TheTeledyneLeCroymid‐busprobesare16‐channeldifferentialsignalprobesthatmeet
thedemandforhigh‐densitysignalaccess,accuracyandrepeatabilitywhileproviding
connector‐lessattachmenttothedeviceundertest.Theyarebaseduponthe
configurationthatwasinitiallyrecommendedintheIntelPCIExpressMid‐BusProbing
FootprintandPinoutRevision1.0documentdated8/05/03andthesubsequentrevisions.
Amid‐busprobeisoneofthetoolsthatcangreatlyhelpengineersdebuggingPCIExpress
buses.APCIExpressmid‐busprobingsolutionprovidesdirectprobingcapabilityofaPCI
Expressbusatawidthofupto16lanes.Toaccommodateamid‐busprobe,aspecialpad
layoutisrequiredtoexposethePCIExpressdifferentialpairsonthesurfaceofthetarget
board.(Seefigurebelow).
Figure 1.1: Board Trace Layout for a Mid-Bus Probe
AlthoughnotpartofthePCIExpressspecifications,theindustryhasdevelopedcommon
mid‐busprobefootprintsforPCIe1.0a,PCIe2.0andPCIe3.0applications(the"full‐size"
PCIe3.0footprintisshownontheright).ThesefootprintsaredesignedintothePCB.For
PCIe3.0applications,theprobecableattachmentusesaprobeconnectorwhichis
mountedthePCBasshowninthelowerimageonthebelow.
Figure 1.2: Full Width Connector for a Mid-Bus Probe
Theappropriatefootprintisrecommendedforusewithalltypesoftestequipment
includingprotocolanalyzers,logicanalyzersandoscilloscopes.Therequiredpadlayout
canbeinx4(half‐size),x8(full‐size)orx16(dualfull‐size)configurationsdependingon
themaximumnumberoflanesthatneedtobeprobed.Allfootprintsizessupportprobing
atreducedlanewidths(e.g.,x1)andatlanewidthsuptothemaximumfootprintsize.
TheillustrationFigure 2.1onpage 7showsthecompletedassemblyforprobinguptox8
configurations(forx16configurations,asecondY‐cable,probepod,headercable

PCIe3.0Mid‐BusProbeInstallationandUsageGuide 3
Multi‐Lead / Mid‐BusProbes TeledyneLeCroy
assemblyandprobeconnectorareused,butconnectionismadetothesame
Summit T3‐16analyzer‐seeFigure 3.8onpage 15).Asnoted,asinglefull‐sizeprobe
connectorsupportsuptox8lanewidthsbidirectional,butcanalsobeconfiguredto
supportx16unidirectional(ascanahalf‐sizeprobeconnectorsupportx8unidirectional).
Note: Thismanualdocumentsthemid‐busfootprintusedforPCIe3.0applications;theprobe
footprintsforPCIe1.0aandPCIe2.0arecoveredintheGen2Mid‐BusProbeUserManual.
TeledyneLeCroymakestwoversionsofmid‐busprobes,oneforPCIe2.0(2.5and5GT/s
datarates,alsoreferredtoas"Gen2")andoneforPCIe3.0(2.5,5and8GT/sdatarates,
alsoreferredtoas"Gen3").ThePCIe3.0mid‐busprobeisforusewiththeSummitT3‐16,
SummitT3‐8,SummitT34analyzers,andisdocumentedinthismanual.
ThePCIe3.0mid‐busprobe,inasimilarfashiontothePCIe1.0aandPCIe2.0
implementationsthatprecededit,isavailableintwoversions:afull‐sizeprobeandahalf‐
sizeprobe.Thefull‐sizeprobeforisshownonFigure 2.1onpage 7.Ithasafour‐strand
ribboncableandax16connectionheader.Ahalf‐sizeprobehasatwostrandribboncable
andax8connectionheader.
ThepartnumbersandcomponentsoftheTeledyneLeCroyPCIe3.0mid‐busprobesareas
follows:
1.4.1 Complete Kits
1. PE090ACA‐XPCIe3.0Mid‐BusProbeKit*
x8LaneWidth,Full‐sizeConnector,whichincludes:
PE010UCA‐X:iPassY‐Cable
PE087ACA‐X:PCIe3.0Mid‐BusProbePodwithpowersupply
PE057ACA‐X:PCIe3.0x8Mid‐busProbeCable
PE009UCA‐X:DaisyChainClockCable
PE014UCA‐X:ReferenceClockCable
PE047UIA‐X:Gen3Mid‐busProbeConnectorFull‐size
*Supportsuptox8bi‐directionallinkorx16uni‐directionallink(forusewith
twoSummitT34s,oneT3‐8oroneT3‐16analyzers).
2. PE094ACA‐XPCIe3.0Mid‐BusProbeKit*
x4LaneWidth,Half‐sizeConnector,whichincludes:
PE010UCA‐X:iPassY‐Cable
PE087ACA‐X:PCIe3.0x8Mid‐BusPodwithpowersupply
PE056ACA‐X:Mid‐busProbeCable(x4)
PE009UCA‐X:DaisyChainClockCable
PE014UCA‐X:ReferenceClockCable
PE054UIA‐X:PCIe3.0Mid‐busProbeConnectorHalf‐Size
*Supportsuptox4bi‐directionallinkorx8uni‐directionallink(forusewith
oneT3‐8oroneT3‐16analyzer).

TeledyneLeCroy Multi‐Lead / Mid‐BusProbes
4 PCIe3.0Mid‐BusProbeInstallationandUsageGuide
3. PE091ACA‐XPCIe3.0Mid‐BusProbeKit*
x4LaneWidth,Half‐sizeConnector,whichIncludes:
PE013UCA‐X:x4‐to‐x8StraightiPassCable
PE087ACA‐X:PCIe3.0x8Mid‐BusPodwithpowersupply
PE056ACA‐X:Mid‐busProbeCable(x4)
PE009UCA‐X:DaisyChainClockCable(secondcableforfutureexpandability)
PE014UCA‐X:ReferenceClockCable(secondcableforfutureexpandability)
PE054UIA‐X:PCIe3.0Mid‐busProbeConnectorHalf‐Size
*Supportsuptox4bi‐directionallinkorx8uni‐directionallink(forusewith
oneSummitT‐34analyzeronly).
TABLE 1.1: Full Size Probe Kit Capabilities
*:Forbidirectionalx16,twoPE090ACA‐Xkitsarerequired.
TABLE 1.2: Half Size Probe Kit Capabilities
1.4.2 Individual Components
1. PE087ACA‐XPCIe3Mid‐busPodwithThumbscrews
Nocables(forusewithSummitT3‐16orSummitT3‐8),includespowersupply.
2. PE056ACA‐XPCIe3Mid‐busProbeCablewithThumbscrews
G3x4probecable(Halfsize‐‐connectstoG3Mid‐busbox,forusewithSummit
T34,SummitT3‐16orSummitT3‐8)
3. PE057ACA‐XPCIe3Mid‐busProbeCablewithThumbscrews
G3x8probecable(Fullsize‐‐connectstoG3Mid‐busbox,forusewithSummit
T3‐16orSummitT3‐8)
4. PE038UIA‐XPCIeGen3x8DishforMid‐busProbe
5. PE047UIA‐XGen3Mid‐busProbeConnectorFull‐Size
PE090ACA-X PCIe 3.0 x8 Full-Size Probe Kit
x1 x2 x4 x8 x16
Uni Bidir Uni Bidir Uni Bidir Uni Bidir Uni Bidir
xxxxxxxxx*
PE094ACA-X / PE091ACA-X PCIe 3.0 x4 Half-Size Probe Kit
x1 x2 x4 x8 x16
Uni Bidir Uni Bidir Uni Bidir Uni Bidir Uni Bidir
xxxxxxx

PCIe3.0Mid‐BusProbeInstallationandUsageGuide 5
Multi‐Lead / Mid‐BusProbes TeledyneLeCroy
6. PE054UIA‐XGen3Mid‐busProbeConnectorHalf‐Size
7. PE010UCA‐XY‐CablefromMid‐busProbePodtoAnalyzer
8. PE013UCA‐Xx4‐to‐x8StraightiPassCable

TeledyneLeCroy Multi‐Lead / Mid‐BusProbes
6 PCIe3.0Mid‐BusProbeInstallationandUsageGuide

PCIe3.0Mid‐BusProbeInstallationandUsageGuide 7
Chapter2
Probe Components
2.1 Probe Components
Y‐CabletoAnalyzer
Gen3Mid‐BusProbePod
ProbeHeaderCableAssembly
ProbeConnector(mountedtoboard)
ClockingCable*(notshown)
Figure 2.1: Typical Full Size Probe Components
Y‐CabletoSummit
T3‐16orSummitT3‐8
Analyzers
(PE010UCA‐X)
Connect“A”Sideto
“UPSTREAM”and“B”
sideto
“DOWNSTREAM”
SummitT3‐16(shown),
SummitT3‐8,
orSummitT34Analyzers
Mid‐busProbePod
(PE087ACA‐X)
ProbeHeaderCable
Assembly
(PE057ACA‐X)
PCIeProbe
Connector
(PE047UIA‐X)

TeledyneLeCroy ProbeComponents
8 PCIe3.0Mid‐BusProbeInstallationandUsageGuide
Note: *TheIntel‐basedmid‐busfootprintspecificationonlysuppliesdifferentiallanesignalingand
groundreference.Shouldareferenceclock(RefClk)berequiredaseparateconnectionmustbe
made.TeledyneLeCroyPCIExpressprotocolanalyzerscanuseareferenceclockprobein
conjunctionwiththemid‐busanalysis.Eachmid‐busprobeisequippedwithoneclockprobe.
Themid‐busreferenceclockprobeisdesignedtofacilitatecapturingclocksignalsfromthe
systemboardinthetwoconfigurationsrecommendedbytheIntelguideline,i.e.,atapoffofan
existingclockoradedicatedclock.

PCIe3.0Mid‐BusProbeInstallationandUsageGuide 9
Chapter3
Mechanical Design
Thissectiondescribesfootprintdimensions,keepoutvolumes,andprobepin
assignments.
3.1 Probe Footprints
TheMid‐busProbeisfullycompatiblewiththestandardizedmid‐busfootprint
recommendedbytheIntelguideline,asshowninthefollowingfigures.
Full-Size Probe Footprint
Figure 3.1: PCIe Gen 3 Footprint

TeledyneLeCroy ProbeFootprints
10 PCIe3.0Mid‐BusProbeInstallationandUsageGuide
PCIe Gen 3 Full Size Keepout Volume
Figure 3.2: PCIe Gen 3 Keepout Volume
Half-Size Probe Footprint
Figure 3.3: PCIe Gen 3 Half Width Footprint
Note:All
dimensionsin
inches

PCIe3.0Mid‐BusProbeInstallationandUsageGuide 11
Mid‐busProbeRetention TeledyneLeCroy
PCIe Gen 3 Half Size Keepout Volume
Figure 3.4: PCIe Gen 3 Half Width Probe Keepout Volume
PCB Layout of Full Size PCIe Gen 3 Mid-bus Footprint
Figure 3.5: Full Size PCIe Gen 3 PCB Footprint
PCB Layout of Half Size PCIe Gen 3 Mid-bus Footprint
Figure 3.6: Half Size PCIe Gen 3 PCB Footprint
3.2 Mid-bus Probe Retention
ToprepareacircuitboardforPCIExpressmid‐busprobing,themid‐busfootprinthasto
belaidoutontothetargetsystemboardandaprobeconnectorhastobeattachedtothe
board.Attachmentoftheprobeconnectorissimpleandquick.Therearetwothrough‐
holescrewsandoneprotrusionkeyunderneaththeprobeconnector.Alignthekeyofthe
probeconnectorwiththekeying/alignmentholeinthemid‐busfootprintonthetarget
systemboard,andconnectthesmallscrews(supplied)throughthePCBandintothe
threadedholesontheundersideoftheMid‐busconnectormodule,andtightenthe
screwstoensuregoodcontactbetweenthecontactsoftheconnectorandthepadson
Note:All
dimensionsin
inches

TeledyneLeCroy Mid‐busProbeRetention
12 PCIe3.0Mid‐BusProbeInstallationandUsageGuide
thePCB.Themid‐busprobecanthenbeattachedtothetargetsystemboardthroughthe
probeconnectortoprovidemechanicalsupportforpin‐to‐pinalignment.Themid‐bus
cablehas2retentionscrewsthatconnecttotheprobeconnectortoholdtheprobein
place.
Cable to PCB Connector
Figure 3.7: Cable Connection to PCB Connector
Note: TheattachmentscrewssuppliedwillprovidesecureattachmentformostPCBdesigns.IfthePCB
isverythick,thescrewsmaynotbelongenoughtopassthroughthePCBandsecurelyattach
theMid‐busconnectormodule,inwhichcaseslongerscrewswillbeneeded.Thescrews
suppliedare5mmlong(McMaster‐CarrP/N91292A005),andlongerlengthscanbeobtained
directlyfromMcMaster‐Carrin6mm(91292A006),8mm(91292A008),orlongerlengthsas
needed.
TheprobeconnectorshouldnotbeconfusedwithaPCBconnectorbecauseitisnotpart
oftheelectricalcircuitsofeitherthetargetsystemortheprobe.
PCIe3.0probeconnectorscanbepurchasedthroughTeledyneLeCroy:
Full‐size:P/NPE047UIA‐X
Half‐size:P/NPE054UIA‐X

PCIe3.0Mid‐BusProbeInstallationandUsageGuide 13
ProbeConnectiontoAnalyzer TeledyneLeCroy
3.3 Probe Connection to Analyzer
Thebussignalscapturedbythemid‐busprobeareconnectedtoamid‐busprobepodfor
amplification.Thisreducestheloadimposedbythemid‐busprobeonthetargetsystem,
whileallowingalongercabletoattachtotheTeledyneLeCroyPCIExpressprotocol
analyzer.TheTeledyneLeCroyPCIExpressprotocolanalyzercantheninterpretthese
signalsforfulldecodingandprotocolanalysis.
3.4 Probe Keepout Volume
AswithanyconnectiontoaPCB,sufficientclearancemustbeallowedaroundthepoint
wheretheprobewillconnect.Thisisdefinedasthekeep‐outvolume,whichmustbekept
clearofothercomponentsmountedonthePCB.
Theprobekeepoutvolumesareshowninthediagramsin“ProbeFootprints”onpage 9.
3.5 Reference Clock Probe Attachment
ShouldSSCclockingbeusedinthesystemundertestorifthelinkvariesthebitrateby
morethan100MHz±300ppm(seeSection4.3.7ofBaseSpec3.0),areferenceclocktap
mayberequired.Theconnectionfromthereferenceclocktotheanalyzerisa3‐pin
header(1by3,0.050”centerspacing)whichisplacedontheclocksignaltransmission
lineoftheDUT.ThePE014UCA‐XReferenceClockCableprovidesathree‐pinmicrosocket
thatconnectsfromthisheadertotheCLKINportontheMid‐BusPod.
Ifthereferenceclockissampledbytappingoffanexistingclock,theheadershallbe
locatedontheexistingclocktransmissionline,whereahighimpedanceclockprobefrom
themid‐busprobeisconnectedwithnosignificantloadingeffects.Inthecaseofa
dedicatedclock,theheadershallbelocatedattheendofadedicatedclocktransmission
linewithouttermination,wherea50‐Ohmcableisconnectedandtheterminationforthe
clocksignalisprovidedonthemid‐busprobeboard.
Theconnectivityoftheclockheaderpinsfollowsthefollowingtable:
TABLE 3.3: Clock Header Pins
Note: Theanalyzerisnotsensitivetothepolarityofthereferenceclock.Therefore,theprobecanbe
pluggedontothepinheaderineitherorientation.
Thefollowing3‐pinheadercanbeusedforthereferenceclock:
SamtecPartNo:TMS‐103(VerticalOrientation)
Signal PinNumber
REFCLKp 1(or3)
Unused 2
REFCLKn 3(or1)

TeledyneLeCroy DaisyChainCable(forx16applications)
14 PCIe3.0Mid‐BusProbeInstallationandUsageGuide
Thereferenceclockiscapturedseparatelywithadedicatedprobecable.Consideringthe
possibilitythatoneclockmaybesharedbetweentwophysicallyseparatedmid‐bus
probes,eachmid‐busprobepodisequippedwithareferenceclockoutputport.The
referenceclockprobecancapturesignalsfromthetargetsystemorreceiveaduplicated
referenceclockfromanothermid‐busprobeboard.
3.6 Daisy Chain Cable (for x16 applications)
Asinglemid‐busprobepodcancapturetrafficonbuswidthsuptox8.Ifx16lanewidths
arerequired(e.g.,whenusingaSummitT3‐16Analyzerwithax16device),twoMid‐Bus
ProbePodsarerequired.
Inthisconfiguration,oneofthepodsisconnectedtotheDUTtotaptheReferenceClock
signal,andthesecondpodis"daisy‐chained"tothefirstpodusingthePE009UCA‐XDaisy
ChainCable.ConnecttheRefClockcabletotheCLKINportofthefirstpod,andconnect
theDaisyChainCablebetweentheCLKOUTportofthefirstpodandtheCLKINportof
thesecondpod.

PCIe3.0Mid‐BusProbeInstallationandUsageGuide 15
DaisyChainCable(forx16applications) TeledyneLeCroy
Mid-bus Probe Setup for x16 lane widths
(using Summit T3-16 Analyzer, Clocking Cable not shown)
Figure 3.8: Mid-bus Probe Setup for x16 lane widths

TeledyneLeCroy DaisyChainCable(forx16applications)
16 PCIe3.0Mid‐BusProbeInstallationandUsageGuide