ARM PrimeCelL PL320 Product manual

Copyright © 2003, 2004. ARM Limited. All rights reserved.
ARM DDI 0306B
PrimeCell®Inter-Processor
Communications Module (PL320)
Revision: r0p0
Technical Reference Manual
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ii Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B
PrimeCell Inter-Processor Communications Module (PL320)
Technical Reference Manual
Copyright © 2003, 2004. ARM Limited. All rights reserved.
Release Information
The following changes have been made to this document.
Proprietary Notice
Words and logos marked with ®or ™are registered trademarks or trademarks of ARM Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM Limited in good faith.
However, all warranties implied or expressed, including but not limited to implied warranties of
merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
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license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
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Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Change
19 December 2003 A First release
22 June 2004 B Reclassify to open access for r0p0
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ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. iii
Contents
PrimeCell Inter-Processor Communications
Module (PL320) Technical Reference Manual
Preface
About this manual .......................................................................................... x
Feedback ..................................................................................................... xiv
Chapter 1 Introduction
1.1 About the IPCM ........................................................................................... 1-2
Chapter 2 Functional Overview
2.1 Functional description ................................................................................. 2-2
2.2 Functional operation ................................................................................... 2-4
2.3 Examples of messaging ............................................................................ 2-18
Chapter 3 Programmer’s Model
3.1 About the programmer’s model ................................................................... 3-2
3.2 Register summary ....................................................................................... 3-6
3.3 Register descriptions ................................................................................ 3-12
Chapter 4 Programmer’s Model for Test
4.1 Scan testing ................................................................................................ 4-2
4.2 Test registers .............................................................................................. 4-3
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Contents
iv Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B
Appendix A Signal Descriptions
A.1 AMBA AHB signals ..................................................................................... A-2
A.2 Non-AMBA signals ..................................................................................... A-3
Glossary
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ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. v
List of Tables
PrimeCell Inter-Processor Communications
Module (PL320) Technical Reference Manual
Change history .............................................................................................................. ii
Table 2-1 Channel ID to interrupt mapping ............................................................................... 2-6
Table 2-2 Configuring number of mailboxes ........................................................................... 2-12
Table 2-3 Configuring number of interrupts ............................................................................. 2-14
Table 2-4 Configuring number of data registers ...................................................................... 2-16
Table 3-1 IPCM register summary ............................................................................................ 3-6
Table 3-2 IPCMxSOURCE Register bit assignments .............................................................. 3-12
Table 3-3 IPCMxDSET Register bit assignments ................................................................... 3-12
Table 3-4 IPCMxDCLEAR Register bit assignments ............................................................... 3-13
Table 3-5 IPCMxDSTATUS Register bit assignments ............................................................ 3-13
Table 3-6 IPCMxMODE Register bit assignments .................................................................. 3-14
Table 3-7 IPCMxMSET Register bit assignments ................................................................... 3-15
Table 3-8 IPCMxMCLEAR Register bit assignments .............................................................. 3-15
Table 3-9 IPCMxMSTATUS Register bit assignments ............................................................ 3-16
Table 3-10 IPCMxSEND Register bit assignments ................................................................... 3-17
Table 3-11 IPCMxDR0-6 Register bit assignments ................................................................... 3-17
Table 3-12 IPCMMISx Register bit assignments ....................................................................... 3-18
Table 3-13 IPCMRISx Register bit assignments ....................................................................... 3-18
Table 3-14 IPCMCFGSTAT Register bit assignments .............................................................. 3-19
Table 3-15 IPCMPeriphID0 Register bit assignments ............................................................... 3-20
Table 3-16 IPCMPeriphID1 Register bit assignments ............................................................... 3-21
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List of Tables
vi Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B
Table 3-17 IPCMPeriphID2 Register bit assignments .............................................................. 3-21
Table 3-18 IPCMPeriphID3 Register bit assignments .............................................................. 3-21
Table 3-19 IPCMPCellID0 Register bit assignments ................................................................ 3-22
Table 3-20 IPCMPCellID1 Register bit assignments ................................................................ 3-23
Table 3-21 IPCMPCellID2 Register bit assignments ................................................................ 3-23
Table 3-22 IPCMPCellID3 Register bit assignments ................................................................ 3-23
Table 4-1 IPCMTCR Register bit assignments ......................................................................... 4-3
Table 4-2 IPCMTOR Register bit assignments ......................................................................... 4-3
Table A-1 AMBA AHB common signals .................................................................................... A-2
Table A-2 AMBA AHB slave signals .......................................................................................... A-2
Table A-3 IPCM configuration signals ....................................................................................... A-3
Table A-4 IPCM interrupt signals .............................................................................................. A-3
Table A-5 Scan test signals ....................................................................................................... A-3
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ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. vii
List of Figures
PrimeCell Inter-Processor Communications
Module (PL320) Technical Reference Manual
Key to timing diagram conventions ............................................................................. xii
Figure 2-1 IPCM block diagram .................................................................................................. 2-2
Figure 2-2 IPCM integration in a multiprocessing system .......................................................... 2-3
Figure 2-3 Basic operation ......................................................................................................... 2-5
Figure 2-4 Mailbox interrupt mapping to IPCM interrupt outputs .............................................. 2-11
Figure 2-5 Configuration, messaging from Core0 to Core1 ...................................................... 2-18
Figure 2-6 Messaging from Core0 to Core1 ............................................................................. 2-19
Figure 2-7 Configuration, back-to-back messaging from Core0 to Core1 ................................ 2-20
Figure 2-8 Back-to-back messaging from Core0 to Core1 ....................................................... 2-21
Figure 2-9 Configuration, messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge ....
2-22
Figure 2-10 Messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge ................... 2-23
Figure 2-11 Configuration, Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1
2-25
Figure 2-12 Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1 .............. 2-25
Figure 3-1 IPCM register map .................................................................................................... 3-4
Figure 3-2 Mailbox0 register map ............................................................................................... 3-5
Figure 3-3 Interrupt0 register map .............................................................................................. 3-5
Figure 3-4 IPCMxMODE Register bit assignments .................................................................. 3-14
Figure 3-5 IPCMxSEND Register bit assignments ................................................................... 3-16
Figure 3-6 Mailbox status ......................................................................................................... 3-18
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List of Figures
viii Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B
Figure 3-7 IPCMCFGSTAT Register bit assignments .............................................................. 3-19
Figure 3-8 Peripheral Identification Register bit assignments .................................................. 3-20
Figure 3-9 PrimeCell Identification Register bit assignments ................................................... 3-22
Figure 4-1 IPCMTCR Register bit assignments ......................................................................... 4-3
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ARM DDI 0306B Copyright © 2003, 2004. ARM Limited. All rights reserved. ix
Preface
This preface introduces the PrimeCell Inter-Processor Communications Module
Revision r0p0 PrimeCell Inter-Processor Communications Module (PL320) Technical
Reference Manual (TRM). It contains the following sections:
•About this manual on page x
•Feedback on page xiv.
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Preface
xCopyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B
About this manual
This is the TRM for the Inter-Processor Communications Module (IPCM).
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This manual is written for hardware engineers who have some experience of using
ARM SoC design flow and methodology. Prior experience of the PrimeCell IPCM is
not assumed.
Using this manual
This manual is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an introduction to the IPCM and its features.
Chapter 2 Functional Overview
Read this chapter for a description of the major functional blocks of the
IPCM.
Chapter 3 Programmer’s Model
Read this chapter for a description of the IPCM registers and
programming details.
Chapter 4 Programmer’s Model for Test
Read this chapter for a description of the logic in the IPCM for functional
verification and production testing.
Appendix A Signal Descriptions
Read this appendix for details of the IPCM signals.
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