Arm Primecell pl320 Product manual

ARM DDI 0306B

PrimeCell®Inter-Processor

Communications Module (PL320)

Revision: r0p0

Technical Reference Manual

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PrimeCell Inter-Processor Communications Module (PL320)

Technical Reference Manual

Release Information

The following changes have been made to this document.

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mentioned herein may be the trademarks of their respective owners.

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holder.

The product described in this document is subject to continuous developments and improvements. All

particulars of the product and its use contained in this document are given by ARM Limited in good faith.

However, all warranties implied or expressed, including but not limited to implied warranties of

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such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to

license restrictions in accordance with the terms of the agreement entered into by ARM and the party that

ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Web Address

http://www.arm.com

Change history

Date Issue Change

19 December 2003 A First release

22 June 2004 B Reclassify to open access for r0p0

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Contents

PrimeCell Inter-Processor Communications

Module (PL320) Technical Reference Manual

Preface

About this manual .......................................................................................... x

Feedback ..................................................................................................... xiv

Chapter 1 Introduction

1.1 About the IPCM ........................................................................................... 1-2

Chapter 2 Functional Overview

2.1 Functional description ................................................................................. 2-2

2.2 Functional operation ................................................................................... 2-4

2.3 Examples of messaging ............................................................................ 2-18

Chapter 3 Programmer’s Model

3.1 About the programmer’s model ................................................................... 3-2

3.2 Register summary ....................................................................................... 3-6

3.3 Register descriptions ................................................................................ 3-12

Chapter 4 Programmer’s Model for Test

4.1 Scan testing ................................................................................................ 4-2

4.2 Test registers .............................................................................................. 4-3

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Contents

Appendix A Signal Descriptions

A.1 AMBA AHB signals ..................................................................................... A-2

A.2 Non-AMBA signals ..................................................................................... A-3

Glossary

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List of Tables

PrimeCell Inter-Processor Communications

Module (PL320) Technical Reference Manual

Change history .............................................................................................................. ii

Table 2-1 Channel ID to interrupt mapping ............................................................................... 2-6

Table 2-2 Configuring number of mailboxes ........................................................................... 2-12

Table 2-3 Configuring number of interrupts ............................................................................. 2-14

Table 2-4 Configuring number of data registers ...................................................................... 2-16

Table 3-1 IPCM register summary ............................................................................................ 3-6

Table 3-2 IPCMxSOURCE Register bit assignments .............................................................. 3-12

Table 3-3 IPCMxDSET Register bit assignments ................................................................... 3-12

Table 3-4 IPCMxDCLEAR Register bit assignments ............................................................... 3-13

Table 3-5 IPCMxDSTATUS Register bit assignments ............................................................ 3-13

Table 3-6 IPCMxMODE Register bit assignments .................................................................. 3-14

Table 3-7 IPCMxMSET Register bit assignments ................................................................... 3-15

Table 3-8 IPCMxMCLEAR Register bit assignments .............................................................. 3-15

Table 3-9 IPCMxMSTATUS Register bit assignments ............................................................ 3-16

Table 3-10 IPCMxSEND Register bit assignments ................................................................... 3-17

Table 3-11 IPCMxDR0-6 Register bit assignments ................................................................... 3-17

Table 3-12 IPCMMISx Register bit assignments ....................................................................... 3-18

Table 3-13 IPCMRISx Register bit assignments ....................................................................... 3-18

Table 3-14 IPCMCFGSTAT Register bit assignments .............................................................. 3-19

Table 3-15 IPCMPeriphID0 Register bit assignments ............................................................... 3-20

Table 3-16 IPCMPeriphID1 Register bit assignments ............................................................... 3-21

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List of Tables

Table 3-17 IPCMPeriphID2 Register bit assignments .............................................................. 3-21

Table 3-18 IPCMPeriphID3 Register bit assignments .............................................................. 3-21

Table 3-19 IPCMPCellID0 Register bit assignments ................................................................ 3-22

Table 3-20 IPCMPCellID1 Register bit assignments ................................................................ 3-23

Table 3-21 IPCMPCellID2 Register bit assignments ................................................................ 3-23

Table 3-22 IPCMPCellID3 Register bit assignments ................................................................ 3-23

Table 4-1 IPCMTCR Register bit assignments ......................................................................... 4-3

Table 4-2 IPCMTOR Register bit assignments ......................................................................... 4-3

Table A-1 AMBA AHB common signals .................................................................................... A-2

Table A-2 AMBA AHB slave signals .......................................................................................... A-2

Table A-3 IPCM configuration signals ....................................................................................... A-3

Table A-4 IPCM interrupt signals .............................................................................................. A-3

Table A-5 Scan test signals ....................................................................................................... A-3

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List of Figures

PrimeCell Inter-Processor Communications

Module (PL320) Technical Reference Manual

Key to timing diagram conventions ............................................................................. xii

Figure 2-1 IPCM block diagram .................................................................................................. 2-2

Figure 2-2 IPCM integration in a multiprocessing system .......................................................... 2-3

Figure 2-3 Basic operation ......................................................................................................... 2-5

Figure 2-4 Mailbox interrupt mapping to IPCM interrupt outputs .............................................. 2-11

Figure 2-5 Configuration, messaging from Core0 to Core1 ...................................................... 2-18

Figure 2-6 Messaging from Core0 to Core1 ............................................................................. 2-19

Figure 2-7 Configuration, back-to-back messaging from Core0 to Core1 ................................ 2-20

Figure 2-8 Back-to-back messaging from Core0 to Core1 ....................................................... 2-21

Figure 2-9 Configuration, messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge ....

2-22

Figure 2-10 Messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge ................... 2-23

Figure 2-11 Configuration, Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1

2-25

Figure 2-12 Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1 .............. 2-25

Figure 3-1 IPCM register map .................................................................................................... 3-4

Figure 3-2 Mailbox0 register map ............................................................................................... 3-5

Figure 3-3 Interrupt0 register map .............................................................................................. 3-5

Figure 3-4 IPCMxMODE Register bit assignments .................................................................. 3-14

Figure 3-5 IPCMxSEND Register bit assignments ................................................................... 3-16

Figure 3-6 Mailbox status ......................................................................................................... 3-18

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List of Figures

Figure 3-7 IPCMCFGSTAT Register bit assignments .............................................................. 3-19

Figure 3-8 Peripheral Identification Register bit assignments .................................................. 3-20

Figure 3-9 PrimeCell Identification Register bit assignments ................................................... 3-22

Figure 4-1 IPCMTCR Register bit assignments ......................................................................... 4-3

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Preface

This preface introduces the PrimeCell Inter-Processor Communications Module

Revision r0p0 PrimeCell Inter-Processor Communications Module (PL320) Technical

Reference Manual (TRM). It contains the following sections:

•About this manual on page x

•Feedback on page xiv.

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Preface

About this manual

This is the TRM for the Inter-Processor Communications Module (IPCM).

Product revision status

The rnpnidentifier indicates the revision status of the product described in this manual,

where:

rnIdentifies the major revision of the product.

pnIdentifies the minor revision or modification status of the product.

Intended audience

This manual is written for hardware engineers who have some experience of using

ARM SoC design flow and methodology. Prior experience of the PrimeCell IPCM is

not assumed.

Using this manual

This manual is organized into the following chapters:

Chapter 1 Introduction

Read this chapter for an introduction to the IPCM and its features.

Chapter 2 Functional Overview

Read this chapter for a description of the major functional blocks of the

IPCM.

Chapter 3 Programmer’s Model

Read this chapter for a description of the IPCM registers and

programming details.

Chapter 4 Programmer’s Model for Test

Read this chapter for a description of the logic in the IPCM for functional

verification and production testing.

Appendix A Signal Descriptions

Read this appendix for details of the IPCM signals.

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Preface

Conventions

Conventions that this manual can use are described in:

•Typographical

•Timing diagrams

•Signals on page xii

•Numbering on page xiii.

Typographical

The typographical conventions are:

italic Highlights important notes, introduces special terminology,

denotes internal cross-references, and citations.

bold Highlights interface elements, such as menu names. Denotes

signal names. Also used for terms in descriptive lists, where

appropriate.

monospace

Denotes text that you can enter at the keyboard, such as

commands, file and program names, and source code.

monospace

Denotes a permitted abbreviation for a command or option. You

can enter the underlined text instead of the full command or option

name.

monospace

italic

Denotes arguments to monospace text where the argument is to be

replaced by a specific value.

monospace

bold

Denotes language keywords when used outside example code.

< and > Angle brackets enclose replaceable terms for assembler syntax

where they appear in code or code fragments. They appear in

normal font in running text. For example:

•

MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>

• The Opcode_2 value selects which register is accessed.

Timing diagrams

The figure named Key to timing diagram conventions on page xii explains the

components used in timing diagrams. Variations, when they occur, have clear labels.

You must not assume any timing information that is not explicit in the diagrams.

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Preface

Shaded bus and signal areas are undefined, so the bus or signal can assume any value

within the shaded area at that time. The actual level is unimportant and does not affect

normal operation.

Key to timing diagram conventions

Signals

The signal conventions are:

Signal level The level of an asserted signal depends on whether the signal is

active-HIGH or active-LOW. Asserted means HIGH for

active-HIGH signals and LOW for active-LOW signals.

Prefix A Denotes Advanced eXtensible Interface (AXI) global and address

channel signals.

Prefix B Denotes AXI write response channel signals.

Prefix C Denotes AXI low-power interface signals.

Prefix H Denotes Advanced High-performance Bus (AHB) signals.

Prefix n Denotes active-LOW signals except in the case of AXI, AHB or

Advanced Peripheral Bus (APB) reset signals.

Prefix P Denotes APB signals.

Prefix R Denotes AXI read channel signals.

Prefix W Denotes AXI write channel signals.

Suffix n Denotes AXI, AHB, and APB reset signals.

Clock

HIGH to LOW

Transient

HIGH/LOW to HIGH

Bus stable

Bus to high impedance

Bus change

High impedance to stable bus

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Preface

Numbering

The numbering convention is:

This is a Verilog method of abbreviating constant numbers. For example:

• 'h7B4 is an unsized hexadecimal value.

• 'o7654 is an unsized octal value.

• 8'd9 is an eight-bit wide decimal value of 9.

• 8'h3F is an eight-bit wide hexadecimal value of

0x3F

. This is

equivalent to b00111111.

• 8'b1111 is an eight-bit wide binary value of b00001111.

Further reading

This section lists publications by ARM Limited, and by third parties.

ARM Limited periodically provides updates and corrections to its documentation. See

http://www.arm.com

for current errata sheets, addenda, and the ARM Limited

Frequently Asked Questions list.

ARM publications

This manual contains information that is specific to the IPCM. Refer to the following

documents for other relevant information:

•AMBA®Specification (Rev 2.0) (ARM IHI 0011)

•AMBA AXI Protocol Specification (ARM IHI 0022)

•DSP Integration Specification (ARM IHI 0026)

•Message Passing Software Integration Guide (ARM DII 0091)

•PrimeCell Inter-Processor Communications Module Implementation Guide

(ARM DII 0107).

•PrimeCell Inter-Processor Communications Module Integration Manual

(ARM DII 0108).

•PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual

(ARM DDI 0273)

•PrimeCell Core Identification Module (PL321) r0p0 Technical Reference Manual

(ARM DDI 0327).

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Preface

Feedback

ARM Limited welcomes feedback on the IPCM and its documentation.

Feedback on the IPCM

If you have any comments or suggestions about this product, contact your supplier

giving:

• the product name

• a concise explanation of your comments.

Feedback on this manual

If you have any comments on this manual, send email to

[email protected]

giving:

• the title

• the number

• the relevant page number(s) to which your comments apply

• a concise explanation of your comments.

ARM Limited also welcomes general suggestions for additions and improvements.

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Chapter 1

Introduction

This chapter introduces the Inter-Processor Communications Module (IPCM). It

contains the following section:

•About the IPCM on page 1-2.

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Introduction

1.1 About the IPCM

The IPCM provides up to 32 mailboxes with control logic and interrupt generation to

support inter-processor communication. An AHB interface enables access from source

and destination cores.

The IPCM:

• sends interrupts to other cores

• passes small amounts of data to other cores.

The mailboxes within the IPCM can be available as floating resources between cores or

as dedicated resources to specific cores. A source core can have multiple mailboxes and

send messages in parallel.

The IPCM consists of the following:

• 1-32 programmable mailboxes, each comprising:

— a single 1-32-bit Mailbox Source Register

— a single 1-32-bit Mailbox Destination Register with separate Set, Clear, and

Status addresses

— a single 2-bit Mailbox Mode Register to enable Auto Acknowledge and

Auto Link modes

— a single 1-32-bit Mailbox Mask Register with separate Set, Clear, and

Status addresses to enable you to mask out individual mailbox interrupts for

cores requiring to poll rather than be interrupted

— a single 2-bit Mailbox Send Register to trigger mailbox interrupts to source

and destination cores

— 0-7 32-bit data registers to store the message.

• 1-32 sets of read-only interrupt status registers, one for each interrupt, each

comprising:

— 1-32-bit Raw Interrupt Status Register (each bit corresponds to each

mailbox)

— 1-32-bit Masked Interrupt Status Register (each bit corresponds to each

mailbox).

• A 32-bit Configuration Status Register

• Integration Test Registers for the interrupt outputs

• Peripheral and PrimeCell Identification Registers.

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Introduction

The IPCM is a highly configurable and programmable module. It has three configurable

parameters:

• 1-32 mailboxes

• 0-7 data registers per mailbox

• 1-32 interrupts.

These parameters reduce gate count by enabling you to configure the IPCM instance to

match the system requirements. The programmable features, such as source,

destination, mode, and mask, enable the configured IPCM to be used by different cores

in different ways, depending on the current application.

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Introduction 
1-4 Copyright © 2003, 2004. ARM Limited. All rights reserved. ARM DDI 0306B
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Chapter 2

Functional Overview

This chapter describes the major functional blocks of the IPCM. It contains the

following sections:

•Functional description on page 2-2

•Functional operation on page 2-4

•Examples of messaging on page 2-18.

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Functional Overview

2.1 Functional description

Figure 2-1 shows a block diagram of the IPCM.

Figure 2-1 IPCM block diagram

The IPCM contains three main functional blocks:

AHB interface

The AHB interface enables access from the system bus to the IPCM

registers.

Mailboxes and control logic

The mailbox and control logic block contains all the mailbox registers

and control logic.

Interrupt generation logic

The interrupt generation logic block generates the IPCM interrupt

outputs from the current status of all the IPCM mailboxes.

Figure 2-2 on page 2-3 shows the integration of the IPCM in a multiprocessing system.

AHB

interface

SCANENABLE

SCANINHCLK

SCANOUTHCLK

IPCMINT[31:0]

Mailboxes

and control

logic

Interrupt

generation

logic

HCLK

HRESETn

HADDR[11:2]

HREADY

HSEL

HWRITE

HSIZE[2:0]

HWDATA[31:0]

HRDATA[31:0]

HREADYOUT

HRESP[1:0]

IPCM

MBOXNUM[5:0]

INTNUM[5:0]

DATANUM[2:0]

HTRANS

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ARM PrimeCelL PL320 Product manual

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