Texas Instruments TPA3003D2 User manual


SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
     
   
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FEATURES
D3-W/Ch Into an 8-ΩLoad From 12-V Supply
DEfficient, Class-D Operation Eliminates
Heatsinks and Reduces Power Supply
Requirements
D32-Step DC Volume Control From −40 dB
to 36 dB
DThird Generation Modulation Techniques
− Replaces Large LC Filter With Small
Low-Cost Ferrite Bead Filter
DThermal and Short-Circuit Protection
APPLICATIONS
DLCD Monitors and TVs
DPowered Speakers
DESCRIPTION
The TPA3003D2 is a 3-W (per channel) efficient,
Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3003D2 can drive stereo speakers
as low as 8 Ω. The high efficiency of the TPA3003D2
eliminates the need for external heatsinks when playing
music.
Stereo speaker volume is controlled with a dc voltage
applied to the volume control terminal offering a range
of gain from –40 dB to 36 dB.
Cs
Cs
10 nF
Cbs
Cs
Cs 10 nF
Cbs
PVCC PVCC
Cs
Cs
10 nF
Cbs
Cs
Cs 10 nF
Cbs
PVCC PVCC
220 pF
Cosc
Rosc
Ccpl
100 nF
Cvdd
Ccpr
Crinp
Crinn
Clinn
Clinp
LINP
LINN
RINN
RINP
SYSTEM CONTROL
VOLUME
BSLP PVCCL PVCCL LOUTP LOUTP PGNDL PGNDL LOUTN LOUTN PVCCL PVCCL BSLN
TPA3003D2
VCLAMPRSD
V2P5
RINP
LINN
LINP
AVDDREF
VREF
AGND
AGND
VOLUME
REFGND
MUTE
NC
NC
NC
AVDD
AGND
COSC
ROSC
AVCC
VCLAMPL
BSRP
PVCCR PVCCR
ROUTP ROUTP
PGNDR PGNDR
ROUTN ROUTN
PVCCR PVCCR
BSRN
RINN
AVDD
AVCC
C2p5
FADE
10 µF10 µF
0.1 µF0.1 µF
1 µF
1 µF
1 µF
1 µF
1 µF
0.1 µF0.1 µF
10 µF10 µF
1 µF
120 kΩ
1 µF
Cs
0.1 µFCvcc
10 µF
MUTE CONTROL
SYSTEM CONTROL
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Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

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AVAILABLE OPTIONS
TA
PACKAGED DEVICE
T
A48-PIN TQFP (PFB)†
−40°C to 85°C TPA3003D2PFB
†The PFB package is available taped and reeled. To order a taped and
reeled part, add the suffix R to the part number (e.g., TPA3003D2PFBR).
PHP PACKAGE
(TOP VIEW)
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
BSRN PVCCR PVCCR ROUTN ROUTN PGNDR PGNDR ROUTP ROUTP PVCCR PVCCR BSRP
VCLAMPR
NC
MUTE
NC
NC
FADE
COSC
ROSC
AGND
VCLAMPL
SD
RINN
RINP
V2P5
LINP
LINN
VREF
AGND
AGND
VOLUME
REFGND
BSLN
PVCCL PVCCL
LOUTN LOUTN
PGNDL PGNDL
LOUTP LOUTP PVCCL PVCCL
BSLP
TPA3003D2
AVCC
AVDD
AVDDREF

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functional block diagram
Biases
&
References
TTL Input
Buffer
Startup
Protection
Logic
Short Circuit
Detect
Thermal
VDDok
RINP
RINN
Ramp
Generator
COSC
ROSC
VCCok
5V LDO
AVCC
AVDD
AVDD
VDD
Deglitch &
Modulation
Logic
Gain
Adj.
Gain
Control
Deglitch &
Modulation
Logic
Gain
Adj.
Rfdbk2
Rfdbk2
Cint2
Cint2
LINP
LINN
Gate
Drive
VClamp
Gen
Gate
Drive
PVCC
BSRP
PVCCR(2)
ROUTP(2)
PGNDR
PGNDR
ROUTN(2
)
PVCCR(2)
BSRN
Gate
Drive
VClamp
Gen
Gate
Drive
PVCC
BSLP
PVCCL(2)
LOUTP(2)
PGNDL
PGNDL
LOUTN(2)
PVCCL(2)
BSLN
VCLAMPL
VCLAMPR
VOLUME To Gain Adj.
SD
VREF
REFGND V2P5
V2P5
V2P5
AVCC
AGND
AVDDREF
V2P5
V2P5
MUTE
FADE Blocks

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NO. NAME
I/O
DESCRIPTION
AGND 9, 10, 26 −Analog ground for digital/analog cells in core
AVCC 33 − High-voltage analog power supply (8.5 V to 14 V)
AVDD 29 O 5-V Regulated output
AVDDREF 7 O 5-V Reference output—provided for connection to adjacent VREF terminal.
BSLN 13 I/O Bootstrap I/O for left channel, negative high-side FET
BSLP 24 I/O Bootstrap I/O for left channel, positive high-side FET
BSRN 48 I/O Bootstrap I/O for right channel, negative high-side FET
BSRP 37 I/O Bootstrap I/O for right channel, positive high-side FET
COSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5
FADE 30 I Input for controlling volume ramp rate when cycling SD or during power-up. A logic low on this pin places
the amplifier in fade mode. A logic high on this pin allows a quick transition to the desired volume setting.
LINN 6 I Negative differential audio input for left channel
LINP 5 I Positive differential audio input for left channel
LOUTN 16, 17 OClass-D 1/2-H-bridge negative output for left channel
LOUTP 20, 21 OClass-D 1/2-H-bridge positive output for left channel
MUTE 34 I A logic high on this pin disables the outputs. A low on this pin enables the outputs.
NC 31, 32,
35 −Not internally connected
PGNDL 18, 19 −Power ground for left channel H-bridge
PGNDR 42, 43 −Power ground for right channel H-bridge
PVCCL 14, 15 −Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or
AVCC.
PVCCL 22, 23 −Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or
AVCC.
PVCCR 38,39 − Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or
AVCC.
PVCCR 46, 47 −Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or
AVCC.
REFGND 12 − Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC
ground to this terminal.
RINP 3 I Positive differential audio input for right channel
RINN 2 I Negative differential audio input for right channel
ROSC 27 I/O Current setting resistor for ramp generator. Nominally equal to 1/8*VCC
ROUTN 44, 45 OClass-D 1/2-H-bridge negative output for right channel
ROUTP 40, 41 OClass-D 1/2-H-bridge positive output for right channel
SD 1 I Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.
VCLAMPL 25 − Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR 36 − Internally generated voltage supply for right channel bootstrap capacitors.
VOLUME 11 IDC voltage that sets the gain of the amplifier.
VREF 8 I Analog reference for gain control section.
V2P5 4 O 2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended
inputs.

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range: AVCC, PVCC −0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: MUTE, VREF, VOLUME, FADE 0 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SD −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RINN, RINP, LINN, LINP −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply current, AVDD 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVDDREF 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA−40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, TJ−40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE TA≤25°CDERATING FACTOR TA= 70°C TA= 85°C
PFB 2.8 W 22.2 mW/°C1.8 W 1.4 W
recommended operating conditions
MIN MAX UNIT
Supply voltage, VCC PVCC, AVCC 8.5 14 V
Volume reference voltage VREF 3.0 5.5 V
Volume control pins, input voltage VOLUME 5.5 V
SD 2
High-level input voltage, V
IH
MUTE 3.5 V
High-level input voltage, VIH
FADE 4
V
SD 0.8
Low-level input voltage, V
IL
MUTE 2 V
Low-level input voltage, VIL
FADE 2
V
MUTE, VI= 5 V, VCC = 14 V 1
High-level input current, I
IH
SD, VI= 14 V, VCC = 14 V 50 µA
High-level input current, IIH
FADE, VI= 5 V, VCC = 14 V 150
µA
Low-level input current, IIL
MUTE, SD, FADE, VI= 0 V, VCC = 14 V
1
A
Low-level input current, I
IL
MUTE, SD, FADE, V
I
= 0 V, V
CC
= 14 V 1µA
Oscillator frequency, fOSC 225 275 kHz
Operating free-air temperature, TA−40 85 °C

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dc characteristics, TA= 25°C, VCC = 12 V, RL= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
| VOS | Output offset voltage (measured
differentially) INN and INP connected together, Gain = 36 dB 10 65 mV
V2P5 (terminal 4) 2.5-V Bias voltage No load 0.45x
AVDD 0.5x AVDD 0.55x AVDD V
PSRR Power supply rejection ratio VCC = 11.5 V to 12.5 V −80 dB
ICC Supply quiescent current MUTE = 2 V, SD = 2 V 16 28.5 mA
ICC(MUTE) MUTE mode quiescent current MUTE = 3.5 V, SD = 2 V 7 9 mA
ICC(max power) Supply current at max power RL= 8 Ω, PO= 3 W 0.6 A
ICC(SD) Supply current in shutdown mode SD = 0.8 V 1 10 µA
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC = 12 V,
ÁÁÁÁÁ
ÁÁÁÁÁ
High side
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
600
ÁÁÁ
ÁÁÁ
700
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
rds(on)
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Drain-source on-state resistance
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC = 12 V,
IO= 1 A,
T = 25 C
ÁÁÁÁÁ
ÁÁÁÁÁ
Low side
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
600
ÁÁÁ
ÁÁÁ
700
ÁÁÁ
ÁÁÁ
mΩ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
rds(on)
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Drain-source on-state resistance
ÁÁÁÁÁ
ÁÁÁÁÁ
IO= 1 A,
TJ= 25°C
ÁÁÁÁÁ
ÁÁÁÁÁ
Total
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
1200
ÁÁÁ
ÁÁÁ
1400
ÁÁÁ
ÁÁÁ
m
ac characteristics, TA= 25°C, VCC = 12 V, RL= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
kSVR Supply ripple rejection ratio VCC = 11.5 V to 12.5 V from 10 Hz
to 1 kHz, Gain = 36 dB −67 dB
PO(max)
Maximum continuous output power
THD+N = 1%, f = 1 kHz, RL= 8 Ω3 W
PO(max) Maximum continuous output power THD+N = 10%, f = 1 kHz, RL= 8 Ω3.75 W
VnOutput integrated noise floor 20 Hz to 22 kHz, No weighting filter,
Gain = 0.5 dB −82 dBV
Crosstalk, Left →Right Gain = 13.2 dB, PO= 1 W, RL= 8 Ω−77 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 0.5%,
f= 1 kHz, Gain = 0.5 dB 102 dB
Thermal trip point 150 °C
Thermal hystersis 20 °C

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Table 1. DC Volume Control
VOLTAGE ON THE
VOLUME PIN AS A
PERCENTAGE OF
VREF (INCREASING
VOLUME OR FIXED
GAIN)
VOLTAGE ON THE
VOLUME PIN AS A
PERCENTAGE OF
VREF (DECREASING
VOLUME)
GAIN OF AMPLIFIER
% % dB
0 − 4.5 0 − 2.9 −75†
4.5 − 6.7 2.9 − 5.1 −40.0
6.7 − 8.91 5.1 − 7.2 −37.5
8.9 − 11.1 7.2 − 9.4 −35.0
11.1 − 13.3 9.4 − 11.6 −32.4
13.3 − 15.5 11.6 − 13.8 −29.9
15.5 − 17.7 13.8 − 16.0 −27.4
17.7 − 19.9 16.0 − 18.2 −24.8
19.9 − 22.1 18.2 − 20.4 −22.3
22.1 − 24.3 20.4 − 22.6 −19.8
24.3 − 26.5 22.6 − 24.8 −17.2
26.5 − 28.7 24.8 − 27.0 −14.7
28.7 − 30.9 27.0 − 29.1 −12.2
30.9 − 33.1 29.1 − 31.3 −9.6
33.1 − 35.3 31.3 − 33.5 −7.1
35.3 − 37.5 33.5 − 35.7 −4.6
37.5 − 39.7 35.7 − 37.9 −2.0
39.7 − 41.9 37.9 − 40.1 0.5†
41.9 − 44.1 40.1 − 42.3 3.1
44.1 − 46.4 42.3 − 44.5 5.6
46.4 − 48.6 44.5 − 46.7 8.1
48.6 − 50.8 46.7 − 48.9 10.7
50.8 − 53.0 48.9 − 51.0 13.2
53.0 − 55.2 51.0 − 53.2 15.7
55.2 − 57.4 53.2 − 55.4 18.3
57.4 − 59.6 55.4 − 57.6 20.8
59.6 − 61.8 57.6 − 59.8 23.3
61.8 − 64.0 59.8 − 62.0 25.9
64.0 − 66.2 62.0 − 64.2 28.4
66.2 − 68.4 64.2 − 66.4 30.9
68.4 − 70.6 66.4 − 68.6 33.5
> 70.6 >68.6 36.0†
†Tested in production. Remaining steps are specified by design.

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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency vs Output power 1
P
O
Output power vs Load resistance 2
PO
Output power
vs Supply voltage 3
IQQuiescent supply current vs Supply voltage 4
ICC Supply current vs Output Power 5
IQ(sd) Quiescent shutdown supply current vs Supply voltage 6
Input impedance vs Gain 7
THD+N
Total harmonic distortion + noise
vs Frequency 8, 9
THD+N Total harmonic distortion + noise vs Output power 10, 11
kSVR Supply ripple rejection ratio vs Frequency 12
Closed loop response 13, 14
Intermodulation performance 15
Input offset voltage vs Common-mode input voltage 16
Crosstalk vs Frequency 17
Mute attenuation
vs Frequency
18
Shutdown attenuation vs Frequency 19
Common-mode rejection ratio vs Frequency 20

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TYPICAL CHARACTERISTICS
Figure 1
0
10
20
30
40
50
60
70
80
0 0.5 1 1.5 2 2.5 3
PO− Output Power − W
EFFICIENCY
vs
OUTPUT POWER
Efficiency − %
VCC = 12 V, RL= 8 Ω
VCC = 8.5 V, RL= 8 Ω
LC Filter
Resistive Load
Figure 2
0
1
2
3
4
5
6
7
8
8 9 10 11 12 13 14 15 16
Thermally Limited
P
O− Output Power − W
OUTPUT POWER
vs
LOAD RESISTANCE
RL− Load Resistance − Ω
VCC = 8.5 V,
THD = 1%
VCC = 8.5 V,
THD = 10%
VCC = 12 V,
THD = 1%
VCC = 12 V,
THD = 10%
Figure 3
OUTPUT POWER
vs
SUPPLY VOLTAGE
P
O− Output Power − W
VDD − Supply Voltage − V
1
2
3
4
5
6
8.5 9 10 11 12 13 14
Thermally Limited
8 Ω, THD = 10%
8 Ω, THD = 1%
Figure 4
10
11
12
13
14
15
16
17
18
8.59 1011121314
QUIESCENT SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC − Supply Voltage − V
I − Quiescent Supply Current − mA
Q
TA= 25°C

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TYPICAL CHARACTERISTICS
Figure 5
SUPPLY CURRENT
vs
OUTPUT POWER (TOTAL)
PO− Output Power (Total) − W
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0123456
VCC = 12 V,
RL= 8 Ω
− Supply Current − A
CC
I
Figure 6
0
0.2
0.4
0.6
0.8
1
8.5 9 10 11 12 13 14
VSD = 0 V
VSD = 0.8 V
QUIESCENT SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC − Supply Voltage − V
− Quiescent Shutdown Supply Current − Aµ
CC
I
Figure 7
60
40
20
0
−50 −30 −10 10
80
100
120
30 50
− Input Impedance − k
Gain − dB
INPUT IMPEDANCE
vs
GAIN
ZiΩ
Figure 8
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
PO= 0.5 W
VCC = 12 V,
RL= 8 Ω,
TA= 25°C
f − Frequency − Hz
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
PO= 1 W
PO= 3 W

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TYPICAL CHARACTERISTICS
Figure 9
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
PO= 0.5 W
VCC = 12 V,
RL= 8 Ω,
TA= 25°C
f − Frequency − Hz
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
PO= 1 W
PO= 3.5 W
Figure 10
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20m 50m 100m 200m 500m 1 2 5 10
VCC = 8.5 V,
RL= 8 Ω,
TA= 25°C
PO− Output Power − W
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
f = 20 Hz
f = 1 kHz
f = 20 KHz
Figure 11
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20m 50m 100m 200m 500m 1 2 5 10
VCC = 12 V,
RL= 8 Ω,
TA= 25°C
PO− Output Power − W
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
f = 1 kHz
f = 20 kHz
f = 20 Hz
Figure 12
−90
−85
−80
−75
−70
−65
−60
−55
−50
−45
−40
20 100 1 k 10 k 100 k
VCC = 12 V,
RL= 8 Ω
f − Frequency − Hz
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
kSVR − Supply Ripple Rejection Ratio − dB

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TYPICAL CHARACTERISTICS
Figure 13
−250
−200
−150
−100
−50
0
50
10 100 1 k 10 k 100 k 1 M
Gain
Phase
−250
−200
−150
−100
−50
0
50
Gain − dB
f − Frequency − Hz
CLOSED LOOP RESPONSE
Phase − Deg
VCC = 12 V,
Gain = +5.6 dB,
RL= 8 Ω
Figure 14
−250
−200
−150
−100
−50
0
50
100
10 100 1 k 10 k 100 k 1 M
Gain
Phase
−250
−200
−150
−100
−50
0
50
100
Gain − dB
f − Frequency − Hz
CLOSED LOOP RESPONSE
Phase − Deg
VCC = 12 V,
Gain = +36 dB,
RL= 8 Ω
Figure 15
−140
0
−120
−100
−80
−60
−40
−20
50 100 1 k 10 k
FFT − dBr
INTERMODULATION PERFORMANCE
f − Frequency − Hz
VCC = 12 V, 19 kHz, 20 kHz,
1:1, PO= 1 W, RL= 8 Ω
Gain= +13.2 dB,
BW =20 Hz to 22 kHz,
Class-D
No Filter
Figure 16
2
1
0
−1
− Input Offset Voltage − mV
4
5
6
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
V
IO
3
VICM − Common-Mode Input Voltage − V
1 1.5 2 2.5 3 3.5 4 4.5 5
VCC = 12 V

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TYPICAL CHARACTERISTICS
Figure 17
−95
−90
−85
−80
−75
−70
−65
−60
10 100 1 k 10 k 100 k
Crosstalk − dB
f − Frequency − Hz
CROSSTALK
vs
FREQUENCY
VCC = 12 V,
Gain = +13.2 dB,
RL= 8 Ω,
PO= 1 W
Figure 18
−80
−100
−110
−13010 100 1 k
Mute Attenuation − dB
−60
−50
f − Frequency − Hz
MUTE ATTENUATION
vs
FREQUENCY
−30
10 k
−120
−90
−70
−40 VCC = 12 V,
RL= 8 Ω,
VI= 1 Vrms
Class-D,
VOLUME = 0 V
Figure 19
−105
−115
−120
−13010 100 1 k
Shutdown Attenuation − dB
−95
−90
f − Frequency − Hz
SHUTDOWN ATTENUATION
vs
FREQUENCY
−80
10 k
−125
−110
−100
−85 VCC = 12 V,
RL= 8 Ω,
VI= 1 Vrms
Gain = +13.2 dB,
Class-D
Figure 20
−90
−80
−70
−60
20 100 1 k 10 k 20 k
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
VCC = 12 V
−100

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APPLICATION INFORMATION
C11
C17
10 nF
C20 C12
10 nF
C21
220pF
C6
R1
C8
100 nF
C14
C7
C2
C1
C4
C3
LIN−
RIN−
SHUTDOWN
BSLP PVCCL PVCCL LOUTP LOUTP PGNDL PGNDL LOUTN LOUTN PVCCL PVCCL BSLN
TPA3003D2
VCLAMPR
SD
V2P5
RINP
LINN
LINP
AVDDREF
VREF
AGND
AGND
VOLUME
REFGND
MUTE
NC
NC
NC
FADE
AVDD
AGND
COSC
ROSC
AVCC
VCLAMPL
BSRP
PVCCR PVCCR
ROUTP ROUTP
PGNDR PGNDR
ROUTN ROUTN
PVCCR
PVCCR
BSRN
RINN
C16
C5
P1
LOUT−
VCC VCC
LOUT+
C9
C15
10 nF
C18 C10
10 nF
C19
ROUT−
VCC
VCC
L3
(Bead)
C24
1nF
L4
(Bead)
C25
1nF
GND
GND GND
AVDD
C13
GND
MUTE
AGND
AGND
AGND
PGND
PGND
PGND
PGND
GND
ROUT+
L1
(Bead)
C22
1 nF
L2
(Bead)
C23
1 nF
VCC
10 µF
0.1uF 0.1uF
1 µF
0.1 µF 10 µF
120 kΩ
1 µF
0.1 µF0.1 µF
10 µF
50 kΩ
1 µF
1 µF
1 µF
1 µF
1 µF
CONTROL
Figure 21. Stereo Configuration With Single-Ended Inputs

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APPLICATION INFORMATION
class-D operation
This section focuses on the class-D operation of the TPA3003D2.
traditional class-D modulation scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown
in Figure 22. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is
high, causing high loss, thus causing a high supply current.
0 V
−12 V
+12 V
Current
OUTP
Differential Voltage
Across Load
OUTN
Figure 22. Traditional Class-D Modulation Scheme’s Output Voltage and
Current Waveforms Into an Inductive Load With No Input
TPA3003D2 modulation scheme
The TPA3003D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50%
and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout
most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.

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APPLICATION INFORMATION
TPA3003D2 modulation scheme (continued)
0 V
−12 V
+12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
0 V
−12 V
+12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
Output > 0 V
Figure 23. The TPA3003D2 Output Voltage and Current Waveforms Into an Inductive Load
efficiency: LC filter required with the traditional class-D modulation scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme, because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 ×VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3003D2 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is VCC instead of 2 ×VCC. As the output power increases, the pulses widen,
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker, which results in less power
dissipation, therefore increasing efficiency.

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APPLICATION INFORMATION
effects of applying a square wave into a speaker
Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the
waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the
square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching
frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2for
frequencies beyond the audio band.
Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency
switching current. The amount of power dissipated in the speaker may be estimated by first considering the
overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the
dominant loss in the system, then the maximum theoretical efficiency for the TPA3003D2 with an 8-Ωload is
as follows:
Efficiency (theoretical, %) +RLńǒRL)rds(on)Ǔ 100% +8ń(8 )1.4) 100% +85.11%
The maximum measured output power is approximately 3 W with an 12-V power supply. The total theoretical
power supplied (P(total)) for this worst-case condition would therefore be as follows:
P(total) +POńEfficiency +3Wń0.8511 +3.52 W
The efficiency measured in the lab using an 8-Ωspeaker was 75%. The power not accounted for as dissipated
across the rds(on) may be calculated by simply subtracting the theoretical power from the measured power:
Other losses +P(total)(measured) *P(total) (theoretical) +4*3.52 +0.48 W
The quiescent supply current at 12 V is measured to be 28.5 mA. It can be assumed that the quiescent current
encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any
remaining power is dissipated in the speaker and is calculated as follows:
P(dis) +0.48 W *(12 V 28.5 mA) +0.14 W
Note that these calculations are for the worst-case condition of 3 W delivered to the speaker. Since the 0.14 W
is only 5% of the power delivered to the speaker, it may be concluded that the amount of power actually
dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the
specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the
power generated from a clipping waveform.
when to use an output filter
Design the TPA3003D2 without the filter if the traces from amplifier to speaker are short (< 1 inch). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but very low impedance at low frequencies.
Use a LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires from
the amplifier to the speaker.
(1)
(2)
(3)
(4)

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APPLICATION INFORMATION
when to use an output filter (continued)
0.1 µF
0.1 µF
0.47 µF
33 µH
33 µH
OUTP
OUTN
L1
L2
C1C2
C3
Figure 24. Typical LC Output Filter, Cutoff Frequency of 41 kHz, Speaker Impedance = 8 Ω
1 nF
Ferrite
Chip Bead
OUTP
OUTN
Ferrite
Chip Bead
1 nF
Figure 25. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
volume control operation
The VOLUME terminal controls the internal amplifier gain. This pin is controlled with a dc voltage, which should
not exceed VREF. Table 1 lists the gain as determined by the voltage on the VOLUME pin in reference to the
voltage on VREF.
If using a resistor divider to fix the gain of the amplifier, the VREF terminal can be directly connected to
AVDDREF and a resistor divider can be connected across VREF and REFGND. (See Figure 21 in the
Application Information Section). For fixed gain, calculate the resistor divider values necessary to center the
voltage between the two percentage points given in the first column of Table 1. For example, if a gain of 10.7
dB is desired, the resistors in the divider network can both be 10 kΩ. With these resistor values, a voltage of
50%*VREF will be present at the VOLUME pin and result in a class-D gain of 10.7 dB.
If using a DAC to control the class-D gain, VREF and REFGND should be connected to the reference voltage
for the DAC and the GND terminal of the DAC, respectively. For the DAC application, AVDDREF would be left
unconnected. The reference voltage of the DAC provides the reference to the internal gain circuitry through the
VREF input and any fluctuations in the DAC output voltage will not affect the TPA3003D2 gain. The percentages
in the first column of Table 1 should be used for setting the voltages of the DAC when the voltage on the VOLUME
terminal is increased. The percentages in the second column should be used for the DAC voltages when
decreasing the voltage on the VOLUME terminal. Two lookup tables should be used in software to control the
gain based on an increase or decrease in the desired system volume. This is explained further in a section
below.

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APPLICATION INFORMATION
volume control operation (continued)
If using an analog potentiometer to control the gain, it should be connected between VREF and REFGND.
VREF can be connected to AVDDREF or an external voltage source, if desired. The first and second column
in Table 1 should be used to determine the point at which the gain changes depending on the direction that the
potentiometer is turned. If the voltage on the center tap of the potentiometer is increasing, the first column in
Table 1 should be referenced to determine the trip points. If the voltage is decreasing, the trip points in the
second column should be referenced.
The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME
terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that
the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation
of the volume control can be found in Figure 26. The graph focuses on three gain steps with the trip points
defined in the first and second columns of Table 1. The dotted lines represent the hysteresis about each gain
step.
The timing of the volume control circuitry is controlled by an internal 60-Hz clock. This clock determines the
rate at which the gain changes when adjusting the voltage on the external volume control pins. The gain updates
every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step until the final desired gain is
reached. For example, if the TPA3003D2 is currently in the +0.53 dB gain step and the VOLUME pin is adjusted
for maximum gain at +36 dB, the time required for the gain to reach +36 dB is 14 steps x 67ms/step = 0.938
seconds. Referencing Table 1, there are 14 steps between the +0.53 dB gain step and the maximum gain step
of +36 dB.
0.5
3.1
5.6
2.10
2.00 2.11 2.21
Class-D Gain − dB
Voltage on VOLUME Pin − V
Decreasing Voltage on
VOLUME Terminal
Increasing Voltage on
VOLUME Terminal
(40.1%*VREF) (44.1%*VREF)
(42.3%*VREF)
(41.9%*VREF)
Figure 26. DC Volume Control Operation, VREF = 5 V

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APPLICATION INFORMATION
FADE operation
The FADE terminal is a logic input that controls the operation of the volume control circuitry during transitions
to and from the shutdown state and during power-up.
A logic low on this terminal places the amplifier in the fade mode. During power-up or recovery from the
shutdown state (a logic high is applied to the SD terminal), the volume is smoothly ramped up from the mute
state, −75 dB, to the desired volume setting determined by the voltage on the volume control terminal.
Conversely, the volume is smoothly ramped down from the current state to the mute state when a logic low is
applied to the SD terminal. The timing of the volume control circuitry is controlled by an internal 60-Hz clock.
This clock determines the rate at which the gain changes when adjusting the voltage on the external volume
control pins. The gain updates every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step
until the final desired gain is reached. For example, if the TPA3003D2 is currently in the +0.53 dB class-D gain
step and the VOLUME pin is adjusted for maximum gain at +36 dB, the time required for the gain to reach 36
dB is 14 steps x 67 ms/step = 0.938 seconds. Referencing Table 1, there are 14 steps between the +0.53 dB
gain step and the maximum gain step of +36 dB.
Figure 27 shows a scope capture of the differential output (measured across OUT+ and OUT−) with the amplifier
in the fade mode. A 1 Vpp dc voltage was applied across the differential inputs and a logic low was applied to
the SD terminal at the time defined in the figure. The figure depicts the outputs transitioning from one gain step
to the next lower step at approximately 67 ms/step.
A logic high on this pin disables the volume fade effect during transitions to and from the shutdown state and
during power-up. During power-up or recovery from the shutdown state (a logic high is applied to the SD
terminal), the transition from the mute state, −75 dB, to the desired volume setting is less than 1 ms. Conversely,
the volume ramps down from current state to the mute state within 1 ms when a logic low is applied to the SD
terminal.
Figure 28 shows a scope capture of the differential output with the fade effect disabled. The outputs transition
to the lowest gain state within 1ms of applying a logic low to the SD terminal.
SD = 0V
GND
Figure 27. Differential Output With FADE (Terminal 30) Held Low