Texas Instruments AFE5801 User manual

User's Guide
SLOU257B–October 2009–Revised March 2015
AFE5801 8-Channel Variable Gain Amplifier (VGA) with
Octal High-Speed ADC
The AFE5801EVM is an evaluation tool designed for the ultrasound analog front-end (AFE) device
AFE5801. In order to deserialize the outputs of AFE5801, an ADSDeSer-50EVM or TSW1400EVM is
needed during the evaluation.
Contents
1 Introduction ................................................................................................................... 3
1.1 AFE5801EVM Kit Contents........................................................................................ 3
1.2 Features.............................................................................................................. 3
1.3 Power Supplies ..................................................................................................... 3
1.4 Indicators............................................................................................................. 3
2 Board Configuration ......................................................................................................... 5
2.1 Board Connections Overview ..................................................................................... 5
2.2 I/O and Power Connectors ........................................................................................ 6
2.3 Jumpers and Setup................................................................................................. 6
2.4 Test Points........................................................................................................... 9
3 Board Operation ............................................................................................................. 9
3.1 Software Installation and Operation.............................................................................. 9
3.2 Hardware Setup ................................................................................................... 14
3.3 Clock Selection .................................................................................................... 14
3.4 Data Analysis ...................................................................................................... 15
4 Schematics, Layout, and, Bill of Materials .............................................................................. 16
4.1 Schematics......................................................................................................... 16
4.2 PCB Layout ........................................................................................................ 22
4.3 Bill of Materials .................................................................................................... 30
5 Typical Performance....................................................................................................... 32
Appendix A TSW1400 for Evaluating AFE5801 ............................................................................. 33
Appendix B High Speed Data Converter Pro (HSDCPro) GUI Installation .............................................. 45
List of Figures
1 AFE5801EVM LED Locations.............................................................................................. 4
2 AFE5801EVM TOP View ................................................................................................... 5
3 AFE5801EVM BOTTOM View ............................................................................................. 5
4 Locations of Jumpers, Headers and Switches on the AFE5801EVM................................................. 7
5 Default Setup for Jumpers.................................................................................................. 8
6 Found New Hardware Wizard Screen .................................................................................... 9
7 Found New Hardware Wizard (Next) Screen........................................................................... 10
8................................................................................................................................ 10
9 AFE5801EVM USB SPI Interface for General Registers.............................................................. 11
10 AFE5801EVM USB SPI Fixed Gain Mode.............................................................................. 12
11 AFE5801EVM USB SPI Interface for Variable Gain Mode ........................................................... 13
12 Typical AFE5801 Bench Setup: ......................................................................................... 14
13 Clock Selection Jumper Configurations: (a) Transformer (default); (b) Single-ended Clock; (c) Future
Microsoft, Windows are registered trademarks of Microsoft Corporation.
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CLK Input Option Based on U1. Both (b) and (c) Configurations Need Some Modifications on the PCB...... 14
14 Schematic Page 1.......................................................................................................... 16
15 Schematic Page 2.......................................................................................................... 17
16 Schematic Page 3.......................................................................................................... 18
17 Schematic Page 4.......................................................................................................... 19
18 Schematic Page 5.......................................................................................................... 20
19 Schematic Page 6.......................................................................................................... 21
20 Top Layer Signal ........................................................................................................... 22
21 Inner Layer 1 Ground...................................................................................................... 23
22 Inner Layer 2 Signal ....................................................................................................... 24
23 Inner Layer 3 Power ....................................................................................................... 25
24 Inner Layer 4 Ground...................................................................................................... 26
25 Bottom Layer Signal ....................................................................................................... 27
26 Top Silk Screen Layer..................................................................................................... 28
27 Bottom Silk Screen Layer ................................................................................................. 29
28 Typical Performance of AFE5801. (a) Fixed Gain Mode; (b) Variable Gain Mode................................ 32
29 Connection Between TSW1400EVM and AFE5801................................................................... 33
30 Connection of the Instruments............................................................................................ 34
31 AFE5801EVM GUI - RUN Mode ......................................................................................... 35
32 AFE5801 EVM GUI - START Button .................................................................................... 36
33 AFE5801EVM GUI - Variable Gain ...................................................................................... 37
34 AFE5801EVM GUI - Setting Fixed Gain ................................................................................ 38
35 User Interface: Initial Setup Screen...................................................................................... 39
36 User Interface: Step-by-Step Setup...................................................................................... 40
37 User Interface: Frequency Load Value to Signal Generator.......................................................... 41
38 User Interface: Final Setup Screen ...................................................................................... 42
39 User Interface: Single FFT Format....................................................................................... 43
40 User Interface: Time Domain Format.................................................................................... 44
41 Plot of Saved Sample Data ............................................................................................... 44
42 HSDCPro Install (Begin)................................................................................................... 45
43 HSDCPro Install (Install Directory)....................................................................................... 46
44 HSDCPro Install (TI License Agreement)............................................................................... 47
45 HSDCPro Install (NI License Agreement)............................................................................... 48
46 HSDCPro Install (Start Installation)...................................................................................... 49
47 HSDCPro Install (Installation Progress)................................................................................. 50
48 HSDCPro Install (Installation Complete) ................................................................................ 51
49 HSDCPro Install (h)........................................................................................................ 52
50 HSDCPro Install............................................................................................................ 52
List of Tables
1 Channel-to-Channel Matching Between the AFE5801EVM and ADSDeSER-50EVM............................ 14
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www.ti.com Introduction
1 Introduction
AFE5801 includes an 8-channel voltage-Controlled-Amplifier (VCA) with digital control and an 8-channel
65MSPS analog-to-digital converter (ADC). The outputs of the ADC are 8-channel LVDS outputs which
should be deserialized by the ADSDeSer-50EVM or TSW1400EVM. The AFE5801EVM provides an easy
way to examine the performances and functionalities of AFE5801.
1.1 AFE5801EVM Kit Contents
The AFE5801EVM kit contains the following:
• AFE5801 EVM board
• USB cable
1.2 Features
• Characterize AFE5801
• Provide 8-channel LVDS outputs from the ADC
• Compatible to the standard TI LVDS deserializer ADSDeSer-50EVM or TSW1400EVM
• Communicate with PC through USB interface
• Power Management provides multiple power supplies for AFE5801 and other devices.
1.3 Power Supplies
The AFE5801EVM requires only +5V power supplies for operation.
1.4 Indicators
The AFE5801EVM has 4 LEDs on the board as shown in Figure 1. Their states demonstrate the normal
operation of AFE5801EVM.
•LED 1: U1 status indicator. Its ON state indicates the clock management chip U1 works well if U1 is
installed.
•LED 3 and 2 (RED): 1.8VD and 1.8VA power supply indicators. ON state indicates that the AFE5801
is powered correctly.
•LED 4 (GREEN): +3.3V power supply indicator. ON state indicates that the AFE5801 is powered
correctly.
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LED 2
LED4
LED3
LED 1
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Figure 1. AFE5801EVM LED Locations
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AFE/TSW
Adapter
Connector
DUT
USB
Input
Signals
Low Jitter
Clk In
Ext Clk In
+5V
PWR
www.ti.com Board Configuration
2 Board Configuration
This chapter describes the locations and functionalities of inputs, outputs, jumpers, test points of the
AFE5801EVM in detail.
2.1 Board Connections Overview
Figure 2. AFE5801EVM TOP View
Figure 3. AFE5801EVM BOTTOM View
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2.2 I/O and Power Connectors
The positions and functions of the AFE5801EVM connectors are discussed in this section.
• Analog Inputs Ch1~Ch8 (J1~J8): Single-end analog signal is converted to differential signals by
transformer.
• Low Jitter CLK Source Input (J11): This input accepts clocks with low jitter noise, such as HP8644
output. 20~50MHz 50% duty cycle clock with 1~2Vrms amplitude can be used. When J11 is used,
make sure shunts P4, P5, P6 are removed.
• CLK output (J10): The output of either the U1 output or the on-board 40MHz oscillator output
depending on jumper P4’s connection.
• External CLK Input (J9): ADC Clock input, such as FPGA outputs. FPGA outputs must be processed
by U1. Otherwise, the ADC of AFE5801 will not achieve satisfactory performance.
• +5V PWR connector(P10): Power supply input
• USB input (P11): USB interface to control the AFE5801.
• LVDS Outputs Ch1~Ch8 (P13): Differential LVDS data outputs.
2.3 Jumpers and Setup
The board has been set to default mode. Detailed description can be found in Figure 4 and Figure 5.
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P9
P8
P7
P6
P12
SW1
P5
P4
P1
P2
P3
P15 P14
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Figure 4. Locations of Jumpers, Headers and Switches on the AFE5801EVM
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Figure 5. Default Setup for Jumpers
• P1: SPI interface for U1
• P2, P3: AFE5801 ADC clock input selection: transformer-based differential clock, single-ended
LVCMOS clock, or future clock option (needs U1 to support). Default is to use transformer-based
differential clock.
• P4: Select jitter-cleaned clock or non-jitter-cleaned clock. Default is to use non-jitter-cleaned clock (i.e.,
on-board 40MHz clock).
• P5: Use on-board 40MHz clock. Default is that the on-board clock is used.
• P6: Power on on-board 40MHz clock generator. Default is on.
• P8: Debug port for monitoring ADS SPI signals.
• P9: USB interface enable. Default is on.
• Regulated power supply outputs (P12, P7): 1.8VA, 1.8VD, and 3.3V. P12 and P7 can be configured as
power supply input as well if users would like to skip the on-board regulators. Remove the ferrite beads
L1, L2, L3, L7 and L24,
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• SW1: Reset switch for AFE5801.
2.4 Test Points
• Multiple Test Points are provided on the EVM. Refer to the attached schematics for more information.
3 Board Operation
This chapter describes how to operate the AFE5801EVM for evaluation. Both software and hardware
installation and operation are discussed.
3.1 Software Installation and Operation
The AFE5801EVM comes with a software install. To Dowload the software, visit the AFE5801 product
folder in the Tools & software section. Once the zip folder is downloaded, run setup.exe to install the
software. The software to use the TSW1400EVM is called HSDCPro (High Speed Data Converter Pro).
For information on how to download this software, please see Appendix B.
USB Driver Installation
• Connect the USB port of EVM to your PC.
• If the driver has not been installed then the message “Windows Found New Hardware” will appear.
The Wizard as the following picture will launch.
• Select "No, not this time" from the options. Press Next button
Figure 6. Found New Hardware Wizard Screen
• Select "Install from a list or specific location (Advanced)" as shown below and then click "Next".
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Figure 7. Found New Hardware Wizard (Next) Screen
• Select "Search for the best driver in these locations" and enter the file path for ("C:\Program
Files\AFE5801\CDM 2.04.06 WHQL Certified ") in the combo-box or browse to it by clicking the browse
button. Once the file path has been entered in the box, click next to proceed.
• If Microsoft®Windows®XP is configured to warn when unsigned (non-WHQL certified) drivers are
about to be installed, the following screen will be displayed unless installing a Microsoft WHQL certified
Driver. Click on "Continue Anyway" to continue with the installation. If Windows XP is configured to
ignore file signature warnings, no message will appear.
Figure 8.
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GUI Startup
• Launch GUI from XP Window
• Start →All Programs\AFE5801EVM\AFE5801
• Several different screens appear displaying the different modes (Figure 9 through Figure 11)
Figure 9. AFE5801EVM USB SPI Interface for General Registers.
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Figure 10. AFE5801EVM USB SPI Fixed Gain Mode
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Figure 11. AFE5801EVM USB SPI Interface for Variable Gain Mode
When AFE5801EVM is powered on, all registers have been set to their default modes. Refer to the
datasheet for all default settings. It is recommended to restart the SPI software when AFE5801 is powered
on in order to synchronize the AFE5801 register settings to the software displays.
Users also can fill out Address Bytes and Data Bytes and press ENTER to configure each register.
Typical Configuration
• From Figure 9 press "Init for TSW1400" button
• Select TAB “TGC Register” - Figure 10 will appear
• From Figure 11, press “Variable” button to get into fixed gain mode
• From Figure 10 enter 30 in the “Coarse Gain(dB)” field then press “Write” button.
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(a) (b) (c)
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3.2 Hardware Setup
As mentioned before, Xilinx DeSerializer ADSDeSER-50EVM or TSW1400EVM is required. Please see
details in the corresponding application notes on how to use the either of these EVMs. An example bench
setup is shown in Figure 12. Band-pass filters are required for signal source in order to ensure the correct
SNR measurements of the AFE5801.
Figure 12. Typical AFE5801 Bench Setup:
The channel order of the AFE5801 outputs is not exactly the same as the one of ADS527x outputs. As a
result, the channel number on the ADSDeSER-50EVM or AFE5801EVM might be misleading. Table 1
provides channel-to-channel sequence matching between the ADSDeSER-50EVM and AFE5801EVM.
Table 1. Channel-to-Channel Matching Between the AFE5801EVM and ADSDeSER-50EVM
AFE FCLK CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 LCLK
Xilinx FCLK CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 LCLK
For example, when an analog signal is input at CH1 on the AFE5801EVM, the corresponding 12-bit digital
output will be seen at CH8 on the ADSDeSER-50EVM when the AFE5801 is configured as 8-channel
mode.
3.3 Clock Selection
AFE5801 is typically clocked through a transformer-based circuit. Other options are also available if
needed as shown in Figure 13.
Figure 13. Clock Selection Jumper Configurations: (a) Transformer (default);
(b) Single-ended Clock; (c) Future CLK Input Option Based on U1.
Both (b) and (c) Configurations Need Some Modifications on the PCB.
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The clock source of the EVM could be the on-board clock 40MHz, HP8644 low jitter clock source, or
external clock source. The best performance of this EVM is achieved when low-jitter clock source HP8644
is used. The P4, P5, P6 should be removed in order to disable the on-board clock.
When HP8644 or similar clock sources are not available, the on-board 40MHz clock is also a desirable
source. The jumpers P4, 5, 6 should be configured as Figure 13 shows (i.e., default setup for
AFE5801EVM). In this mode, the transform-based differential clock is used.
3.4 Data Analysis
Based on the data file acquired by a logic analyzer, the performance of AFE5801 can be evaluated.
In Appendix A, we provide one solution (TI TSW1400 EVM) to analyze the data file using the PC.
Appendix B provides step by step instructions on how to download the HSDCPro (Hish Speed Data
Converter Pro) GUI, which accompanies the TSW1400EVM. Coherent sampling is recommended if the
input and sampling clock are phase locked. Due to the frequency accuracy requirement of coherence
sampling, two HP8644s for generating ADC clock and analog signal are required. For most users, this
may not be feasible. Data analysis based on windowing is a more suitable approach.
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4 Schematics, Layout, and, Bill of Materials
This chapter provides the schematics and layout of the AFE5801EVM as well as the bill of materials.
4.1 Schematics
Figure 14. Schematic Page 1
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Figure 15. Schematic Page 2
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Figure 16. Schematic Page 3
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Figure 17. Schematic Page 4
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Figure 18. Schematic Page 5
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