Texas Instruments TAS5733L User manual

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5
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8 9 10 11 12 13 14 15
Output Power (W)
PVDD (V)
RL = 4 Ω
RL = 8 Ω
Digital Audio
Processor
(DAP)
Sample Rate
Converter
(SRC)
I²C Control Port
Internal Register/State Machine Interface
Power-On Reset
(POR)
PVDDDVDD
MCLK Monitoring
and Watchdog
AVDD
PDN RST
AMP_OUT_A
AMP_OUT_C
SDIN
MCLK
SCLK
LRCK
SCL SDA
Serial Audio Port
(SAP)
Sample Rate
Auto-Detect
PLL
Digital to PWM
Converter
(DPC)
Click & Pop
Suppression
2 Ch. PWM
Modulator
Noise Shaping
Open Loop Stereo
Stereo PWM Amplifier
Sensing & Protection
Temperature
Short Circuits
PVDD Voltage
Output Current
Fault Notification
Internal Voltage Supplies
Internal Regulation and Power Distribution
AMP_OUT_B
AMP_OUT_D
DR_SD
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5733L
SLASE77A –MARCH 2016–REVISED MARCH 2016
TAS5733L - Digital Input Audio Power Amplifier with EQ and 3-Band AGL
1
1 Features
1• Audio Input/Output
– One-Stereo Serial Audio Input
– Supports 44.1-kHz and 48-kHz Sample Rates
(LJ/RJ/I²S)
– Supports 3-Wire I²S Mode (no MCLK required)
– Automatic Audio Port Rate Detection
– Supports BTL and PBTL Configuration
– POUT = 10 W @ 10% THD+N
– PVDD = 12 V, 8 Ω, 1 kHz
• Audio/PWM Processing
– Independent Channel Volume Controls With
Gain of 24 dB to Mute in 0.125-dB Steps
– Programmable Three-Band Automatic Gain
Limiting (AGL)
– 20 Programmable Biquads for Speaker EQ
and Other Audio-Processing Features
• General Features
– 104-dB SNR, A-Weighted, Referenced to Full
Scale (0 dB)
– I²C Serial Control Interface w/ two Addresses
– Thermal, Short-Circuit, and Undervoltage
Protection
– Up to 90% Efficient
– AD, BD, and Ternary Modulation
– PWM Level Meter
2 Applications
• LCD TV, LED TV
• Low-Cost Audio Equipment
3 Description
The TAS5733L device is an efficient, digital-input
audio amplifier for driving stereo speakers configured
as a bridge tied load (BTL). In parallel bridge tied
load (PBTL) in can produce higher power by driving
the parallel outputs into a single lower impedance
load. One serial data input allows processing of up to
two discrete audio channels and seamless integration
to most digital audio processors and MPEG
decoders. The device accepts a wide range of input
data and data rates. A fully programmable data path
routes these channels to the internal speaker drivers.
The TAS5733L device is a slave-only device
receiving all clocks from external sources. The
TAS5733L device operates with a PWM carrier
between a 384-kHz switching rate and a 288-kHz
switching rate, depending on the input sample rate.
Oversampling combined with a fourth-order noise
shaper provides a flat noise floor and excellent
dynamic range from 20 Hz to 20 kHz.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TAS5733L HTSSOP (48) 12.50 mm × 6.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Power vs PVDD Simplified Block Diagram

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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Characteristics............................................ 6
6.5 Electrical Characteristics........................................... 6
6.6 Speaker Amplifier Characteristics............................. 7
6.7 Protection Characteristics......................................... 7
6.8 Master Clock Characteristics .................................... 7
6.9 I²C Interface Timing Requirements........................... 8
6.10 Serial Audio Port Timing Requirements.................. 8
6.11 Typical Characteristics - Stereo BTL Mode .......... 11
6.12 Typical Characteristics - Mono PBTL Mode ......... 13
7 Detailed Description............................................ 15
7.1 Overview................................................................. 15
7.2 Functional Block Diagram....................................... 15
7.3 Audio Signal Processing Overview......................... 16
7.4 Feature Description................................................. 17
7.5 Device Functional Modes........................................ 19
7.6 Programming........................................................... 20
7.7 Register Maps......................................................... 31
8 Application and Implementation ........................ 49
8.1 Application Information............................................ 49
8.2 Typical Applications ............................................... 50
9 Power Supply Recommendations...................... 55
10 Layout................................................................... 56
10.1 Layout Guidelines ................................................. 56
10.2 Layout Example .................................................... 57
11 Device and Documentation Support................. 59
11.1 Trademarks........................................................... 59
11.2 Electrostatic Discharge Caution............................ 59
11.3 Glossary................................................................ 59
12 Mechanical, Packaging, and Orderable
Information........................................................... 60
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2016) to Revision A Page
• Moved from Product Preview to Production Data release. ................................................................................................... 1

PowerPADTM
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48
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BSTRP_B
AMP_OUT_B
AMP_OUT_B
PGND
PGND
AMP_OUT_A
PVDD
PVDD
BSTRP_A
SSTIMER
PBTL
NC
NC
PLL_GND
PLL_FLTM
PLL_FLTP
AVDD _REF
AVDD
ADR / FAULT
MCLK
OSC_RES
OSC _GND
DVDD_REG
PDN
BSTRP_C
AMP_OUT_C
AMP_OUT_C
PGND
PGND
AMP_OUT_D
PVDD
PVDD
BSTRP_D
GVDD_REG
AVDD_ REG
NC
NC
AGND
DGND
DVDD
TEST
RST
NC
SCL
SDA
SDIN
SCLK
LRCLK
3
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(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
5 Pin Configuration and Functions
DCA Package
48-Pin HTSSOP With PowerPAD™
Top View
Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
ADR/FAULT 19 DI/DO Dual function terminal which sets the LSB of the I²C Address to 0 if pulled to GND, 1 if pulled to AVDD. Also, if configured to be a fault output by the methods described in the
Fault Indication section, this terminal will be pulled low when an internal fault occurs.
AGND 35 P Ground reference for analog circuitry (NOTE: This terminal should be connected to the
system ground)
AMP_OUT_A 6
AO Speaker amplifier outputs
AMP_OUT_B 2
3
AMP_OUT_C 46
47
AMP_OUT_D 43
AVDD 18 P Power supply for internal analog circuitry
AVDD_REF 17 P Internal power supply (NOTE: This terminal is provided as a connection point for filtering
capacitors for this supply and must not be used to power any external circuitry)
AVDD_REG 38 P Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power
any external circuitry)
BSTRP_A 9
PConnection points to for the bootstrap capacitors, which are used to create a power
supply for the gate drive for the high-side device
BSTRP_B 1
BSTRP_C 48
BSTRP_D 40
DGND 34 P Ground reference for digital circuitry (NOTE: This terminal should be connected to the
system ground)
DVDD 33 P Power supply for the internal digital circuitry
DVDD_REG 23 P Voltage regulator derived from DVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power
any external circuitry)
GVDD_REG 39 P Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power
any external circuitry)
LRCLK 25 DI Word select clock for the digital signal that is active on the input data line of the serial
port

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Pin Functions (continued)
PIN TYPE(1) DESCRIPTION
NAME NO.
(2) Although these pins are not connected internally, optimum thermal performance is realized when these pins are connected to the ground
plane. Doing so allows copper on the PCB to fill up to and including these pins, providing a path for heat to conduct away from the
device and into the surrounding PCB area.
MCLK 20 DI Master clock used for internal clock tree and sub-circuit/state machine clocking
NC(2)
12
PNot connected inside the device (all "no connect" terminals should be connected to
system ground)
13
30
36
37
OSC_GND 22 P Ground reference for oscillator circuitry (NOTE: These terminals should be connected to
the system ground)
OSC_RES 21 AO Connection point for precision resistor used by internal oscillator circuit. Details for this
resistor are shown in the Typical Applications section
PBTL 11 DI Places the power stage in BTL mode when pulled low, or in PBTL mode when pulled
high
PDN 24 DI Places the device in power down when pulled low
PGND
4
—Ground reference for power device circuitry (NOTE: This terminal should be connected
to the system ground)
5
44
45
PLL_FLTM 15 AO Negative connection point for the PLL loop filter components
PLL_FLTP 16 AO Positive connection point for the PLL loop filter components
PLL_GND 14 P Ground reference for PLL circuitry (NOTE: This terminal should be connected to the
system ground)
PVDD
7
P Power supply for internal power circuitry
8
41
42
RST 31 DI Places the devices in reset when pulled low
SCL 29 DI I²C serial control port clock
SCLK 26 DI Bit clock for the digital signal that is active on the input data line of the serial data port
SDA 28 DI/DO I²C serial control port data
SDIN 27 DI Data line to the serial data port
SSTIMER 10 AO Connection point for the capacitor that is used by the ramp timing circuit, as described in
the SSTIMER Pin Functionality section
TEST 32 — Used by TI for testing during device production (NOTE: This terminal should be
connected to system ground)
PowerPAD — P Exposed metal pad on the underside of the device, which serves as an electrical
connection point for ground as well as a heat conduction path from the device into the
board (NOTE: This terminal should be connected to ground through a land pattern
defined in the Mechanical Data section)

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RST, SCLK, LRCK, MCLK, SDIN, SDA, and SCL.
(3) Maximum pin voltage should not exceed 6 V.
(4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
Supply voltage DVDD, AVDD –0.3 to 3.6 V
PVDD –0.3 to 20
Input voltage 3.3-V digital input –0.5 to DVDD + 0.5 V5-V tolerant(2) digital input (except MCLK) –0.5 to DVDD + 2.5(3)
5-V tolerant MCLK input –0.5 to AVDD + 2.5(3)
AMP_OUT_x to GND 22(4) V
BSTRP_x to GND 29(4) V
Operating free-air temperature 0 to 85 °C
Storage temperature range, Tstg –40 to 125 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) ±1500
(1) For operation at PVDD levels greater than 14.5 V, the modulation limit must be set to 96.1% or lower via the control port register 0x10.
(2) 16.5 V is the maximum recommended voltage for continuous operation of the TAS5733L device. Testing and characterization of the
device is performed up to and including 16.5 V to ensure “in system” design margin. However, continuous operation at these levels is
not recommended. Operation above the maximum recommended voltage may result in reduced performance, errant operation, and
reduction in device reliability.
6.3 Recommended Operating Conditions MIN NOM MAX UNIT
DVDD, AVDD Digital, analog supply voltage 3 3.3 3.6 V
PVDD Output power devices supply voltage 8 16.5(1)
(2) V
VIH High-level input voltage 5-V tolerant 2 V
VIL Low-level input voltage 5-V tolerant 0.8 V
TAOperating ambient temperature range 0 85 °C
TJ(2) Operating junction temperature range 0 125 °C
RLLoad impedance 4 8 Ω
RLLoad impedance in PBTL 2 Ω
LOOutput-filter inductance Minimum output inductance under
short-circuit condition 10 μH

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
6.4 Thermal Characteristics
THERMAL METRIC(1)
DCA (48 PINS)
UNITS
Special Test
Case
JEDEC
Standard 2-
Layer PCB
JEDEC
Standard 4-
Layer PCB
TAS5733LEVM
θJA Junction-to-ambient thermal resistance(2) 50.7 27.6 25.0 °C/W
θJCtop Junction-to-case (top) thermal resistance(3) 14.9 16.7 °C/W
θJB Junction-to-board thermal resistance(4) 6.9 7.9 °C/W
ψJT Junction-to-top characterization parameter(5) 1.2 0.8 0.7 °C/W
ψJB Junction-to-board characterization parameter(6) 11.8 7.8 5.8 °C/W
θJCbot Junction-to-case (bottom) thermal resistance(7) 1.7 2.2 °C/W
6.5 Electrical Characteristics
TA= 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL BD mode, fS= 48 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage ADR/FAULT and SDA
IOH = –4 mA
DVDD = AVDD = 3 V 2.4 V
VOL Low-level output voltage IOL = 4 mA
DVDD = AVDD = 3 V 0.5 V
IIL Low-level input current Digital Inputs
VI< VIL
DVDD = AVDD = 3.6 V 75 μA
IIH High-level input current VI> VIH
DVDD = AVDD = 3.6 V 75 μA
IDD 3.3-V supply current 3.3-V supply voltage
(DVDD, AVDD)
Normal mode 49 68 mA
Reset (RST = low, PDN =
high) 23 38

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(1) This does not include bond-wire or pin resistance.
6.6 Speaker Amplifier Characteristics
PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, fS= 48 KHz, RL= 8 Ω, audio frequency = 1 kHz, AES17 filter, fPWM =
384 kHz, TA= 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions
and as tested on the TAS5733L EVM.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POPower output per channel
PVDD = 12 V, 10% THD, 1-kHz input signal 10
W
PVDD = 12 V, 7% THD, 1-kHz input signal 9
PVDD = 12 V, 1% THD, 1-kHz input signal 7.5
PVDD = 13.2 V, 10% THD, 1-kHz input signal 12
PVDD = 13.2 V, 7% THD, 1-kHz input signal 11
PVDD = 13.2 V, 1% THD, 1-kHz input signal 9
THD+N Total harmonic distortion +
noise PVDD = 12 V, PO= 1 W 0.25 %
PVDD = 13.2 V, PO= 1 W 0.3
VnOutput integrated noise (rms) A-weighted 30 μV
Crosstalk PO= 1 W, f = 1 kHz (BD Mode), PVDD = 12 V –79 dB
PO=1 W, f = 1 kHz (AD Mode), PVDD = 12 V –62 dB
Output switching frequency 11.025, 22.05, 44.1-kHz data rate ±2% 288 kHz
48, 24, 12, 8, 16, 32-kHz data rate ±2% 384
IPVDD Supply current No load (PVDD) Normal mode 16 25 mA
Reset (RST = low, PDN = high) 3 8
rDS(on)(1)
Drain-to-source resistance,
low side TJ= 25°C, includes metallization resistance 120 mΩ
Drain-to-source resistance,
high side TJ= 25°C, includes metallization resistance 120
RPD Internal pulldown resistor at
the output of each half-bridge Connected when drivers are in the high-impedance state to provide bootstrap capacitor charge. 3 kΩ
6.7 Protection Characteristics
TA= 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL BD mode, fS= 48 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vuvp(fall) Undervoltage protection limit PVDD falling 5.4 V
Vuvp(rise) Undervoltage protection limit PVDD rising 5.8 V
OTE Overtemperature error 150 °C
IOC Overcurrent limit protection 4 A
IOCT Overcurrent response time 150 ns
(1) For clocks related to the serial audio port, please see Serial Audio Port Timing Requirements.
6.8 Master Clock Characteristics(1)
PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, fS= 48 kHz, RL= 8 Ω, audio frequency = 1 kHz, AES17 filter, fPWM =
384 kHz, TA= 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions
(unless otherwise specified).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLL INPUT PARAMETERS
fMCLKI MCLK frequency 2.8224 24.576 MHz
MCLK duty cycle 40% 50% 60%
tr/ tf(MCLK) Rise/fall time for MCLK 5 ns

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6.9 I²C Interface Timing Requirements MIN NOM MAX UNIT
tw(RST) Pulse duration, RST active 100 μs
td(I²C_ready) Time to enable I²C after RST goes high 13.5 ms
fSCL Frequency, SCL 400 kHz
tw(H) Pulse duration, SCL high 0.6 μs
tw(L) Pulse duration, SCL low 1.3 μs
trRise time, SCL and SDA 300 ns
tfFall time, SCL and SDA 300 ns
tsu1 Setup time, SDA to SCL 100 ns
th1 Hold time, SCL to SDA 0 ns
t(buf) Bus free time between stop and start conditions 1.3 μs
tsu2 Setup time, SCL to start condition 0.6 μs
th2 Hold time, start condition to SCL 0.6 μs
tsu3 Setup time, SCL to stop condition 0.6 μs
CLLoad capacitance for each bus line 400 pF
6.10 Serial Audio Port Timing Requirements
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fSCL≤30 pF 1.024 12.28
8MHz
tsu1 Setup time, LRCK to SCLK rising edge 10 ns
th1 Hold time, LRCK from SCLK rising edge 10 ns
tsu2 Setup time, SDIN to SCLK rising edge 10 ns
th2 Hold time, SDIN from SCLK rising edge 10 ns
LRCK frequency 8 48 48 kHz
SCLK duty cycle 40% 50% 60%
LRCK duty cycle 40% 50% 60%
SCLK rising edges between LRCK rising edges 32 64 SCLK
edges
t(edge) LRCK clock edge with respect to the falling edge of SCLK –1/4 1/4 SCLK
period
tr/tfRise/fall time for SCLK/LRCK 8 ns
LRCK allowable drift before LRCK reset 4 MCLKs

SCL
SDA
th2 t(buf)
tsu2 tsu3
Start
Condition
Stop
Condition
T0028-01
SCL
SDA
tw(H) tw(L) trtf
tsu1 th1
T0027-01
tw(RST)
RST
td(I2C_ready)
System Initialization.
Enable via I C.
2
T0421-01
I C Active
2I C Active
2
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NOTE: On power up, hold the TAS5733L RST LOW for at least 100 μs after DVDD has reached 3 V.
NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is
deasserted (HIGH).
Figure 1. Reset Timing
Figure 2. SCL and SDA Timing
Figure 3. Start and Stop Conditions Timing

th1
tsu1
t(edge)
tsu2
th2
SCLK
(Input)
LRCLK
(Input)
SDIN
T0026-04
trtf
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Figure 4. Serial Audio Port Timing

Frequency (Hz)
THD+N (%)
0.001
0.01
0.1
1
55
20 100 1k 10k 20k
D003
1 W
2.5 W
5 W
Output Power (W)
THD+N (%)
0.01 0.1 1 10 50
0.01
0.1
1
10
D001
20 Hz
1 kHz
7 kHz
Frequency (Hz)
THD+N (%)
0.002
0.01
0.1
1
10
20 100 1k 10k 20k
D001
1 W
2.5 W
5 W
Frequency (Hz)
THD+N (%)
0.002
0.01
0.1
1
10
10 100 1k 10k 20k
D002
1 W
2.5 W
5 W
PVDD (V)
Output Power (W)
8 9 10 11 12 13 14 15
0
5
10
15
20
25
30
D007
THD+N = 10%; 8 Ohms
THD+N = 1%; 8 Ohms
THD+N = 10%; 6 Ohms
THD+N = 1%; 6 Ohms
THD+N = 10%; 4 Ohms
THD+N = 1%; 4 Ohms
PVDD (V)
Idle Channel Noise (µV)
8 9 10 11 12 13 14 15
0
5
10
15
20
25
30
35
40
45
50
D012
8 Ohms
6 Ohms
4 Ohms
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6.11 Typical Characteristics - Stereo BTL Mode
Figure 5. Output Power vs Supply Voltage - BTL Figure 6. Idle Channel Noise vs Supply Voltage - BTL
PVDD = 12 V RL= 8 Ω
Figure 7. THD+N vs Frequency - BTL
PVDD = 12 V RL= 6 Ω
Figure 8. THD+N vs Frequency - BTL
PVDD = 12 V RL= 4 Ω
Figure 9. THD+N vs Frequency - BTL
PVDD = 12 V RL= 8 Ω
Figure 10. THD+N vs Output Power - BTL

Frequency (Hz)
Crosstalk (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
20 100 1k 10k 20k
D010
Right to Left
Left to Right
Frequency (Hz)
Crosstalk (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
20 100 1k 10k 20k
D011
Right to Left
Left to Right
Total Output Power (W)
Efficiency (%)
0 5 10 15 20 25
0
10
20
30
40
50
60
70
80
90
100
D008
PVDD = 8 V
PVDD = 12 V
PVDD = 13.2 V
Output Power (W)
Efficiency (%)
0 5 10 15 20 25 30 35 40 45 50
0
10
20
30
40
50
60
70
80
90
100
D009
PVDD = 8 V
PVDD = 12 V
PVDD = 13.2 V
Output Power (W)
THD+N (%)
0.01 0.1 1 10 50
0.001
0.01
0.1
1
10
2020
D001
20 Hz
1 kHz
7 kHz
Output Power (W)
THD+N (%)
0.01 0.1 1 10 50
0.01
0.1
1
10
D006
20 Hz
1 kHz
7 kHz
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Typical Characteristics - Stereo BTL Mode (continued)
PVDD = 12 V RL= 6 Ω
Figure 11. THD+N vs Output Power - BTL
PVDD = 12 V RL= 4 Ω
Figure 12. THD+N vs Output Power - BTL
RL= 8 Ω
Total Output Power includes power delivered from both amplifier
outputs. For instance, 40 W of total output power means 2 × 20 W,
with 20 W delivered by one channel and 20 W delivered by the
other channel.
Figure 13. Efficiency vs Total Output Power - BTL
RL= 4 Ω
Total Output Power includes power delivered from both amplifier
outputs. For instance, 40 W of total output power means 2 × 20 W,
with 20 W delivered by one channel and 20 W delivered by the
other channel.
Figure 14. Efficiency vs Total Output Power - BTL
PVDD = 12 V RL= 8 Ω
Figure 15. Crosstalk vs Frequency - BTL
PVDD = 12 V RL= 4 Ω
Figure 16. Crosstalk vs Frequency - BTL

Output Power (W)
THD+N (%)
0.001 0.01 0.1 1 10 50
0.01
0.1
1
10
2020
D017
20 Hz
1 kHz
7 kHz
Output Power (W)
THD+N (%)
0.002 0.01 0.1 1 10 6060
0.02
0.1
1
10
2020
D018
20 Hz
1 kHz
7 kHz
Frequency (Hz)
THD+N (%)
0.001
0.01
0.1
1
10
20 100 1k 10k 20k
D015
1 W
2.5 W
5 W
Output Power (W)
THD+N (%)
0.001 0.01 0.1 1 10 50
0.01
0.1
1
10
2020
D016
20 Hz
1 kHz
7 kHz
Frequency (Hz)
THD+N (%)
0.001
0.01
0.1
1
10
20 100 1k 10k 20k
D013
1 W
2.5 W
5 W
Frequency (Hz)
THD+N (%)
0.001
0.01
0.1
1
55
20 100 1k 10k 20k
D014
1 W
2.5 W
5 W
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6.12 Typical Characteristics - Mono PBTL Mode
PVDD = 12 V RL= 4 Ω
Figure 17. THD+N vs Frequency - PBTL
PVDD = 12 V RL= 3 Ω
Figure 18. THD+N vs Frequency - PBTL
PVDD = 12 V RL= 2 Ω
Figure 19. THD+N vs Frequency - PBTL
PVDD = 12 V RL= 4 Ω
Figure 20. THD+N vs Output Power - PBTL
PVDD = 12 V RL= 3 Ω
Figure 21. THD+N vs Output Power - PBTL
PVDD = 12 V RL= 2 Ω
Figure 22. THD+N vs Output Power - PBTL

Output Power (W)
Efficiency (%)
0 5 10 15 20 25 30 35 40 45
0
10
20
30
40
50
60
70
80
90
100
D021
PVDD = 8 V
PVDD = 12 V
PVDD = 13.2 V
PVDD (V)
Idle Channel Noise (µV)
8 9 10 11 12 13 14 15
0
10
20
30
40
50
60
D022
RL = 4 R
RL = 3 R
RL = 2 R
Supply Voltage (V)
Output Power (W)
8 9 10 11 12 13 14 15
0
10
20
30
40
50
60
D019
THD+N = 10%; RL = 4R
THD+N = 1%; RL = 4R
THD+N = 10%; RL = 3R
THD+N = 1%; RL = 3R
THD+N = 10%; RL = 2R
THD+N = 1%; RL = 2R
Output Power (W)
Efficiency (%)
0 5 10 15 20 25
0
20
40
60
80
100
D020
PVDD = 8 V
PVDD = 12 V
PVDD = 13.2 V
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Typical Characteristics - Mono PBTL Mode (continued)
Figure 23. Output Power vs PVDD - PBTL
RL= 4 Ω
Total Output Power includes power delivered from both amplifier
outputs. For instance, 40 W of total output power means 2 × 20 W,
with 20 W delivered by one channel and 20 W delivered by the
other channel.
Figure 24. Efficiency vs Output Power - PBTL
RL= 2 Ω
Total Output Power includes power delivered from both amplifier
outputs. For instance, 40 W of total output power means 2 × 20 W,
with 20 W delivered by one channel and 20 W delivered by the
other channel.
Figure 25. Efficiency vs Output Power - PBTL
Figure 26. Idle Channel Noise vs PVDD - PBTL

Digital Audio
Processor
(DAP)
Sample Rate
Converter
(SRC)
I²C Control Port
Internal Register/State Machine Interface
Power-On Reset
(POR)
PVDDDVDD
MCLK Monitoring
and Watchdog
AVDD
PDN RST
AMP_OUT_A
AMP_OUT_C
SDIN
MCLK
SCLK
LRCK
SCL SDA
Serial Audio Port
(SAP)
Sample Rate
Auto-Detect
PLL
Digital to PWM
Converter
(DPC)
Click & Pop
Suppression
2 Ch. PWM
Modulator
Noise Shaping
Open Loop Stereo
Stereo PWM Amplifier
Sensing & Protection
Temperature
Short Circuits
PVDD Voltage
Output Current
Fault Notification
Internal Voltage Supplies
Internal Regulation and Power Distribution
AMP_OUT_B
AMP_OUT_D
DR_SD
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7 Detailed Description
7.1 Overview
The TAS5733L device is an efficient, digital-input audio amplifier for driving stereo speakers configured as a
bridge tied load (BTL). In parallel bridge tied load (PBTL) in can produce higher power by driving the parallel
outputs into a single lower impedance load. One serial data input allows processing of up to two discrete audio
channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a
wide range of input data and data rates. A fully programmable data path routes these channels to the internal
speaker drivers.
The TAS5733L device is a slave-only device receiving all clocks from external sources. The TAS5733L device
operates with a PWM carrier between a 384-kHz switching rate and a 288-kHz switching rate, depending on the
input sample rate. Oversampling combined with a fourth-order noise shaper provides a flat noise floor and
excellent dynamic range from 20 Hz to 20 kHz.
7.2 Functional Block Diagram
Figure 27. TAS5733L Functional Block Diagram

L
R
Input
Mixer L
AGL 1
Low Band
Vol 1
Vol 2
Mixer L
AGL 4
Full Band
Mixer R
AGL 2
High Band
AGL 3
Mid Band
10 Biquads
Biquad
Biquad
2 Biquads
2 Biquads
Biquad
Biquad
10 Biquads
Biquad
0x26
0x59
0x8
0x9
0x51
0x52
0x5E
0x5A
0x5F
0x5B, 0x5C
0x60, 0x61
0x76, 0x77
0x72, 0x73
0x27 - 0x2F, 0x58
0x3B - 0x3C, 0x40
0x3E - 0x3F, 0x43
0x44 - 0x45, 0x48
0x42 - 0x41, 0x47
0x31 - 0x39, 0x5D
0x30
DC Block and LR Mixer Equalizer Multi Band AGL Full Band AGL
L
R
Master Volume,
Pre Scale,
Post Scale
0x07 - 0x57, 0x56
Master Volume
Biquad Input
Mixer R
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7.3 Audio Signal Processing Overview
Figure 28. TAS5733L Audio Process Flow

B0396-01
1 – a
rms
ABSCh1
Z–1
a
Post-DAP Processing
32-Bit Level
I C Registers
(PWM Level Meter)
2
rms
ABSCh2
Z–1 32-Bit Level
ADDR = 0x6C
ADDR = 0x6B
1 – a
a
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7.4 Feature Description
7.4.1 Clock, Autodetection, and PLL
The TAS5733L device is an I²S slave device. The TAS5733L device accepts MCLK, SCLK, and LRCK. The
digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the Clock Control
Register.
The TAS5733L device checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only
supports a 1 × fSLRCK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The
clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to
produce the internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the Clock Control Register.
The TAS5733L device has robust clock error handling that uses the built-in trimmed oscillator clock to quickly
detect changes/errors. Once the system detects a clock change/error, the system mutes the audio (through a
single-step mute) and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks
are stable, the system autodetects the new rate and reverts to normal operation. During this process, the default
volume is restored in a single step (also called hard unmute). The ramp process can be programmed to ramp
back slowly (also called soft unmute) as defined in the Volume Configuration Register.
7.4.2 PWM Section
The TAS5733L DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz.
The PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. For PVDD > 14.5 V the
modulation index must be limited to 96.1% for safe and reliable operation.
7.4.3 PWM Level Meter
The structure in Figure 29 shows the PWM level meter that can be used to study the power profile.
Figure 29. PWM Level Meter Structure
7.4.4 Automatic Gain Limiter (AGL)
The AGL scheme has three AGL blocks. One ganged AGL exists for the high-band left/right channels, the mid-
band left/right channels, and the low-band left/right channels.
The AGL input/output diagram is shown in Figure 30.

S
Z–1
Alpha Filter Structure
w
a
Output Level (dB)
Input Level (dB)
T
M0091-04
1:1 Transfer Function
Implemented Transfer Function
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Feature Description (continued)
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• Each AGL has adjustable threshold levels.
• Programmable attack and decay time constants
•Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 30. Automatic Gain Limiter
T = 9.23 format, all other AGL coefficients are 3.23 format
Figure 31. AGL Structure
Table 1. AGL Structure
α,ωTαa, ωa / αd, ωd
AGL 1 0x3B 0x40 0x3C
AGL 2 0x3E 0x43 0x3F
AGL 3 0x47 0x41 0x42
AGL 4 0x48 0x44 0x45
7.4.5 Fault Indication
ADR/FAULT is an input pin during power up. This pin can be programmed after RST to be an output by writing 1
to bit 0 of I²C register 0x05. In that mode, the ADR/FAULT pin has the definition shown in Table 2.
Any fault resulting in device shutdown is signaled by the ADR/FAULT pin going low (see Table 2). A latched
version of this pin is available on D1 of register 0x02. This bit can be reset only by an I²C write.
Table 2. ADR/FAULT Output States
ADR/FAULT DESCRIPTION
0 Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or overvoltage
error
1 No faults (normal operation)

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7.4.6 SSTIMER Pin Functionality
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shut down, the drivers are placed in the high-impedance state and transition slowly down through an internal 3-
kΩresistor, similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER
pin capacitance. Larger capacitors increase the start-up time, while smaller capacitors decrease the start-up
time. The SSTIMER pin can be left floating for BD modulation.
7.4.7 Device Protection System
7.4.7.1 Overcurrent (OC) Protection With Current Limiting
The TAS5733L device has independent, fast-reacting current detectors on all high-side and low-side power-stage
FETs. The detector outputs are closely monitored to prevent the output current from increasing beyond the
overcurrent threshold defined in the Protection Characteristics table.
If the output current increases beyond the overcurrent threshold, the device shuts down and the outputs
transition to the off or high impedance (Hi-Z) state. The device returns to normal operation once the fault
condition (i.e., a short circuit on the output) is removed. Current-limiting and overcurrent protection are not
independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent
fault, half-bridges A, B, C, and D shut down.
7.4.7.2 Overtemperature Protection
The TAS5733L device has an overtemperature-protection system. If the device junction temperature exceeds
150°C (nominal), the device enters thermal shutdown, where all half-bridge outputs enter the high-impedance
(Hi-Z) state, and ADR/FAULT asserts low if the device is configured to function as a fault output. The TAS5733L
device recovers automatically once the junction temperature of the device drops approximately 30°C.
7.4.7.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5733L device fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD
and AVDD are independently monitored. For PVDD, if the supply voltage drops below the UVP threshold, the
protection feature immediately sets all half-bridge outputs to the high-impedance (Hi-Z) state and asserts
ADR/FAULT low.
7.5 Device Functional Modes
The TAS5733L device is a digital input class-d amplifier with audio processing capabilities. The TAS5733L
device has numerous modes to configure and control the device.
7.5.1 Serial Audio Port Operating Modes
The serial audio port in the TAS5733L device supports industry-standard audio data formats, including I²S, Left-
justified(LJ) and Right-justified(RJ) formats. To select the data format that will be used with the device can
controlled by using the serial data interface registers 0x04. The default is 24bit, I²S mode. The timing diagrams
for the various serial audio port are shown in the Serial Interface Control and Timing section
7.5.2 Communication Port Operating Modes
The TAS5733L device is configured via an I²C communication port. The I²C communication protocol is detailed in
the 7.7 I²C Serial Control Port Requirements and Specifications section.

7-Bit Slave Address R/
W8-Bit Register Address (N)
A8-Bit Register Data For
Address (N)
Start Stop
SDA
SCL
765432 1 0765432 1 0765432 1 0765432 1 0
A8-Bit Register Data For
Address (N)
A A
T0035-01
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Device Functional Modes (continued)
7.5.3 Speaker Amplifier Modes
The TAS5733L device can be configured as:
• Stereo Mode
• Mono Mode
7.5.3.1 Stereo Mode
Stereo mode is the most common option for the TAS5733L. TAS5733L can be connected in 2.0 mode to drive
stereo channels. Detailed application section regarding the stereo mode is discussed in the Stereo Bridge Tied
Load Application section.
7.5.3.2 Mono Mode
Mono mode is described as the operation where the two BTL outputs of amplifier are placed in parallel with one
another to provide increase in the output power capability. This mode is typically used to drive subwoofers, which
require more power to drive larger loudspeakers with high-amplitude, low-frequency energy. Detailed application
section regarding the mono mode is discussed in the Mono Parallel Bridge Tied Load Application section.
7.6 Programming
7.6.1 I²C Serial Control Interface
The TAS5733L device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I²C bus operation (100 kHz maximum) and the fast I²C bus operation
(400 kHz maximum). The DAP performs all I²C operations without I²C wait cycles.
7.6.1.1 General I²C Operation
The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 32. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5733L device holds SDA low during the
acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte
of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor
must be used for the SDA and SCL signals to set the high level for the bus.
Figure 32. Typical I²C Sequence