Texas Instruments TPA3122D2 User manual

1
FEATURES APPLICATIONS
DESCRIPTION
1 Fm
SD
Mute Control
PVCCL
TPA3122D2
SIMPLIFIED APPLICATION CIRCUIT
PVCCR
VCLAMP
GAIN1
BYPASS
1 Fm
1 Fm
0.22 Fm
AGND
Left Channel
Right Channel
10 V to 30 V
10 V to 30 V
}
4-Step Gain
Control
Shutdown
Control
LIN
RIN
BSR
BSL
PGNDR
PGNDL
0.22 Fm
22 Hm
22 Hm
0.68 Fm
470 Fm
0.68 Fm
1 Fm
470 Fm
GAIN0
AVCC
MUTE
ROUT
LOUT
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007www.ti.com
15-W STEREO CLASS-D AUDIO POWER AMPLIFIER
•Televisions•10-W/ch into an 4- ΩLoad From a 17-V Supply•15-W/ch into an 8- ΩLoad From a 28-V Supply•Operates from 10 V to 30 V
The TPA3122D2 is a 15-W (per channel) efficient,•Efficient Class-D Operation
Class-D audio power amplifier for driving stereo•Four Selectable, Fixed Gain Settings
single ended speakers or mono bridge tied load. The•Internal Oscillator (No External Components
TPA3122D2 can drive stereo speakers as low as 4 Ω.Required) The efficiency of the TPA3122D2 eliminates the needfor an external heat sink when playing music.•Single Ended Analog Inputs
The gain of the amplifier is controlled by two gain•Thermal and Short-Circuit Protection with
select pins. The gain selections are 20, 26, 32, andAuto Recovery Feature
36 dB.•20-pin DIP Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PVCCL
SD
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
N (DIP) PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION20-PINNAME
(DIP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance toSD 2 I
AVCC.RIN 5 I Audio input for right channel.LIN 4 I Audio input for left channel.GAIN0 15 I Gain select least significant bit. TTL logic levels with compliance to AVCC.GAIN1 14 I Gain select most significant bit. TTL logic levels with compliance to AVCC.Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle; low =MUTE 3 I
outputs enabled). TTL logic levels with compliance to AVCC.BSL 18 I/O Bootstrap I/O for left channel.PVCCL 1 Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.LOUT 19 O Class-D -H-bridge positive output for left channel.PGNDL 20 Power ground for left channel H-bridge.VCLAMP 9 Internally generated voltage supply for bootstrap capacitors.BSR 13 I/O Bootstrap I/O for right channel.ROUT 12 O Class-D -H-bridge negative output for right channel.PGNDR 11 Power ground for right channel H-bridge.PVCCR 10 Power supply for right channel H-bridge, not connected to PVCCL or AVCC.AGND 8 Analog ground for digital/analog cells in core.AGND 7 Analog Ground for analog cells in core.Reference for pre-amplifier inputs. Nominally equal to AVCC/8. Also controls start-up time viaBYPASS 6 O
external capacitor sizing.AVCC 16, 17 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
V
CC
Supply voltage, AVCC, PVCC – 0.3 to 36 VV
I
Logic input voltage SD, MUTE, GAIN0, GAIN1 – 0.3 to V
CC
+0.3 – 0.3 to V
CC
+0.3 VV
IN
Analog input voltage RIN, LIN – 0.3 to 7 VContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range – 40 to 85 °CT
J
Operating junction temperature range – 40 to 150 °CT
stg
Storage temperature range -65 to 150 °CR
L
Load resistance (Minimum value) 3.2 kVHuman body model (all pins) ± 2 kVESD Electrostatic Discharge
Charged-device model (all pins) ± 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operations of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE
(1)
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °C
20-pin DIP 1.87 W 15 mW/ °C 1.20 W 0.97 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .
MIN MAX UNIT
V
CC
Supply voltage PVCC, AVCC 10 30 VV
IH
High-level input voltage SD, MUTE, GAIN0, GAIN1 2 VV
IL
Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 VSD, V
I
= V
CC
, V
CC
= 30 V 125I
IH
High-level input current MUTE, V
I
= V
CC
, V
CC
= 30 V 125 µAGAIN0, GAIN1, V
I
= V
CC
, V
CC
= 24 V 125SD, V
I
= 0, V
CC
= 30 V 1I
IL
Low-level input current MUTE, V
I
= 0 V, V
CC
= 30 V 1 µAGAIN0, GAIN1, V
I
= 0 V, V
CC
= 24 V 1T
A
Operating free-air temperature – 40 85 °C
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DC CHARACTERISTICS
AC CHARACTERISTICS
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
T
A
= 25 °C, V
CC
= 24 V, R
L
= 4 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage| V
OS
| V
I
= 0 V, A
V
= 36 dB 7.5 50 mV(measured differentially)V
(BYPASS)
Bypass output voltage No load AV
CC
/8 VI
CC(q)
Quiescent supply current SD = 2 V, MUTE = 0 V, No load 23 37 mAI
CC(q)
Quiescent supply current in mute mode MUTE = 2 V, No load 23 mAI
CC(q)
Quiescent supply current in shutdown 1SD = 0.8 V , No load 0.39 mAmoder
DS(on)
Drain-source on-state resistance 200 m Ω
Gain0 = 0.8 V 18 20 22Gain1 = 0.8 V
Gain0 = 2 V 24 26 28G Gain dBGain0 = 0.8 V 30 32 34Gain1 = 2 V
Gain0 = 2 V 34 36 38Mute Attenuation V
I
= 1Vrms – 82
T
A
= 25 °C, V
CC
= 24V, R
L
= 4 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
= 12 V, V
ripple
= 200 mV
PP
100 Hz – 30 dBK
SVR
Supply ripple rejection
Gain = 20 dB
1 kHz -48 dBV
CC
= 12 V, R
L
= 4 Ω, f = 1 kHz 4Output Power at 1% THD+N
V
CC
= 24 V, R
L
= 8 Ω, f = 1 kHz 8P
O
WV
CC
= 12 V, R
L
= 4 Ω, f = 1 kHz 5Output Power at 10%THD+N
V
CC
= 24 V, R
L
= 8 Ω, f = 1 kHz 10R
L
= 4 Ω, f = 1 kHz, P
O
= 1 W 0.1%Total harmonic distortion +THD+N
noise
R
L
= 8 Ω, f = 1 kHz, P
O
= 1 W 0.06%
85 µVV
n
Output integrated noise floor 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
– 80 dBCrosstalk P
O
= 1 W, f = 1kHz; Gain = 20 dB – 60 dBSNR Signal-to-noise ratio Max Output at THD+N < 1%, f = 1 kHz, Gain = 20 dB 99 dBThermal trip point 150 °CThermal hysteresis 30 °Cf
OSC
Oscillator frequency 10 V ≤V
CC
230 250 270 kHzmute delay time from mute input switches high until outputs muted 120 msecΔt
unmute delay time from mute input switches low until outputs unmuted 120 msec
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LS
HS
LS
HS
OSC/RAMP
MUTE
CONTROL
BYPASS
AV
CONTROL
CONTROL
BIAS
THERMAL
SC
DETECT
SC
DETECT
AVDD
AVCC
LIN
RIN
MUTE
BYPASS
GAIN1
GAIN0
SD
BSL
PVCCL
LOUT
PGNDL
VCLAMP
BSR
PVCCR
ROUT
PGNDR
VCLAMP
VCLAMP
AVDD
AVDD
AVDD/2
AVDD
AVDD
AVDD/2
REGULATOR
AGND
+
-
+
-
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
FUNCTIONAL BLOCK DIAGRAM
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TYPICAL CHARACTERISTICS
f − Frequency − Hz
20 100 1k 20k
0.1
0.01
G001
Gain = 20 dB
RL= 4 Ω(SE)
VCC = 12 V
1
10k
THD+N − %
10
PO= 1 W PO= 0.5 W
PO= 2 W
f − Frequency − Hz
20 100 1k 20k
0.1
0.01
G002
Gain = 20 dB
RL= 4 Ω(SE)
VCC = 18 V
1
10k
THD+N − %
10
PO= 1 W
PO= 5 W
PO= 2.5 W
f − Frequency − Hz
20 100 1k 20k
0.1
0.01
G003
Gain = 20 dB
RL= 4 Ω(SE)
VCC = 24 V
1
10k
THD+N − %
10
PO= 1 W
PO= 5 W
PO= 2.5 W
f − Frequency − Hz
20 100 1k 20k
0.1
0.01
G004
Gain = 20 dB
RL= 8 Ω(SE)
VCC = 24 V
1
10k
THD+N − %
10
PO= 1 W
PO= 5 W
PO= 2.5 W
PO− Output Power − W
0.01 0.1 1 40
0.1
0.01
G005
1
10
THD+N − %
10 Gain = 20 dB
RL= 4 Ω(SE)
VCC = 12 V
VCC = 24 V
VCC = 18 V
PO− Output Power − W
0.01 0.1 1 40
0.1
0.01
G006
Gain = 20 dB
RL= 8 Ω(SE)
1
10
THD+N − %
10
VCC = 12 V
VCC = 24 V
VCC = 18 V
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY (SE) FREQUENCY (SE)
Figure 1. Figure 2.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY (SE) FREQUENCY (SE)
Figure 3. Figure 4.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsOUTPUT POWER (SE) OUTPUT POWER (SE)
Figure 5. Figure 6.
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−100
−80
−60
−40
−20
0
f − Frequency − Hz
Crosstalk − dB
G007
20 100 1k 20k10k
Gain = 20 dB
PO= 0.25 W
RL= 4 Ω (SE)
VCC = 18 V
Right to Left
Left to Right
−100
−80
−60
−40
−20
0
f − Frequency − Hz
Crosstalk − dB
G008
Gain = 20 dB
PO= 0.125 W
RL= 8 Ω (SE)
VCC = 18 V
20 100 1k 20k10k
Right to Left
Left to Right
f − Frequency − Hz
Gain − dBr A
G009
0
−200
200
400
Phase − °
100 1k 100k10k
Phase
Gain
−20
−40
0
20
VCC = 24 V
Gain = 20 dB
O
P = 0.125 W
Lfilt = 22 mH
Cfilt = 0.68 Fm
Cdc = 470 Fm
RL= 4 Ω (SE)
0
5
10
15
20
25
30
f − Frequency − Hz
Gain − dBr A
G010
0
−100
−200
−300
100
200
Phase − °
20 100 1k 200k10k
Phase
Gain
Gain = 20 dB
PO= 0.125 W
RL= 8 Ω (SE)
VCC = 18 V
Lfilt = 47 mH
Cfilt = 0.22 Fm
Cdc = 470 Fm
PVCC − Supply Voltage − V
0
5
10
15
10 12 14 16 18 20
PO− Output Power −W
G011
THD+N = 10%
THD+N = 1%
Gain = 20 dB
RL= 4 (SE)W
PVCC − Supply Voltage − V
0
2
4
6
8
10
12
14
16
18
10 12 14 16 18 20 22 24 26 28 30
PO− Output Power −W
G012
Gain = 20 dB
RL= 8 Ω (SE)
THD+N = 10%
THD+N = 1%
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
CROSSTALK CROSSTALKvs vsFREQUENCY (SE) FREQUENCY (SE)
Figure 7. Figure 8.
GAIN/PHASE GAIN/PHASEvs vsFREQUENCY (SE) FREQUENCY (SE)
Figure 9. Figure 10.
OUTPUT POWER OUTPUT POWERvs vsSUPPLY VOLTAGE (SE) SUPPLY VOLTAGE (SE)
Figure 12.NOTE: Dashed line = Thermally limited
Figure 11.
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PO− Output Power − W
0
20
40
60
80
100
01234567
Efficiency − %
G013
Gain = 20 dB
RL= 4 Ω(SE)
VCC = 12 V
PO− Output Power − W
0
20
40
60
80
100
0 2 4 6 8 10 12 14
Efficiency − %
G014
Gain = 20 dB
RL= 8 Ω(SE)
VCC = 12 V
VCC = 18 V
VCC = 24 V
PO− Total Output Power − W
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 2 4 6 8 10 12 14
ICC − Supply Current − A
G015
Gain = 20 dB
RL= 4 Ω(SE)
VCC = 12 V
PO− Total Output Power − W
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 2 4 6 8 10 12 14
ICC − Supply Current − A
G016
Gain = 20 dB
RL= 8 Ω(SE)
VCC = 18 V
VCC = 24 V
VCC = 12 V
−120
−100
−80
−60
−40
−20
0
f − Frequency − Hz
PSRR − dB
G017
Gain = 20 dB
RL= 4 Ω(SE)
VCC = 12 V
Vripple = 200 mVp-p
20 100 1k 20k10k
20 100 1k 20k10k
f − Frequency − Hz
0.1
0.01
0.001
G018
Gain = 20 dB
RL= 8 Ω (BTL)
VCC = 24 V
1
THD+N − %
10
PO= 20 W
PO= 1 W
PO= 5 W
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY EFFICIENCYvs vsOUTPUT POWER (SE) OUTPUT POWER (SE)
Figure 13. Figure 14.
SUPPLY CURRENT SUPPLY CURRENTvs vsTOTAL OUTPUT POWER (SE) TOTAL OUTPUT POWER (SE)
Figure 15. Figure 16.
POWER SUPPLY REJECTION RATIO TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY (SE) FREQUENCY (BTL)
Figure 17. Figure 18.
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−30
−20
−10
0
10
20
30
f − Frequency − Hz
Gain − dBr A
G020
−400
−500
−600
−700
−300
−200
Phase − °
20 100 1k 200k10k
Phase
Gain
Gain = 20 dB
PO= 0.125 W
RL= 8 Ω (BTL)
VCC = 24 V
Lfilt = 33 mH
Cfilt = 1 Fm
PO− Output Power − W
0.1
0.01
0.001
G019
Gain = 20 dB
RL= 8 Ω(BTL)
1
THD+N − %
10
0.01 0.1 1 5010
VCC = 24 V
VCC = 18 V
VCC = 12 V
PVCC − Supply Voltage − V
0
10
20
30
40
50
60
70
10 12 14 16 18 20 22 24 26 28 30
PO− Output Power − W
G021
Gain = 20 dB
RL= 8 Ω(BTL)
THD+N = 10%
THD+N = 1%
PO− Output Power − W
0
20
40
60
80
100
0 4 8 12 16 20 24 28
Efficiency − %
G022
Gain = 20 dB
RL= 8 Ω(BTL)
VCC = 12 V
VCC = 18 V
VCC = 24 V
PO− Total Output Power − W
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 4 8 12 16 20 24 28
ICC − Supply Current − A
G023
Gain = 20 dB
RL= 8 Ω(BTL)
VCC = 24 V
VCC = 12 V
VCC = 18 V
−120
−100
−80
−60
−40
−20
0
f − Frequency − Hz
PSRR − dB
G024
Gain = 20 dB
RL= 8 Ω(BTL)
VCC = 24 V
Vripple = 200 mVp-p
20 100 1k 20k10k
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION + NOISE GAIN/PHASEvs vsOUTPUT POWER (BTL) FREQUENCY (BTL)
Figure 19. Figure 20.
OUTPUT POWER EFFICIENCYvs vsSUPPLY VOLTAGE (BTL) OUTPUT POWER (BTL)
Figure 21. Figure 22.
SUPPLY CURRENT POWER SUPPLY REJECTION RATIOvs vsTOTAL OUTPUT POWER (BTL) FREQUENCY (BTL)
Figure 23. Figure 24.
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APPLICATION INFORMATION
CLASS-D OPERATION
Traditional Class-D Modulation Scheme
0 V
0 V
-12 V
-12 V
+12 V
+12 V
Current
OUTP
Differential Voltage
Across Load
OUTN
0 V
Supply Pumping
Gain setting via GAIN0 and GAIN1 inputs
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
This section focuses on the class-D operation of the TPA3122D2.
The TPA3122D2 operates in AD mode. There are two main configurations that may be used. For stereooperation, the TPA3122D2 should be configured in a single-ended (SE) half bridge amplifier. For monoapplications, TPA3122D2 may be used as a bridge tied load (BTL) amplifier. The traditional class-D modulationscheme, which is used in the TPA3122D2 BTL configuration, has a differential output where each output is 180degrees out of phase and changes from ground to the supply voltage, V
CC
. Therefore, the differential pre-filteredoutput varies between positive and negative V
CC
, where filtered 50% duty cycle yields0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown inFigure 25 .
Figure 25. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into anInductive Load With No Input
One issue encountered in single-ended (SE) class-D amplifier designs is supply pumping. Power-supply pumpingis a rise in the local supply voltage due to energy being driven back to the supply by operation of the class-Damplifier. This phenomenon is most evident at low audio frequencies and when both channels are operating atthe same frequency and phase. At low levels, power-supply pumping results in distortion in the audio output dueto fluctuations in supply voltage. At higher levels, pumping can cause the overvoltage protection to operate,which temporarily shuts down the audio output.
Several things can be done to relieve power-supply pumping. The lowest impact is to operate the two inputs outof phase 180 °and reverse the speaker connections. Because most audio is highly correlated, this causes thesupply pumping to be out of phase and not as severe. If this is not enough, the amount of bulk capacitance onthe supply must be increased. Also, improvement is realized by hooking other supplies to this node, thereby,sinking some of the excess current. Power-supply pumping should be tested by operating the amplifier at lowfrequencies and high output levels.
The gain of the TPA3122D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors insidethe amplifier. This causes the input impedance (Z
I
) to be dependent on the gain setting. The actual gain settingsare controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedancefrom part-to-part at the same gain may shift by ± 20% due to shifts in the actual resistance of the input resistors.
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