Texas instruments Trf7960 User manual

TRF7960

TRF7961

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SLOU186F–AUGUST 2006–REVISED AUGUST 2010

MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFID

ANALOG FRONT END AND DATA-FRAMING READER SYSTEM

Check for Samples: TRF7960,TRF7961

1 Introduction

1.1 Features

•Completely Integrated Protocol Handling •Parallel 8-Bit or Serial 4-Pin SPI Interface With

MCU Using 12-Byte FIFO

•Separate Internal High-PSRR Power Supplies

for Analog, Digital, and PA Sections Provide •Ultra-Small 32-Pin QFN Package

Noise Isolation for Superior Read Range and (5 mm ×5 mm)

Reliability •Available Tools

•Dual Receiver Inputs With AM and PM –Reference Design/EVM With Development

Demodulation to Minimize Communication Software

Holes –Source Code Available for MSP430

•Receiver AM and PM RSSI

•Reader-to-Reader Anti-Collision 1.2 APPLICATIONS

•High Integration Reduces Total BOM and Board •Secure Access Control

Area •Product Authentication

–Single External 13.56-MHz Crystal Oscillator –Printer Ink Cartridges

–MCU-Selectable Clock-Frequency Output of

RF, RF/2, or RF/4 –Blood Glucose Monitors

–Adjustable 20-mA, High-PSRR LDO for •Contactless Payment Systems

Powering External MCU •Medical Systems

•Easy to Use With High Flexibility

–Auto-Configured Default Modes for Each

Supported ISO Protocol

–12 User-Programmable Registers

–Selectable Receiver Gain and AGC

–Programmable Output Power

(100 mW or 200 mW)

–Adjustable ASK Modulation Range

(8% to 30%)

–Built-In Receiver Band-Pass Filter With

User-Selectable Corner Frequencies

•Wide Operating Voltage Range of 2.7 V to 5.5 V

•Ultra-Low-Power Modes

–Power Down <1μA

–Standby 120 μA

–Active (Rx only) 10 mA

1.3 Description

The TRF7960/61 is an integrated analog front end and data-framing system for a 13.56-MHz RFID reader

system. Built-in programming options make it suitable for a wide range of applications for proximity and

vicinity RFID systems.

The reader is configured by selecting the desired protocol in the control registers. Direct access to all

control registers allows fine tuning of various reader parameters as needed.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Tag-it is a trademark of Texas Instruments Incorporated.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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Table 1-1. PRODUCT SELECTION TABLE

PROTOCOLS

DEVICE ISO14443A/B ISO15693 Tag-it™

ISO18000-3

106 kbps 212 kbps 424 kbps 848 kbps

TRF7960 √√√√√√

TRF7961 √ √

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1 Introduction .............................................. 14.4 ELECTRICAL CHARACTERISTICS ................. 8

4.5 Application Schematic for the TRF796x EVM

1.1 Features .............................................. 1(Parallel Mode) ....................................... 9

1.2 APPLICATIONS ...................................... 14.6 Application Schematic for the TRF796x EVM (SPI

1.3 Description ........................................... 1Mode) ............................................... 10

2 Description (continued) ................................ 45 System Description ................................... 11

3 Physical Characteristics ............................... 55.1 Power Supplies ..................................... 11

3.1 Terminal Functions ................................... 55.2 Receiver –Analog Section ......................... 17

5.3 Register Descriptions ............................... 24

3.2 PACKAGING/ORDERING INFORMATION .......... 65.4 Direct Commands From MCU to Reader ........... 34

4 ELECTRICAL SPECIFICATIONS ..................... 75.5 Reader Communication Interface .................. 36

4.1 ABSOLUTE MAXIMUM RATINGS .................. 75.6 Parallel Interface Communication .................. 38

4.2 DISSIPATION RATINGS TABLE .................... 75.7 Serial Interface Communication .................... 40

4.3 RECOMMENDED OPERATING CONDITIONS ..... 75.8 External Power Amplifier Application ............... 44

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8 (Parallel)

3 (SPI)

Z – Matching

Circuit

Tx_Out

Rx_IN1

Rx_IN2

VDD_X

VDD_I/O

SYS_CLK

DATA_CLK

VDD

TRF796x MSP430

Xtal

13.56 MHz

IRQ

Xtal In

Xtal Out

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2 Description (continued)

Figure 2-1. Typical Application

A parallel or serial interface can be implemented for communication between the MCU and reader.

Transmit and receive functions use internal encoders and decoders with a 12-byte FIFO register. For

direct transmit or receive functions, the encoders / decoders can be bypassed so the MCU can process

the data in real time. The transmitter has selectable output power levels of 100 mW (20 dBm) or 200 mW

(23 dBm) into a 50-Ωload (5 -V supply) and is capable of ASK or OOK modulation. Integrated voltage

regulators ensure power-supply noise rejection for the complete reader system.

Data transmission comprises low-level encoding for ISO15693, modified Miller for ISO14443-A,

high-bit-rate systems for ISO14443 and Tag-it coding systems. Included with the data encoding is

automatic generation of SOF, EOF, CRC, and / or parity bits.

The receiver system enables AM and PM demodulation using a dual-input architecture. The receiver also

includes an automatic gain control option and selectable gain. Also included is a selectable bandwidth to

cover a broad range of input sub-carrier signal options. The received signal strength for AM and PM

modulation is accessible via the RSSI register. The receiver output is a digitized sub-carrier signal among

a selectable protocol and bit rate as outlined in Table 5-11. A selected decoder delivers bit stream and a

data clock as outputs.

The receiver system also includes a framing system. This system performs CRC and / or parity check,

removes the EOF and SOF settings, and organizes the data in bytes. Framed data is then accessible to

the MCU via a 12-byte FIFO register and MCU interface. The framing supports ISO14443 and ISO15693

protocols.

The TRF7960/61 supports data communication levels from 1.8 V to 5.5 V for the MCU I/O interface, while

also providing a data synchronization clock. An auxiliary 20-mA regulator (pin 32) is available for

additional system circuits.

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3 Physical Characteristics

3.1 Terminal Functions

Figure 3-1. TRF796x Pin Assignments (Top View)

Table 3-1. Terminal Functions

TERMINAL TYPE(1) DESCRIPTION

NAME NO.

VDD_A 1 OUT Internal regulated supply (2.7 V –3.4 V) for analog circuitry

VIN 2 SUP External supply input to chip (2.7 V –5.5 V)

VDD_RF 3 OUT Internal regulated supply (2.7 V –5 V), normally connected to VDD_PA (pin 4)

VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3)

TX_OUT 5 OUT RF output (selectable output power, 100 mW at 8 Ωor 200 mW at 4 Ω, with VDD = 5 V)

VSS_RF 6 SUP Negative supply for PA; normally connected to circuit ground

VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground

RX_IN1 8 INP RX input, used for AM reception

RX_IN2 9 INP RX input, used for PM reception

VSS 10 SUP Chip substrate ground

BAND_GAP 11 OUT Band-gap voltage (1.6 V); internal analog voltage reference; must be ac-bypassed to ground.

Also can be configured to provide the received analog signal output (ANA_OUT)

ASK/OOK 12 BID Direct mode, selection between ASK and OOK modulation (0 = ASK, 1 = OOK)

IRQ 13 OUT Interrupt request

MOD 14 INP Direct mode, external modulation input

VSS_A 15 SUP Negative supply for internal analog circuits; normally connected to circuit ground

Supply for I/O communications (1.8 V –5.5 V). Should be connected to VIN for 5-V

VDD_I/O 16 SUP communication, VDD_X for 3.3-V communication, or any other voltage from 1.8 V to 5.5 V.

I/O_0 17 BID I/O pin for parallel communication

I/O_1 18 BID I/O pin for parallel communication

I/O_2 19 BID I/O pin for parallel communication

I/O_3 20 BID I/O pin for parallel communication

I/O_4 21 BID I/O pin for parallel communication

(1) SUP = Supply, INP = Input, BID = Bi-directional, OUT = Output

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Table 3-1. Terminal Functions (continued)

TERMINAL TYPE(1) DESCRIPTION

NAME NO.

I/O pin for parallel communication

I/O_5 22 BID Strobe out clock for serial communication

Data clock output in direct mode

I/O pin for parallel communication

I/O_6 23 BID MISO for serial communication (SPI)

Serial bit data output in direct mode 1 or sub-carrier signal in direct mode 0

I/O pin for parallel communication.

I/O_7 24 BID MOSI for serial communication (SPI)

Pulse enable and selection of power down mode. If EN2 is connected to VIN, then VDD_X is

EN2 25 INP active during power down to support the MCU. Pin can also be used for pulse wake-up from

power-down mode.

DATA_CLK 26 INP Clock input for MCU communication (parallel and serial)

Clock for MCU (3.39 / 6.78 / 13.56 MHz) at EN = 1 and EN2 = don't care

SYS_CLK 27 OUT If EN = 0 and EN2 = 1, then system clock is set to 60 kHz

EN 28 INP Chip enable input (If EN = 0, then chip is in power-down mode).

VSS_D 29 SUP Negative supply for internal digital circuits; normally connected to circuit ground

OSC_OUT 30 OUT Crystal oscillator output

OSC_IN 31 INP Crystal oscillator input

VDD_X 32 OUT Internally regulated supply (2.7 V –3.4 V) for external circuitry (MCU)

Thermal Pad Connected to circuit ground

3.2 PACKAGING/ORDERING INFORMATION(1)

PACKAGED DEVICES PACKAGE TYPE (2) TRANSPORT MEDIA QUANTITY

TRF7960RHBT Tape and reel 250

RHB-32

TRF7960RHBR Tape and reel 3000

TRF7961RHBT Tape and reel 250

RHB-32

TRF7961RHBR Tape and reel 3000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package .

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4 ELECTRICAL SPECIFICATIONS

4.1 ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)(1)

VALUE UNIT

VIN Supply voltage 6 V

IOOutput current 150 mA

Continuous power dissipation See Dissipation Ratings Table

Maximum junction temperature, any condition(2) 140 °C

TJMaximum junction temperature, continuous operation, long-term reliability(2) 125 °C

Tstg Storage temperature range –55 to 150 °C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C

HBM (human body model) 2 kV

ESDS rating CDM (charged device model) 500 V

MM (machine model) 200

(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may

cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are

stress ratings only and functional operation of the device at these or any other conditions beyond those specified are not implied.

(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability and/or lifetime of the device.

4.2 DISSIPATION RATINGS TABLE

POWER RATING(2)

θJC θJA (1)

PACKAGE (°C/W) (°C/W) TA≤25°C TA= 85°C

RHB (32) 31 36.4 2.7 W 1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB.

(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially.

Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and

long-term reliability.

4.3 RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT

VIN Supply voltage 2.7 5 5.5 V

TJOperating virtual junction temperature range –40 125 °C

TAOperating ambient temperature range –40 25 110 °C

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4.4 ELECTRICAL CHARACTERISTICS

over temperature range VS= 5 V (unless otherwise noted) TYP

–40°C

PARAMETER CONDITIONS MIN/

25°C TO UNIT MAX

110°C

IPD Supply current in power-down mode All systems disabled, including supply-voltage regulators 1 10 μA MAX

The reference voltage generator and the VDD_X remain

IPD2 Supply current in power-down mode 2 120 300 μA MAX

active to support external circuitry.

Oscillator running, supply-voltage regulators in

ISTBY Supply current in standby mode 1.5 4 mA MAX

low-consumption mode

Supply current without antenna driver Oscillator, regulators, Rx and AGC, are all active. Tx is

ION1 10 16 mA MAX

current off.

Supply current with antenna driver Oscillator, regulators, Rx, AGC, and Tx are all active.

ION2 70 mA MAX

current Pout = 100 mW.

Supply current with antenna driver Oscillator, regulators, Rx, AGC, and Tx are all active.

ION3 120 mA MAX

current Pout = 200 mW.

1.4 MIN

BG Band Gap voltage Internal analog reference voltage 1.6 V

1.7 MAX

1.4 MIN

VPOR Power on reset voltage (POR) 2 V

2.5 MAX

3.1 MIN

VDD_A Regulated supply for analog circuitry 3.5 V

3.8 MAX

4 MIN

VDD_RF Regulated supply for RF circuitry Regulator set for 5-V system with 250-mV difference. 4.6 V

5.2 MAX

3.1 MIN

VDD_X Regulated supply for external circuitry 3.4 V

3.8 MAX

The difference between the external supply and the

Rejection of external supply noise on

PPSRR regulated voltage is higher than 250 mV. Measured at 26 20 dB MIN

the supply VDD_RF regulator 212 kHz.

Half-power mode 8 12 ΩMAX

RRFOUT PA driver output resistance Full- power mode 4 6 ΩMAX

5 MIN

RRFIN RX_IN1 and RX_IN2 input resistance 10 kΩ

20 MAX

VRFIN Maximum input voltage At RX_IN1 and RX_IN2 inputs 3.5 VPP MAX

fSUB-CARRIER = 424 kHz 1.2 2.5 mVPP MAX

VSENS Input sensitivity fSUB-CARRIER = 848 kHz 1.2 3 mVPP MAX

tSET_PD Set up time after power down 10 20 ms MAX

tSET_STBY Set up time after standby mode 30 100 μs MAX

Recovery time after modulation

tREC Modulation signal: sine, 424-kHz, 10-mVpp 60 μs MAX

(ISO14443)

30 MIN

fSYS_CLK SYS_CLK frequency In PD2 mode EN = 0 and EN2 = 1 60 kHz

120 MAX

CLKMAX Maximum CLK frequency 2 MHz TYP

VIL Input logic low 0.2 0.2 VDD_I/O MAX

VIH Input logic high 0.8 VDD_I/O MIN

ROUT Output resistance I/O_0 to I/O_7 low_io = H for VDD_I/O <2.7 V 400 800 ΩMAX

RSYS_CLK Output resistance SYS_CLK low_io = H for VDD_I/O <2.7 V 200 400 ΩMAX

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Test Port

Ext Ant Port

TRF796x

RHB - 32

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

Thermal Pad

VDD_X

OSC_IN

OSC_OUT

VSS_D

SYS_CLK

DATA_CLK

EN2

VDD_I / O

VSS_A

MOD

IRQ

ASK / OOK

BAND GAP

VSS

RX2_PM

RX1_AM

VDD_A

VSS_RX

VSS_RF

TX_OUT

VDD_PA

VDD_RF

VIN

I / O_0

I / O_1

I / O_2

I / O_3

I / O_4

I / O_5

I / O_6

I / O_7

1000 pF

1500 pF

680 pF

220 pF

VSWR

Adj

Phase Adj

330 nH 150 nH

Freq Adj

100 pF

27 pF

2.2 uF

10 nF

2.2 uF

0 Ohms

27 pF

13.56 MHz

VSWR Adj

DVcc

D/AVss

XIN

1 K

Reader Pwr Enable (GPIO)

Interrupt Capable GPIO

MSP430 (Family)

4.7 uF

10V

0.1 uF

1 K

CLK (GPIO)

PX.7

PX.6

PX.5

PX.4

PX.3

PX.2

PX.1

PX.0

Vcc

100

0.1 uF

2.2 uF

10 nF

10K

10 pF

Harmonic

Suppression

C1 C2´

Xtal CLCS

C1 + C2

Antenna

Circuit

Ant “Q”

Adj

R “cal”

open / short / load

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4.5 Application Schematic for the TRF796x EVM (Parallel Mode)

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Test Port

Ext Ant Port

TRF796x

RHB - 32

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

Thermal Pad

VDD_X

OSC_IN

OSC_OUT

VSS_D

SYS_CL

DATA_CLK

EN2

VDD_I / O

VSS_A

MOD

IRQ

ASK /

BAND GAP

VSS

RX2_PM

RX1_AM

VDD_A

VSS_RX

VSS_RF

TX_OUT

VDD_PA

VDD_RF

VIN

I / O_0

I / O_1

I / O_2

I / O_3

I / O_4

I / O_5

I / O_6

I / O_7

1000 pF

1500 pF

680 pF

220 pF

VSWR

Adj

Phase Adj 330 nH 150 nH

Freq Adj

100 pF

27 pF

2.2 Fµ

10 nF

2.2 Fµ

0 Ohms

27 pF

13.56 MHz

VSWR Adj

Vcc

DVcc

D/AVss

MISO

MOSI

XIN

10 K

1 K

CLK (GPIO)

Slave Select (GPIO)

Reader Pwr Enable (GPIO)

Interrupt Capable GPIO

MSP430 (Family)

4.7 F

10V

0.1 Fµ

1 K

100

0.1 Fµ

2.2 Fµ

10 nF

10 pF

Harmonic

Suppression

10 K

C1 C2´

Xtal CLCS

C1 + C2

Antenna

Circuit

Ant “Q”

Adj

R “cal”

open / short / load

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4.6 Application Schematic for the TRF796x EVM (SPI Mode)

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5 System Description

5.1 Power Supplies

The positive supply pin, VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. The positive supply input

sources three internal regulators with output voltages VDD_RF, VDD_A and VDD_X that use external bypass

capacitors for supply noise filtering. These regulators provide enhanced PSRR for the RFID reader

system.

The regulators are not independent and have common control bits for output voltage setting. The

regulators can be configured to operate in either automatic or manual mode. The automatic regulator

mode setting ensures an optimal compromise between regulator PSRR and highest possible supply

voltage for RF output power. Whereas, the manual mode allows the user to manually configure the

regulator settings.

VDD_RF The regulator VDD_RF (pin 3) is used to source the RF output stage. The voltage regulator can

be set for either 5-V or 3-V operation. When configured for the 5-V operation, the output

voltage can be set from 4.3 V to 5 V in 100-mV steps. The current sourcing capability for 5-V

operation is 150 mA maximum over the adjusted output voltage range.

When configured for 3-V operation, the output can be set from 2.7 V to 3.4 V, also in 100-mV

steps. The current sourcing capability for 3-V operation is 100 mA maximum over the adjusted

output voltage range.

VDD_A Regulator VDD_A (pin 1) supplies voltage to analog circuits within the reader chip. The voltage

setting is divided in two ranges. When configured for 5-V operation, the output voltage is fixed

at 3.5 V.

When configured for 3-V operation, the output can be set from 2.7 V to 3.4 V in 100-mV steps.

Note that when configured, both VDD_A and VDD_X regulators are configured together

(their settings are not independent).

VDD_X Regulator VDD_X (pin 32) can be used to source the digital I/O of the reader chip together with

other external system components. When configured for 5-V operation, the output voltage is

fixed at 3.4 V.

When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV

steps. The total current sourcing capability of the VDD_X regulator is 20 mA maximum over the

adjusted output range. Note that when configured, both VDD_A and VDD_X regulators are

configured together (their settings are not independent).

VDD_PA The VDD_PA pin (pin 4) is the positive supply pin for the RF output stage and is externally

connected to the regulator output VDD_RF (pin 3).

5.1.1 Negative Supply Connections

The negative supply connections are all externally connected together (to GND). The substrate connection

is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic negative supply is VSS_D (pin 29),

the RF output stage negative supply is VSS_TX (pin 6), and the negative supply for the RF receiver input is

VSS_RX (pin 7).

5.1.2 Digital I/O Interface

To allow compatible I/O signal levels, the TRF7960/61 has a separate supply input VDD_I/O (pin 16), with

an input voltage range of 1.8 V to 5.5 V. This pin is used to supply the I/O interface pins (I/O_0 to I/O_7),

IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, VDD_I/O is connected directly to

VDD_X to ensure that the I/O signal levels of the MCU are the same as the internal logic levels of the

reader.

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5.1.3 Supply Regulator Configuration

The supply regulators can be automatically or manually configured by the control bits. The available

options are shown in Table 5-1 through Table 5-4.Table 5-1 shows a 5-V system and the manual-mode

regulator settings. Table 5-2 shows manual mode for selection of a 3-V system. Table 5-3 and Table 5-4

show the automatic-mode gain settings for 5-V and 3-V systems.

The automatic mode is the default configuration. In automatic mode, the regulators are automatically set

every time the system is activated by asserting the EN input HIGH. The internal regulators are also

automatically reconfigured every time the automatic regulator selection bit is set HIGH (on the rising

edge).

The user can re-run the automatic mode setting from a state in which the automatic setting bit is already

high by changing the automatic setting bit from high to low to high. The regulator-configuration algorithm

adjusts the regulator outputs 250 mV below the VIN level, but not higher than 5 V for VDD_RF, 3.5 V for

VDD_A, and 3.4 V for VDD_X. This ensures the highest possible supply voltage for the RF output stage while

maintaining an adequate PSRR (power supply rejection ratio). As an example, the user can improve the

PSRR if there is a noisy supply voltage from VDD_X by increasing the target voltage difference across the

VDD_X regulator as shown for automatic regulator settings in Table 5-3 and Table 5-4.

Table 5-1. Supply-Regulator Setting –Manual –5-V System

Byte Option Bits Setting in Control Register Action

Address B7 B6 B5 B4 B3 B2 B1 B0

00 1 5-V system

0B 0 Manual regulator setting

0B 0 1 1 1 VDD_RF = 5 V, VDD_A = 3.5 V, and VDD_X = 3.4 V

0B 0 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.5 V, and VDD_X = 3.4 V

0B 0 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.5 V, and VDD_X = 3.4 V

0B 0 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.5 V, and VDD_X = 3.4 V

0B 0 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.5 V, and VDD_X = 3.4 V

0B 0 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.5 V, and VDD_X = 3.4 V

0B 0 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.5 V, and VDD_X = 3.4 V

0B 0 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.5 V, and VDD_X = 3.4 V

Table 5-2. Supply-Regulator Setting –Manual –3-V System

Byte Option Bits Setting in Control Register Action

Address B7 B6 B5 B4 B3 B2 B1 B0

00 0 3V system

0B 0 Manual regulator setting

0B 0 1 1 1 VDD_RF = 3.4 V, VDD_A, and VDD_X = 3.4 V

0B 0 1 1 0 VDD_RF = 3.3 V, VDD_A, and VDD_X = 3.3 V

0B 0 1 0 1 VDD_RF = 3.2 V, VDD_A, and VDD_X = 3.2 V

0B 0 1 0 0 VDD_RF = 3.1 V, VDD_A, and VDD_X = 3.1 V

0B 0 0 1 1 VDD_RF = 3.0 V, VDD_A, and VDD_X = 3.0 V

0B 0 0 1 0 VDD_RF = 2.9 V, VDD_A, and VDD_X = 2.9 V

0B 0 0 0 1 VDD_RF = 2.8 V, VDD_A, and VDD_X = 2.8 V

0B 0 0 0 0 VDD_RF = 2.7 V, VDD_A, and VDD_X = 2.7 V

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Table 5-3. Supply-Regulator Setting –Automatic –5-V System

Byte Option Bits Setting in Control Register Action

Address B7 B6 B5 B4 B3 B2(1) B1 B0

00 1 5-V system

0B 1 x 1 1 Automatic regulator setting ≉250-mV difference

0B 1 x 1 0 Automatic regulator setting ≉350-mV difference

0B 1 x 0 0 Automatic regulator setting ≉400-mV difference

(1) X are don't cares

Table 5-4. Supply-Regulator Setting –Automatic –3-V System

Byte Option Bits Setting in Control Register Action

Address B7 B6 B5 B4 B3 B2(1) B1 B0

00 0 3-V system

0B 1 x 1 1 Automatic regulator setting ≉250-mV difference

0B 1 x 1 0 Automatic regulator setting ≉350-mV difference

0B 1 x 0 0 Automatic regulator setting ≉400-mV difference

(1) X are don't cares

5.1.4 Power Modes

The chip has seven power states, which are controlled by two input pins (EN and EN2) and three bits in

the chip status control register (00h).

The main reader enable input is EN (which has a threshold level of 1 V minimum). Any input signal level

from 1.8 V to VIN can be used. When EN is set high, all of the reader regulators are enabled, together with

the 13.56-MHz oscillator, while the SYS_CLK (output clock for external micro controller) is made available.

The auxiliary-enable input EN2 has two functions. A direct connection from EN2 to VIN ensures availability

of the regulated supply (VDD_X) and an auxiliary clock signal (60 kHz) on the SYS_CLK output (same for

the case EN = 0). This mode is intended for systems in which the MCU controlling the reader is also being

supplied by the reader supply regulator (VDD_X) and the MCU clock is supplied by the SYS_CLK output of

the reader. This allows the MCU supply and clock to be available during power-down.

A second function of the EN2 input is to enable start-up of the reader system from complete power down

(EN = 0, EN2 = 0). In this case the EN input is being controlled by the MCU or other system device that is

without supply voltage during complete power down (thus unable to control the EN input). A rising edge

applied to the EN2 input (which has a 1-V threshold level) starts the reader supply system and 13.56-MHz

oscillator (identical to condition EN = 1). This start-up mode lasts until all of the regulators have settled

and the 13.56-MHz oscillator has stabilized. If the EN input is set high by the MCU (or other system

device), the reader stays active. If the EN input is not set high within 100 μs after the SYS_CLK output is

switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the

reader system returns to complete power-down mode. This option can be used to wake the reader system

from complete power down by using a push-button switch or by sending a single pulse.

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After the reader EN line is high, the other power modes are selected by control bits. The power mode

options and functions are listed in Table 5-5.

Table 5-5. Power Modes

Byte Option Bits Setting in Chip Status Control Register EN EN2 Functionality Current

Address B7 B6 B5 B4 B3 B2 B1 B0

STBY RFON RF PWR REC ON

00 0 0 Complete power down <1μA

00 0 1 VDD_X available 120 μA

SYS_CLK auxiliary frequency 60 kHz is ON

00 1 x x x 1 x All supply regulators active and in low power 1.5 mA

mode

13.56-MHz oscillator ON

SYS_CLK clock available

00 0 0 x 0 1 x All supply regulators active 3.5 mA

13.56-MHz oscillator ON

SYS_CLK clock available

00 0 0 x 1 1 x All supply regulators active 10 mA

13.56-MHz oscillator ON

SYS_CLK clock available

Receiver active

00 0 1 1 x 1 x All supply regulators active 70 mA

13.56-MHz oscillator ON (at 5 V)

SYS_CLK clock available

Receiver active

Transmitter active –half-power mode

00 0 1 0 x 1 x All supply regulators active 120 mA

13.56-MHz oscillator running (at 5 V)

SYS_CLK clock available

Receiver active

Transmitter active –full-power mode

During reader inactivity, the TRF7960/61 can be placed in power down-mode (EN = 0). The power down

can be complete (EN = 0, EN2 = 0) with no function running, or partial (EN = 0, EN2 = 1) where the

regulated supply (VDD_X) and auxiliary clock 60 kHz (SYS_CLK) are available to the MCU or other system

device.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1), the supply regulators are

activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency

is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the selected

frequency derived from the crystal oscillator. At this point, the reader is ready to communicate and perform

the required tasks. The control system (MCU) can then write appropriate bits to the chip status control

The STANDBY mode (bit 7 = 1 of register 00) is the active mode with the lowest current consumption. The

reader is capable of recovering from this mode to full operation in 100 μs.

The active mode with RF section disabled (bit 5 = 0 and bit 1 = 0 of register 00) is the next active mode

with low power consumption. The reader is capable of recovering from this mode to full operation in 25 μs.

The active mode with only the RF receiver section active (bit 1 = 1 of register 00) can be used to measure

the external RF field (as described in RSSI measurements paragraph) if reader-to-reader anticollision is

implemented.

The active mode with the entire RF section active (bit 5 = 1 of register 00) is the normal mode used for

transmit and receive operations.

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5.1.5 Timing Diagrams CHIP POWER UP TO CLOCK START

Figure 5-1. Power Up [VIN (Blue) to Crystal Start (Red)]

CHIP ENABLE TO CLOCK START

Figure 5-2. EN2 Low and EN High (Blue) to Start of System Clock (Red)

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CHIP ENABLE TO CLOCK START

Figure 5-3. EN2 High and EN Low (Blue) to Start of System Clock (Red)

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5.2 Receiver –Analog Section

The TRF7960/61 has two receiver inputs, RX_IN1 (pin 8) and RX_IN2 (pin 9). The two inputs are

connected to an external filter to ensure that AM modulation from the tag is available on at least one of the

two inputs. The external filter provides a 45°phase shift for the RX_IN2 input to allow further processing of

a received PM-modulated signal (if it appears) from the tag. This architecture eliminates any possible

communication holes that may occur from the tag to the reader.

The two RX inputs are multiplexed to two receiver channels: the main receiver and the auxiliary receiver.

Receiver input multiplexing is controlled by control bit B3 (pm-on) in the chip status control register

(address 00). The main receiver is composed of an RF-detection stage, gain, filtering with AGC, and a

digitizing stage whose output is connected to the digital processing block. The main receiver also has an

RSSI measuring stage, which measures the strength of the demodulated signal.

The primary function of the auxiliary receiver is to measure the RSSI of the modulation signal. It also has

similar RF-detection, gain, filtering with AGC, and RSSI blocks.

The default setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary

receiver (bit pm_on = 0). When a response from the tag is detected by the RSSI, values on both inputs

are measured and stored in the RSSI level register (address 0F). The control system reads the RSSI

values and switches to the stronger receiver input (RX_IN1 or RX_IN2 by setting pm_on = 1).

The receiver input stage is an RF level detector. The RF amplitude level on RX_IN1 and RX_IN2 inputs

should be approximately 3 VPP for a VIN supply level greater than 3.3 V. If the VIN level is lower, the RF

input peak-to-peak voltage level should not exceed the VIN level. Note: VIN is the main supply voltage to

the device at pin 2.

The first gain and filtering stage following the RF-envelope detector has a nominal gain of 15 dB with an

adjustable bandpass filter. The bandpass filter has adjustable 3-dB frequency steps (100 kHz to 400 kHz

for high pass and 600 kHz to 1500 kHz for low pass). Following the bandpass filter is another

gain-and-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first

stage.

The internal filters are configured automatically, with internal presets for each new selection of a

communication standard in the ISO control register (address 01). If required, additional fine tuning can be

accomplished by writing directly to the RX special setting registers (address 0A).

The second receiver gain stage and digitizer stage are included in the AGC loop. The AGC loop is

activated by setting the bit B2 = 1 (agc-on) in the chip status control register (address 00). When

activated, the AGC continuously monitors the input signal level. If the signal level is significantly higher

than an internal threshold level, gain reduction is activated. AGC activation is by default five times the

internal threshold level. It can be reduced to three times the internal level by setting bit B1 = 1 (agcr) in the

RX special setting register (address 0A). The AGC action is fast, typically finishing after four sub-carrier

pulses. By default, the AGC action is blocked after the first few pulses of the sub-carrier signal. This

prevents the AGC from interfering with the reception of the remaining data packet. In certain situations,

this type of blocking is not optimal, so it can be removed by setting B0 = 1 (no_lim) in the RX special

setting register (address 0A).

The bits of the RX special settings register (address 0A), which control the receiver analog section, are

shown in Table 5-20.

5.2.1 Received Signal Strength Indicator (RSSI)

The RSSI measurement block measures the demodulated signal (except in the case of a direct command

for RF-amplitude measurement described in the Direct Commands section). The measuring system

latches the peak value, so the RSSI level can be read after the end of the receive packet. The RSSI

for each new tag response.

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Correlation between the RF input level and RSSI designation levels on the RX_IN1 and RX_IN2 are

shown in Table 5-6 and Table 5-7.

Table 5-6 shows the RSSI level versus RSSI bit value. The RSSI has seven levels (3 bits each) with 4-dB

increments. The input level is the peak-to-peak modulation level of the RF signal as measured on one side

envelope (positive or negative).

Table 5-6. RSSI Level Versus Register Bit Value

RSSI1234567

Input level 2 mVpp 3.2 mVpp 5 mVpp 8 mVpp 13 mVpp 20 mVpp 32 mVpp

As an example, from Table 5-7, let B2 = 1, B1 = 1, B0 = 0; this yields an RSSI value of 6. From Table 5-6

a Bit value of 6 would yield an RSSI level of 20 mVpp.

Table 5-7. RSSI Bit Value and Oscillator Status Register (0F)

Bit Signal Name Function Comments

B7 Unused

B6 osc_ok Crystal oscillator stable

B5 rssi_x2 MSB of auxiliary receiver RSSI

B4 rssi_x1 Auxiliary receiver RSSI

B3 rssi_x1 LSB of auxiliary receiver RSSI 4 dB per step

B2 rssi_2 MSB of main receiver RSSI

B1 rssi_1 Main receiver RSSI

B0 rssi_0 LSB of main receiver RSSI

5.2.2 Receiver –Digital Section

The received sub-carrier is digitized to form a digital representation of the modulated RF envelope. This

digitized signal is applied to digital decoders and framing circuits for further processing.

The digital part of the receiver consists of two sections, which partly overlap. The first section is the bit

decoders for the various protocols, whereas the second section consists of framing logic. The bit decoders

convert the sub-carrier coded signal to a bit stream and also to the data clock. Thus, the sub-carrier-coded

signal is transformed to serial data and the data clock is extracted. The decoder logic is designed for

maximum error tolerance. This enables the decoders to successfully decode even partly corrupted (due to

noise or interference) sub-carrier signals.

In the framing section, the serial bit-stream data is formatted in bytes. In this process, special signals like

the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are

automatically removed. The parity bits and CRC bytes are checked and also removed. The end result is

clean or raw data, which is sent to the 12-byte FIFO register where it can be read by the external

microcontroller system.

The start of the receive operation (successfully received SOF) sets the flags in the IRQ and status

interrupt request (pin 13 IRQ). If the receive data packet is longer than 8 bytes, an interrupt is sent to the

MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be

removed from the FIFO.

Any error in data format, parity, or CRC is detected, and the external system is notified of the error by an

interrupt-request pulse. The source condition of the interrupt-request pulse is available in the IRQ and

status register (address 0C). The bit-coding description of this register is given in Table 5-22.

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The main register controlling the digital part of the receiver is the ISO control register (address 01). By

writing to this register, the user selects the protocol to be used. With each new write in this register, the

default presets are loaded in all related registers, so no further adjustments in other registers are needed

for proper operation.

Table 5-10 shows the coding of the ISO control register. Note that the TRF7961 does not include the

ISO14443 functionality; its features/commands in this area are non-functional.

The framing section also supports the bit-collision detection as specified in ISO14443A. When a bit

collision is detected, an interrupt request is sent and flag set in the IRQ and status register. The position of

the bit collision is written in two registers. Register collision position, with address 0E, and in register

collision position and interrupt mask (address 0D), in which only the bits B7 and B6 are used for collision

position. The collision position is presented as a sequential bit number, where the count starts immediately

after the start bit. For example, the collision in the first bit of the UID would give the value 00 0001 0000 in

the collision-position registers. The count starts with 0, and the first 16 bits are the command code and the

NVB byte. Note: the NVB byte is the number of valid bits.

The receive section also has two timers. The RX-wait-time timer is controlled by the value in the RX wait

time register (address 08). This timer defines the time after the end of the transmit operation in which the

receive decoders are not active (held in reset state). This prevents incorrect detections resulting from

transients following the transmit operation. The value of the RX wait time register defines this time in

increments of 9.44 μs. This register is preset at every write to ISO control register (address 01) according

to the minimum tag-response time defined by each standard.

The RX no-response timer is controlled by the RX no response wait time register (address 07). This timer

measures the time from the start of slot in the anti-collision sequence until the start of tag response. If

there is no tag response in the defined time, an interrupt request is sent and a flag is set in IRQ status

control register. This enables the external controller to be relieved of the task of detecting empty slots. The

wait time is stored in the register in increments of 37.76 μs. This register is also preset, automatically, for

every new protocol selection.

5.2.3 Transmitter

The transmitter section consists of the 13.56-MHz oscillator, digital protocol processing, and RF output

stage.

5.2.3.1 Transmitter –Analog

The 13.56-MHz crystal oscillator (connected to pins 31 and 32) directly generates the RF frequency for the

RF output stage. Additionally, it also generates the clock signal for the digital section and clock signal

displayed for the SYS_CLK (pin 27) which can be used by an external MCU system.

During partial power-down mode (EN = 0, EN2 = 1), the frequency of SYS_CLK is 60 kHz. During normal

reader operation, SYS_CLK can be programmed by bits B4 and B5 in the modulator and SYS_CLK

control register (address 09); available clock frequencies are 13.56 MHz, 6.78 MHz, or 3.39 MHz.

The reference crystal (HC49U) should have the following characteristics:

Parameter Specification

Frequency 13.560000 MHz

Mode of operation Fundamental

Type of resonance Parallel

Frequency tolerance ±20 ppm

Aging <5 ppm/year

Operation temperature range –40°C to 85°C

Equivalent series resistance 50 Ω, minimum

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NOTE

The crystal oscillator’s two external shunt capacitor values are calculated based on the

crystal’s specified load capacitance. The external capacitors (connected to the OSC pins 30

and 31), are calculated as two capacitors in series plus CS(oscillator's gate internal

input/output capacitance plus PCB stray capacitance). The stray capacitance (CS) can be

estimated at approximately 5 ±2 pF (typical).

As an example, given a crystal with a required load capacitance (CL) of 18 pF,

CL= ((C1×C2) / (C1+ C2)) + CS

18 pF = ((27 pF ×27 pF) / (27 pF + 27 pF)) + 4.5 pF

Hence, from this example, a 27-pF capacitor would be placed on pins 30 and 31 to ensure

proper crystal oscillator operation.

The transmit power level is selectable between half power of 100 mW (20 dBm) or full power of 200 mW

(23 dBm) when configured for 5-V automatic operation. The transmit output impedance is 8 Ωwhen

configured for half power and 4 Ωwhen configured for full power. Selection of the transmit power level is

set by bit B4 (rf_pwr) in the chip status control register (Table 5-9). When configured for 3-V automatic

operation, the transmit power level is typically selectable between 33 mW (15 dBm) in half-power mode

and 70 mW (18 dBm) in full-power mode (Vdd_RF at 3.3 V). Note that lower operating voltages result in

reduced transmit power levels.

In normal operation, the transmit modulation is configured by the selected ISO control register (address

01). External control of the transmit modulation is possible by setting the ISO control register (address 01)

to direct mode. While in direct mode, the transmit modulation is made possible by selecting the modulation

type ASK or OOK at pin 12. External control of the modulation type is made possible only if enabled by

setting B6 = 1 (en_ook_p) in the modulator and SYS_CLK control register (address 09). ASK modulation

depth is controlled by bits B0, B1 and B2 in the Modulator and SYS_CLK Control register (address 09).

The range of the ASK modulation is 7%–30%, or 100% (OOK).

The coding of the modulator and SYS_CLK control register is shown in Table 5-19.

The length of the modulation pulse is defined by the protocol selected in the ISO control register. With a

high-Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than

intended. For such cases, the modulation pulse length can be corrected by using the TX pulse length

increments. This means the range of adjustment can be between 73.7 ns and 18.8 μs.

5.2.3.2 Transmitter - Digital

The digital portion of the transmitter is very similar to that of the receiver. Before beginning data

transmission, the FIFO should be cleared with a Reset command (0F). Data transmission is initiated with a

selected command (described in the Direct Commands section, Table 5-29). The MCU then commands

the reader to do a continuous Write command (3Dh, see Table 5-31) starting from register 1Dh. Data

written into register 1Dh is the TX length byte1 (upper and middle nibbles), while the following byte in

when the reader sends the EOF byte. After the TX length bytes, FIFO data is loaded in register 1Fh with

byte storage locations 0 to 11. Data transmission begins automatically after the first byte is written into the

FIFO. The TX length bytes and FIFO can be loaded with a continuous-write command because the

addresses are sequential.

If the data length is longer than the allowable size of the FIFO, the external system (MCU) is warned when

the majority of data from the FIFO has already been transmitted by sending an interrupt request with a

flag in the IRQ register signaling FIFO low/high status. The external system should respond by loading the

next data packet into the FIFO.

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