Texas Instruments ADS127L21EVM-PDK User manual

User’s Guide
ADS127L21EVM-PDK Evaluation Module
ABSTRACT
This user's guide describes the characteristics, operation, and use of the ADS127L21 evaluation module (EVM).
This kit is an evaluation platform for the ADS127L21, which is a 24-bit, high-speed, wide-bandwidth, delta-sigma
(ΔΣ) analog-to-digital converter (ADC). The ADS127L21 offers excellent ac and dc performance, along with
multiple internal digital filter options including a fully programmable finite impulse response (FIR) and infinite
impulse response (IIR) filter, making the device useful for a wide variety of data acquisition applications. The
ADS127L21EVM eases the evaluation of the device with hardware, software, and computer connectivity through
the universal serial bus (USB) interface. This user's guide includes complete circuit descriptions, schematic
diagrams, and a bill of materials. Throughout this document, the abbreviation EVM and the term evaluation
module are synonymous with the ADS127L21EVM.
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Table of Contents
1 EVM Overview......................................................................................................................................................................... 3
1.1 ADS127L21 EVM Kit..........................................................................................................................................................3
1.2 ADS127L21EVM Board..................................................................................................................................................... 4
1.3 ADS127L21EVM-PDK-GUI Unsupported Features........................................................................................................... 4
1.4 Related Documentation......................................................................................................................................................4
2 Analog Interface......................................................................................................................................................................5
2.1 EVM Analog Input Options.................................................................................................................................................5
2.2 ADC Connections and Decoupling.....................................................................................................................................5
2.3 ADC Input Drive Amplifiers................................................................................................................................................ 6
2.4 VCOM Buffer......................................................................................................................................................................7
2.5 Onboard Voltage Reference...............................................................................................................................................7
2.6 External Voltage Reference............................................................................................................................................... 8
2.7 Clock Tree.......................................................................................................................................................................... 9
3 Digital Interface.....................................................................................................................................................................10
3.1 Serial Interface................................................................................................................................................................. 10
3.2 I2C bus for Onboard EEPROM........................................................................................................................................ 10
4 Power Supplies..................................................................................................................................................................... 11
4.1 Power Connection and Configuration...............................................................................................................................11
4.2 Low Dropout Regulator (LDO)......................................................................................................................................... 12
5 ADS127L21 EVM Software Installation............................................................................................................................... 13
6 EVM Operation...................................................................................................................................................................... 16
6.1 Connecting the Hardware................................................................................................................................................ 16
6.2 Optional EVM Connections.............................................................................................................................................. 17
6.3 EVM GUI Global Settings for ADC Control...................................................................................................................... 18
6.4 Time Domain Display....................................................................................................................................................... 19
6.5 Frequency Domain Display.............................................................................................................................................. 20
6.6 Histogram Display............................................................................................................................................................ 21
6.7 Digital Filter Configuration................................................................................................................................................22
6.8 Digital Filter Response..................................................................................................................................................... 23
7 Bill of Materials, Schematics, and Layout.......................................................................................................................... 24
7.1 Bill of Materials.................................................................................................................................................................24
7.2 Schematics.......................................................................................................................................................................29
7.3 Board Layout....................................................................................................................................................................31
Trademarks
Windows® and Microsoft® are registered trademarks of Microsoft Corporation.
MATLAB® is a registered trademark of MathWorks, Incorporated.
All trademarks are the property of their respective owners.
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1 EVM Overview
The ADS127L21EVM is a platform for evaluating the performance of the ADS127L21, which is a 24-bit, high-
speed, wide-bandwidth ΔΣ ADC. The evaluation kit includes the ADS127L21EVM board and the precision host
interface (PHI) controller board that enables the accompanying computer software to communicate with the ADC
over the USB for data capture, configuration, and analysis. The ADS127L21EVM board includes the ADS127L21
ADC and all the peripheral analog circuits and components required to extract optimum performance from the
ADC. The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS127L21
• Supplies power to all active circuitry on the ADS127L21EVM board
1.1 ADS127L21 EVM Kit
The ADS127L21 evaluation module kit includes the following features (Figure 1-1):
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of the
ADS127L21 ADC.
• USB powered—no external power supply is required.
• The PHI controller that provides a convenient communication interface to the ADS127L21 ADC over USB 2.0
(or higher) for power delivery as well as digital input and output.
• Windows® 10 operating systems.
• Easy-to-use evaluation software for 64-bit Microsoft® Windows®.
• The software suite includes graphical tools for data capture, histogram analysis, spectral analysis, and
custom configuration of the programmable digital filters. This suite also has a provision for exporting data to a
text file for post-processing.
Signal
Source
A-to- Micro-B
USB Cable
ADS127L21
EVM GUI
ADS127L21EVM PHI Board
Included in kit
ADS127L21
EVM GUI
Figure 1-1. System Connection for Evaluation
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1.2 ADS127L21EVM Board
The ADS127L21EVM board includes the following features:
• External signal source from differential pair subminiature version A (SMA) connectors
• Options to use external analog and digital power supplies
• Serial interface header for easy connection to the PHI controller
• Pin connections to monitor digital signals with a logic analyzer
• Onboard ultra-low noise, low-dropout (LDO) regulator for excellent 5-V, single-supply regulation of all analog
circuits
1.3 ADS127L21EVM-PDK-GUI Unsupported Features
The following features of the ADS127L21 device are currently not supported in the ADS127L21 EVM GUI,
but will be on a future version of the software. To provide proper operation of the EVM, do not modify the
corresponding register settings from the default values.
• CONFIG2_REG; bits 5:4, START_MODE, default 00b, only start and stop conversions are supported
• CONFIG3_REG; bit 2, SPI_CRC, default 0b, CRC not supported
• CONFIG3_REG; bit 0, STATUS, default 0b, status readback not supported
• FILTER3_REG; bits 1:0, DATA_MODE, default 01b, SDO is dual function
1.4 Related Documentation
Table 1-1 shows the related documentation from Texas Instruments.
Table 1-1. Related Documentation
Document Literature Number
ADS127L21 product data sheet SBASAK4
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2 Analog Interface
The ADS127L21EVM is designed for easy interfacing with analog sources. This section covers the details of the
front-end circuit, including jumper configuration for different input test signals and board connectors for signal
sources.
2.1 EVM Analog Input Options
For best performance, differential analog input signals can be connected through the SMA connectors (J3 and
J6). Header J4 can also directly connect inputs for dc measurements, or where best ac performance is not
needed. For single-ended inputs, header J4 can connect AINN or AINP to GND. Then use either J3 or J6
as the single-ended input. The input driver circuit uses the THS4561 fully-differential amplifier in a unity-gain,
second-order, low-pass filter configuration with a single-pole RC filter at the output. Multiple passive components
around the amplifier are intentionally left uninstalled to give users the flexibility to customize the input drive circuit
for their specific application.
When differential inputs are connected to the SMA connectors (J3 and J6), make sure header J4 does not have
any connection to pins 1 or 4.
2.2 ADC Connections and Decoupling
The circuit shown in Figure 2-1 shows all connections to the ADS127L21 data converter (U3). Each power-
supply connection has a 1-μF and 100-nF decoupling capacitor. Make sure these capacitors are physically close
to the device and have a good connection to the GND plane. The supply connections also have a series 0.1-Ω
resistor. The purpose of this component is to facilitate current measurement for the ADC. Also, each digital input
has a 10-Ω series resistor. These resistors smooth the edges of the digital signals to provide minimal overshoot
and ringing. Although not strictly required, these components can be included in the final design to improve
digital signal integrity.
GND
1uF
C12
IOVDD
100k
R19
100k
R20
0.1
R15
IOVDD
1uF
C8
0.1
R11
AVDD2
1uF
C10
1uF
C11
GND
1uF
C6
0.1
R7
AVDD1
AINP
AINN
REFP
REFN
VCM
ADS127L21
1uF
C15
ADC.SDI
ADC.SDO/DRDY
ADC.CS
ADC.DRDY
ADC.START/SYNC
ADC.RESET
AVSS
AVSS
AVSS
TP7
A1+
DNP
TP8
A1-
DNP
TP9
A2+
DNP
TP10
A2-
DNP
TP11
D+
DNP
TP12
D-
DNP
10.0
R9
10.0
R10
10.0
R12
10.0
R13
10.0
R14
10.0
R16
10.0
R18
10.0
R8 10.0
R95
DNP
RET_SCLK
CAP_SCLK
100nF
C7
100nF
C9
100nF
C13
100nF
C16
CLK
10.0
R30
DNP
eCLK
0
R94 AVDD1
20
AVDD2
19
IOVDD
13 CS 7
DRDY 11
RESET
6
AINN
2AINP
1
CAPA 18
CAPD 15
CLK
12
REFN
5REFP
4
SCLK 9
SDI 8
SDO/DRDY 10
START 16
Thermal_Pad 21
VCM 3
AVSS 17
DGND 14
ADS127L21IRUKR
U3
ADC.SCLK
Figure 2-1. ADS127L21 Connections and Decoupling
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2.3 ADC Input Drive Amplifiers
The circuit shown in Figure 2-2 is the fully differential amplifier (THS4561) that drives the ADC. The input applied
to J3 and J6 must be a low-distortion differential signal. The common-mode output for the amplifier is controlled
by pin 7 on U5 (VOCM). The common-mode signal is set by the data converter (pin 3, VCM). The output of the
amplifier connects to an RC filter that connects to the ADC input (R37, R43, C30, C26, and C32). The amplified
configuration has several do not populate (DNP) components. These components provide flexibility, but are not
required for good performance. The amplifier power supplies are connected by default to the AVDD and AVSS
supplies that are also used for the ADC. The amplifier supplies can be changed to external supplies VP and VM
by removing the 0-Ω resistors that connect to AVDD1 and AVSS (R31 and R47), and installing these resistors to
connect VP and VM (R32 and R48).
AINN
AINP
1µF
C31
1.00k
R38
VCM
GND
GND
10µFC34
10µF
C23
GND
Place Capacitors near ADC inputs
INPUT AMPLIFIER
0.1%
1.00k
R27
0.1%
1.00k
R54
1
2 3 4 5
J3
142-0701-801
1
2 3 4
5
J6
142-0701-801
VM
0R48
DNP
0R47
AVSS
VP
0R31 0R32
DNP
AVDD1
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
100nF
C22
100nF
C33
AINP
AINN
VPAMP
VMAMP
VPAMP
VMAMP
0
R28
0
R50
C0G/NP0
1%390pF
C20
C0G/NP0
1%390pF
C36
C0G/NP0
1000pF
C29
49.9
R37
49.9
R43
C0G/NP0
2200pF
C30
C0G/NP0
1%
220pF
C26
C0G/NP0
1%
220pF
C32
C0G/NP0
680pF
C18
C0G/NP0
120pF
C28
22.0R39
22.0
R40
0.1%
499
R67
0.1%
499
R17
0.1%
499
R26
0.1%
499
R53
0.1%
499
R44
0.1%
499
R33
49.9
R22
DNP
49.9
R57
DNP
4
1
2
3
J4
TSW-104-07-G-S
NC
8
NC
2
THS4561IRUNR
U5B
6
7
10
9
1
5
3
4
VOCM
V+
V-
THS4561IRUNR
U5A
Figure 2-2. ADC Drive Amplifier
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2.4 VCOM Buffer
The circuit shown in Figure 2-3 buffers the VCM signal from the ADC and connects this signal to the J8 SMA
connector. This process is useful if the VCOM signal must be connected to an external piece of test equipment
to set the common-mode voltage. A common use case is to connect this signal to the Audio Precision SYS-2722
to set the signal generators common-mode output. This circuit is not required in the end application and is only
used for testing purposes.
10µF
C45
37.4
R64
1.00k
R66
10.0k
R65
0.033µF
C47
GND
1µF
16V
C44
1.00k
R63 VCM
VCOM BUFFER
1
2
J9
TSW-102-07-G-S
DNP
1
2 3 4 5
J8
901-144-8RFX
AVSS
AVDD1
AVSS
GND
AVSS
AVSS
100nF
C46
2
3
4
6
7
OPA192IDGKT
U7A
NC
1
NC
5
NC
8
OPA192IDGKT
U7B
Figure 2-3. VCOM Buffer
2.5 Onboard Voltage Reference
Figure 2-4 shows the REF6225 configuration. This reference includes an integrated wide bandwidth buffer
that makes the REF6225 designed for driving the switched-capacitor input to the ADS127L21. There are also
unpopulated 0-Ω resistors that allow use of the REF70 reference if higher DC precision is needed. The EVM
provides a buffer and connections if a different voltage reference is chosen. This reference is sufficient to meet
the ADS127L21 data sheet specifications for dynamic performance.
AVDD1
VREF_2v5
1µF
16V
C5
25V
22µF
C3
10µF
C2
REFERENCE
0 R2 REFP
REFN
Minimum (AVDD1-AVSS) 3V for REF6225
0
R1
0 R4
0.047
R5
120k
R6
AVSS
VIN
1
EN
2
SS
3
FILT
4
OUT_S 5
OUT_F 6
GND_F 7
GND_S 8
REF6225IDGKR
U1
TP2
REFN
DNP
TP1
REFP
DNP
TP3
AVSS
DNP
TP4
VrefIN
DNP
0
R89
DNP
0
R90
0
R92
0
R93
DNP
Figure 2-4. Onboard Voltage Reference
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2.6 External Voltage Reference
Figure 2-5 shows a reference buffer that allows connection of an external voltage reference to connector J5. This
circuit and connections are not required if the onboard voltage reference is used (see Figure 2-4). This amplifier
was selected for low voltage offset and low offset drift. The amplifier topology is designed to drive capacitive
loads. For information on this topology, see the Op Amp Stability Videos in TI Precision Labs.
1.00k
R24
0R35
DNP REFP
1.00k
R46
0R56
DNP REFN
GND
1.00k
R36
1.00k
R58
EXTERNAL REFERENCE
AVDD1
AVDD1
AVSS
AVSSAVSS
AVSS
AVSS
AVSS
AVSS
100nF
C21
0
R23
DNP
0
R45
DNP
REFPb
REFNb
REFPb
REFNb
1
2
3
J5
0393570003
10µF
C39
37.4
R55
0.033µF
C35
10.0k
R49
1µF
16V
C40
1µF
16V
C25 10µF
C24
37.4
R34
0.033µF
C19
10.0k
R25
2
3
1
AV+
V-
5
104
OPA2320SAIDGSR
U4A
8
7
9
BV+
V-
6
104
OPA2320SAIDGSR
U4B
Figure 2-5. External Reference Connection and Buffer
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2.7 Clock Tree
Figure 2-6 shows the different clock options for the ADS127L21EVM. The default position for jumper (JP7) 2-3
routes the PHI digital controller board clock to the CLK pin on the ADS127L21 (U3). If the ADS127L21EVM
is used without the PHI board, then change the shunt on jumper (JP7) to position 1-2 to directly route
the local clock to ADS127L21 (U3). Jumper (JP6) 2-3 enables the local 32.768-MHz oscillator (Y1) on the
ADS127L21EVM board, or if inactive (JP6) 1-2, allows an external clock supplied on the SMA connector (J14).
The default position for jumper (JP6) 2-3 selects the local 32.768-MHz oscillator (Y1). The ADS127L21EVM-
PDK-GUI software by default uses the 32.768-MHz (Y1) oscillator, but can also select the 24-MHz PHI clock
source. If an external clock source is used, jumper (JP6) 1-2 position, use a CMOS square-wave signal with an
amplitude equal to IOVDD (2.5 V when using the PHI board) and a frequency within the specified range of the
ADS127L21.
GND
1
2
3 4 5
J14
901-144-8RFX
GND GND
100k
R91
IOVDD
Clock Tree
EXT Clock
100nF
C55
1
2
3
JP6
TSW-103-07-G-S
1
2
3
JP7
TSW-103-07-G-S
EVM CLK
EXT CLK
EVM/EXT CLK
PHI CLK
10pF
C58
DNP
GND
ADC.MCLK_IN
EVM Clock PHI Clock
10pF
C59
DNP
GND
CLK
0
R96
Vcc=3.63V MAX
100k
R98
0
R100
GND
100nF
C60
IOVDD
GND
0
R97
GND
ADC.MCLK_OUT
49.9
R87
49.9
R88
10.0
R29
DNP eCLK
INH
1
Output 3
Vcc
4
Case_GND 2
Y1
KC2016K32.7680C1GE00
49.9
R101 42
U10A
SN74AUP1G17DCKR
VCC
5GND 3
NC
1
U10B
SN74AUP1G17DCKR
10pF
C27
DNP
0R99
DNP
Figure 2-6. Clock Tree
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3 Digital Interface
As discussed in Section 1, the EVM interfaces with the PHI and communicates with the computer over the
USB. There are two devices on the EVM with which the PHI communicates: the ADS127L21 ADC (over SPI)
and the EEPROM (over I2C). The electrically erasable programmable read-only memory (EEPROM) comes
preprogrammed with the information required to configure and initialize the ADS127L21 platform. When the
hardware is initialized, the EEPROM is no longer used.
3.1 Serial Interface
Figure 3-1 shows the digital connections between the ADS127L21EVM and the PHI. The ADS127L21 ADC uses
SPI serial communication in mode 1 (CPOL = 0, CPHA = 1). Because the serial clock (SCLK) frequency can be
as fast as 50 MHz, the ADS127L21EVM offers 10-Ω resistors between the SPI signals to aid with signal integrity.
Typically, in high-speed SPI communication, fast signal edges can cause overshoot; these 10-Ω resistors slow
down the signal edges to minimize signal overshoot. J2 provides test points to measure the digital signals.
Digital Interface
11
33
55
77
99
11 11
13 13
15 15
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
41 41
43 43
45 45
47 47
49 49
51 51
53 53
55 55
57 57
59 59
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
GND
MP1
GND
MP2 GND MP3
GND MP4
J1
GND GND
EVM_ID_SDA
EVM_ID_SCL
EVM_5V
0
R21
EVM_ID_PWR
GND
10uF
C14
10uF
C17
GND
GND
GND
EVM_REG_5V5
EVM_DVDD
GND
RESET
START/SYNC
SDI
CS
SCLK
DRDY
SDO/DRDY
MCLK_IN
MCLK_OUT
RESET
START/SYNC
SDI
CS
SCLK
DRDY
SDO/DRDY
MCLK_IN
MCLK_OUT
12
34
56
78
910
11 12
13 14
15
17
16
18
J2
TSW-109-07-G-D
TP5
GND
DNP
TP6
EVM_5V
DNP
RET_SCLK
CAP_SCLK
Figure 3-1. Connections to Digital Signals on PHI and Test Points
3.2 I2C bus for Onboard EEPROM
The circuit shown in Figure 3-2 is used with the EVM controller (PHI) for EVM identification. This circuit is not
required by the ADS127L21 for operation. The jumper (JP1) is write protected and does not need to be changed
for EVM operation.
A0
1
A1
2
A2
3
VSS
4SDA 5
SCL 6
WP 7
VCC 8
U2
BR24G32FVT-3AGE2
EVM_ID_PWR
EVM_ID_PWR
GND
EVM_ID_SCL
EVM_ID_SDA
EVM_ID_PWR
GND
GND
GND
EVM ID EEPROM
10.0k
R3
1
2
JP1
EEPROM_EN
100nF
C1
100nF
C4
Figure 3-2. EEPROM for EVM ID
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4 Power Supplies
The default state of the EVM is that all power supplies are generated using the USB power from the PHI
controller. This section shows how external power connections can be made and how the default configuration
for AVDD is generated with a 5-V low-dropout regulator (LDO).
4.1 Power Connection and Configuration
Figure 4-1 shows connections to external supplies for the amplifier, reference, and data converter. The default
state of the EVM is that the power is provided by the PHI digital controller board via the USB port. The external
power connections can be used in cases where the PHI does not provide the needed voltage. For example, the
PHI does not provide negative voltages, so if a negative AVSS is needed an external power supply is required.
To use the external power connections for AVDD and IOVDD, remove the 0-Ω resistor connections (R71, R74,
and R81). Connector J12 can optionally be used to supply power to the onboard 5-V and –2.5-V regulators. In
this case, the allowable voltage range for –VinExt is –15.5 V < –VinExt < –3.5 V and +VinExt is 6 V < +VinExt <
15.5 V.
GNDGNDGND
AMP/REF Power Con

gura

on
16V
D1
MMSZ4703T1G
16V
D2
MMSZ4703T1G
GND GND
1uF
C42
1uF
C43
VP VM
1
2 3
J7
0393570003
1.0
R61
1.0
R62
5V_LDO
IOVDDEVM_DVDD
0R81
0R71
AVDD1
0R74
AVDD25V_LDO
EVM/PHI Power
1uF
C53
EVM/External Power
1uF
C51
AVDD1AVDD2 IOVDD
AVS S
AVDD1
AVS S
AVDD2
GND
-VinE xt
GND
IOVDD
1uF
C54
1
2
J10
1
2
J11
1
2
J13
5.6V
D6
MMSZ4690T1G
5.6V
D4
MMSZ4690T1G
5.6V
D5
MMSZ4690T1G
GND
AVSS
GND
1
2 3
J12
GND
+Vin -Vin
+VinE xt
1.0
R76
1.0
R79 1.0
R77
Figure 4-1. Power Connection and Configuration
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4.2 Low Dropout Regulator (LDO)
Figure 4-2 shows how the 5.5-V power from the PHI is regulated to 5 V using a low-noise TPS7A47 LDO. By
default, the shunt on (JP4) 1-2 routes 5.5 V from the PHI to the LDO. The 5-V LDO can also be supplied by
external power on J12 by moving the shunt on (JP4) to position 2-3. The 5-V LDO output is used for the AVDD
connections and can be reprogrammed to different output voltages using R72, R73, R75, R78, R82, and R83.
An additional LDO generates –2.5 V for AVSS, using the low-noise TPS7A30 LDO. This LDO is only supplied by
external power on J12. By default, AVSS is connected to GND with a shunt on (JP5) 1-2. If AVSS must be set to
–2.5 V, then connect an external negative supply to J12 and move the shunt on (JP5) to position 2-3.
TP17
GND
TP18
GND
GND
100k
R68
5.2V Analog LDO
EVM_REG_5V5
OUT 1
NC 2
SENSE 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
TPS7A4700RGWR
U8
10uF
C48
GND
0
R72
0
R73
DNP
0
R75
DNP
0
R78
0
R82
DNP
0
R83
DNP
1uF
C50
0.1
R69
25V
22µF
C49
5V_LDO
10.0k
R70
Green
12
D3
APT2012LZGCK
1
2
JP2
/LDO_EN
DNP
3V
D7
MMSZ4683T1G
TP14
5V_LDO
DNP
TP13
AVSS
DNP
TP15
5V5
DNP
TP16
GND
DNP
GND
0R85
DNP
AVSS
AVSS
AVSS
OUT 1
FB 2
NC
3GND 4
EN
5
NR/SS
6
DNC
7
IN
8
PAD 9
TPS7A3001DRBR
U9
10uF
C56
10uF
C52
0.01µF
C38
10.0k
R86
11.3k
R80
1
2 3
JP4
TSW-103-07-G-S
1
2 3
JP5
TSW-103-07-G-S
GND
-2.5V
GND
GND0.01µF
C57
GND
GND
-2.5V
GND
+Vin
-Vin
-Vin
-2.5V Analog LDO
0
R84
Figure 4-2. LDO Regulators for 5 V and –2.5 V
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5 ADS127L21 EVM Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the ADS127L21EVM
and run the GUI installer to install the EVM GUI software on your computer.
CAUTION
Manually disable any antivirus software running on the computer before downloading the EVM GUI
installer onto the local hard disk. Depending on the antivirus settings, an error message can possibly
appear or the installer.exe file can be deleted.
As shown in Figure 5-1, accept the license agreements and follow the on-screen instructions to complete the
installation.
Figure 5-1. Software Installation and Prompts
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As part of the ADS127L21 EVM GUI installation, and as shown in Figure 5-2, a prompt with a Device Driver
Installation appears on the screen. Click Next to proceed.
Figure 5-2. Device Driver Installation
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The ADS127L21EVM requires the LabVIEW™ run-time engine and can possibly prompt for the installation of
this software, as shown in Figure 5-3, if not already installed.
Figure 5-3. LabVIEW Run-Time Engine Installation
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6 EVM Operation
6.1 Connecting the Hardware
Connect the EVM as shown in Figure 6-1 after installing the software:
1. Physically connect P2 of the PHI to J1 of the ADS127L21 EVM.
2. Install the screws to provide a robust connection. Connect the USB on the PHI to the computer first.
a. LED D5 on the PHI lights up, indicating that the PHI is powered up.
b. LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating with
the PC; Figure 6-1 shows the resulting LED indicators.
3. Start the software GUI as shown in Figure 6-2. Notice that the LEDs blink slowly when the FPGA firmware is
loaded on the PHI. This loading takes a few seconds, then the AVDD and DVDD power supplies turn on.
4. Connect the signal generator. The input range is 0 V to 5 V. A common input signal applied is a 4.9-VPP
signal with a 2.5-V offset. This signal is adjusted just below the full-scale range to avoid clipping.
1. Connect PHI to
ADS127L21EVM
and install screws.
4. Connect optional
signals as needed.
5. Connect input to
signal source. 4. Connect optional
signals as needed.
2. Connect USB power before
applying signal source.
3. Start software GUI.
Figure 6-1. Connecting the Hardware to the ADS127L21EVM
Select EVM GUI from
start menu, or
associated shortcut.
Figure 6-2. Launch the EVM GUI Software
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6.2 Optional EVM Connections
Figure 6-3 shows optional connections to the power, clock, and VCM. These connections are not required
for initial setup of the EVM but can be helpful to configure the EVM more closely to the end application
configuration. Review the schematic and hardware sections of this document to understand how these
connections are used.
Buffered Vcm
signal
Optional power
connections
Optional digital
communications
Optional amplifier
power connection
Optional external
reference connection
Optional external
clock
Optional power
connections
Figure 6-3. Optional EVM Connections
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6.3 EVM GUI Global Settings for ADC Control
Figure 6-4 shows that the EVM global controls are located on the left-hand side of the GUI. These controls
include the number of samples, MCLK (ADC external clock frequency), SCLK frequency, data rate, and others.
In the upper left-hand side of the GUI is the Pages control that allows access to the other key pages in the GUI.
Figure 6-4 also shows the ADC register settings. The registers can be used to set the different device modes
(such as filter settings and power settings).
Figure 6-4. EVM GUI Global Settings for ADC Control
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6.4 Time Domain Display
The time domain display tool allows visualization of the ADC response to a given input signal. This tool is useful
for both studying the behavior and debugging any gross problems with the ADC or drive circuits. The user can
trigger a capture of the data of the selected number of samples from the ADS127L21EVM, as per the current
interface mode settings indicated in Figure 6-5 by using the Capture button. The sample indices are on the
x-axis and two y-axes show the corresponding output codes and the equivalent analog voltages based on the
specified reference voltage. Switching pages to any of the analysis tools described in the subsequent sections
causes calculations to be performed on the same set of data.
Figure 6-5. Time Domain Display
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6.5 Frequency Domain Display
The spectral analysis tool, shown in Figure 6-6, is intended to evaluate the dynamic performance (SNR, THD,
SFDR, SINAD, and ENOB) of the ADS127L21 ADC through single-tone sinusoidal signal FFT analysis using
the 7-term Blackman-Harris window setting. The FFT tool includes windowing options that are required to
mitigate the effects of non-coherent sampling (this discussion is beyond the scope of this document). The
7-Term Blackman-Harris window is the default option and has sufficient dynamic range to resolve the frequency
components of up to a 24-bit ADC. The None option corresponds to not using a window (or a rectangular
window) and is not recommended.
Figure 6-6. Frequency Domain Display
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