Texas Instruments ADS8332EVMV2-PDK User manual

User’s Guide
ADS8332EVMV2-PDK Evaluation Module
Reed Kaczmarek Data Acquisition Products
ABSTRACT
This user's guide describes the characteristics, operation, and use of the ADS8332 evaluation module (EVM)
performance demonstration kit (PDK). The ADS8332 is a low-power, 16-bit, 500k samples per-second (SPS)
successive approximation (SAR) analog-to-digital converter (ADC) with an 8-to-1 multiplexer (mux) input. Each
input channel on the device supports unipolar input ranges of 0 V to 4.096 V with single-supply operation. The
EVM-PDK eases the evaluation of ADS8332 device with hardware, software, and computer connectivity through
the universal serial bus (USB) interface. This user's guide includes complete circuit descriptions, schematic
diagrams, and a bill of materials.
www.ti.com
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 1
Copyright © 2023 Texas Instruments Incorporated

Table of Contents
1 Overview..................................................................................................................................................................................4
1.1 ADS8332EVMV2-PDK Features........................................................................................................................................4
1.2 ADS8332EVMV2 Features................................................................................................................................................ 4
2 EVM Analog Interface.............................................................................................................................................................5
2.1 ADS8332EVMV2 Onboard Reference............................................................................................................................... 6
3 Digital Interfaces.....................................................................................................................................................................7
3.1 ADS8332 Digital Interface..................................................................................................................................................7
4 Power Supplies....................................................................................................................................................................... 8
5 ADS8332EVMV2-PDK Initial Setup........................................................................................................................................9
5.1 Default Jumper Settings.....................................................................................................................................................9
5.2 EVM Graphical User Interface (GUI) Software Installation.............................................................................................. 10
6 ADS8332EVMV2-PDK Operation......................................................................................................................................... 14
6.1 EVM GUI Global Settings for ADC Control...................................................................................................................... 15
6.2 Time Domain Display Tool................................................................................................................................................15
6.3 Spectral Analysis Tool...................................................................................................................................................... 17
6.4 Histogram Tool................................................................................................................................................................. 18
6.5 Linearity Analysis Tool......................................................................................................................................................19
6.6 Input Amplifier Configurations.......................................................................................................................................... 20
7 Bill of Materials, PCB Layout, and Schematics................................................................................................................. 21
7.1 Bill of Materials.................................................................................................................................................................21
7.2 PCB Layout...................................................................................................................................................................... 24
7.3 Schematics.......................................................................................................................................................................26
8 Revision History................................................................................................................................................................... 29
List of Figures
Figure 2-1. ADS8332EVMV2 Analog Input Connections for Channels IN0 to IN7...................................................................... 5
Figure 2-2. REF6041 4.096-V Onboard Reference Source.........................................................................................................6
Figure 5-1. ADS8332EVMV2 Default Jumper Settings............................................................................................................... 9
Figure 5-2. Software Installation Prompts..................................................................................................................................10
Figure 5-3. ADS8332 Device Driver Installation Wizard Prompts..............................................................................................11
Figure 5-4. LabVIEW Run-Time Engine Installation.................................................................................................................. 12
Figure 5-5. ADS8332EVM Folder Post-Installation................................................................................................................... 13
Figure 6-1. ADS8332EVMV2-PDK Hardware Setup and LED Indicators..................................................................................14
Figure 6-2. Launch the ADS8332EVMV2 GUI Software........................................................................................................... 14
Figure 6-3. EVM GUI Global Input Parameters......................................................................................................................... 15
Figure 6-4. Time Domain Display: Manual.................................................................................................................................16
Figure 6-5. Time Domain Display: Auto..................................................................................................................................... 16
Figure 6-6. Spectral Analysis Tool............................................................................................................................................. 17
Figure 6-7. Histogram Analysis Tool.......................................................................................................................................... 18
Figure 6-8. Linearity Analysis Tool.............................................................................................................................................19
Figure 6-9. Input Amplifier Configuration Examples.................................................................................................................. 20
Figure 7-1. ADS8332EVMV2 PCB: Top Overlay....................................................................................................................... 24
Figure 7-2. ADS8332EVMV2 PCB Layer 1: Top Layer..............................................................................................................24
Figure 7-3. ADS8332EVMV2 PCB Layer 2: GND Plane........................................................................................................... 24
Figure 7-4. ADS8332EVMV2 PCB Layer 3: Power Planes....................................................................................................... 24
Figure 7-5. ADS8332EVMV2 PCB Layer 4: Bottom Layer........................................................................................................ 25
Figure 7-6. ADS8332EVMV2 PCB: Bottom Overlay..................................................................................................................25
Figure 7-7. ADS8332EVMV2-PDK Schematic: ADC.................................................................................................................26
Figure 7-8. ADS8332EVMV2-PDK Schematic: Interface.......................................................................................................... 27
Figure 7-9. ADS8332EVMV2-PDK Schematic: Hardware.........................................................................................................28
List of Tables
Table 2-1. J1 Header Analog Interface Connections................................................................................................................... 6
Table 2-2. SMA Analog Interface Connections............................................................................................................................ 6
Table 3-1. Digital I/O Connections for Connector J2....................................................................................................................7
Table 5-1. Default Jumper Configuration..................................................................................................................................... 9
Table 6-1. External Source Requirements for Evaluation of the ADS8332................................................................................17
Table 6-2. External Source Requirements for ADS8332 Evaluation..........................................................................................19
Table 7-1. Bill of Materials..........................................................................................................................................................21
Table of Contents www.ti.com
2ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

Trademarks
Samtec™ is a trademark of Samtec, Inc.
LabVIEW™ is a trademark of National Instruments.
Windows 7® and Windows 8® are registered trademarks of Microsoft Corporation.
All trademarks are the property of their respective owners.
www.ti.com Trademarks
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 3
Copyright © 2023 Texas Instruments Incorporated

1 Overview
The ADS8332EVMV2-PDK is a platform for evaluating the performance of the ADS8332 SAR ADC, which is
an 8-channel, 16-bit, 4.096-V, multiplexed input ADC device. The evaluation kit includes the ADS8332EVMV2
board and the precision host interface (PHI) controller board that enables the accompanying computer software
to communicate with the ADC over USB for data capture and analysis.
The ADS8332EVMV2 board includes the ADS8332 SAR ADC, all the peripheral analog circuits, and
components required to extract optimum performance from the ADC.
The PHI board primarily serves three functions:
1. Provides a communication interface from the EVM to the computer through a USB port
2. Provides the digital input and output signals necessary to communicate with the ADS8332EVMV2
3. Supplies power to all active circuitry on the ADS8332EVMV2 board
Along with the ADS8332EVMV2 and PHI controller board, this evaluation kit includes an A-to-micro-B USB cable
to connect to a computer.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Related Documentation
Device Literature Number
ADS8332 SBAS363
OPA320 SBOS513
REF6041 SBOS708
TPS7A4700 SBVS204
1.1 ADS8332EVMV2-PDK Features
The ADS8332EVMV2-PDK includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of the
ADS8332 ADC
• USB powered—no external power supply is required
• The PHI controller that provides a convenient communication interface to the ADS8332 ADC over USB 2.0
(or higher) for power delivery as well as digital input and output
• Easy-to-use evaluation software for Windows 7® and Windows 8®, 64-bit operating systems
• The software suite includes graphical tools for data capture, histogram analysis, spectral analysis, and
linearity analysis. This suite also has a provision for exporting data to a text file for post-processing.
1.2 ADS8332EVMV2 Features
The ADS8332EVMV2 includes the following features:
• Onboard SMA connectors and RC input filters
• Jumper-selectable onboard 0.2-V common pin supply
• Jumper-selectable buffer between the multiplexer and the ADC
• Onboard ultralow-noise low-dropout (LDO) regulator for excellent 5.2-V single-supply regulation of the ADC
and onboard voltage reference.
Overview www.ti.com
4ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

2 EVM Analog Interface
The ADS8332EVMV2 is designed for easy interfacing to analog sources. The Samtec™ connector provides
a convenient 16-pin, single-row, header J1 accessing channels IN0-IN7 of the device. In addition, four SMA
connectors, J-1 to J-4, provide a high quality connection to channels IN0, IN1, IN6, and IN7. Figure 2-1 shows
the ADS8332EVMV2 analog input connections, input buffers, and input RC filters for channels IN0 to IN7. Table
2-1 lists the analog interface connections for header J1 and Table 2-2 lists the analog interface connections for
the SMA connectors.
ADS8332
40.2

SMA Connector
J5 IN0
1500 pF
40.2

COM
0.2-V Supply
JP1
J1
40.2

1 k

SMA Connector
J8 IN7
16
15
2
1
1500 pF
1500 pF
1 k

Figure 2-1. ADS8332EVMV2 Analog Input Connections for Channels IN0 to IN7
www.ti.com EVM Analog Interface
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 5
Copyright © 2023 Texas Instruments Incorporated

Table 2-1. J1 Header Analog Interface Connections
Header Pin Number Signal Description
J1.1 IN0 Positive analog input for channel IN0
J1.3 IN1 Positive analog input for channel IN1
J1.5 IN2 Positive analog input for channel IN2
J1.7 IN3 Positive analog input for channel IN3
J1.9 IN4 Positive analog input for channel IN4
J1.11 IN5 Positive analog input for channel IN5
J1.13 IN6 Positive analog input for channel IN6
J1.15 IN7 Positive analog input for channel IN7
J1.2, J1.4, J1.6, J1.8, J1.10, J1.12,
J1.14, J1.16
GND Ground connections
Table 2-2. SMA Analog Interface Connections
SMA Connector Signal Description
J5 IN0 Analog input for channel IN0
J6 IN1 Analog input for channel IN1
J7 IN6 Analog input for channel IN6
J8 IN7 Analog input for channel IN7
2.1 ADS8332EVMV2 Onboard Reference
The ADS8332EVMV2 incorporates an onboard 4.096-V reference, REF6041 (U9). With a reference of 4.096-V
the full-scale range of the ADS8332 is 0 V to 4.096 V. The output of the REF6041 is buffered internally. Testpoint
REF allows the reference voltage to be monitored. The schematic for the reference circuit is shown in Figure 2-2.
U9
REF6041
VOUT
FILT
1 µF 47 µF
0

ADS8332
REF+ (PIN15)
Figure 2-2. REF6041 4.096-V Onboard Reference Source
EVM Analog Interface www.ti.com
6ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

3 Digital Interfaces
As noted in Section 1, the EVM interfaces with the PHI that, in turn, communicates with the computer over USB.
There are two devices on the EVM with which the PHI communicates: the ADS8332 ADC (over serial interface)
and the EEPROM (over I2C). The EEPROM comes preprogrammed with the information required to configure
and initialize the ADS8332EVMV2-PDK platform. After the hardware is initialized, the EEPROM is no longer
used.
3.1 ADS8332 Digital Interface
The ADS8332EVMV2-PDK communicates with the PHI controller through SPI connections. The PHI controller is
configured to operate at a 3.3-V logic level and is directly connected to the digital I/O lines of the ADC.
Socket strip connector J2 provides the digital I/O connections between the ADS8332EVMV2 board and the PHI
controller.
Table 3-1 summarizes the pin-outs for connector J2.
Table 3-1. Digital I/O Connections for Connector J2
Pin Number Signal Description
J2.1 EVM_REG_5V5 5.5-V power supply from the PHI to the ADS8332EVMV2
J2.3 GND Ground connection
J2.18 SDI Serial data input connection
J2.20 CONVST Active high logic input to control start of conversion
J2.22 CS Chip select, active low
J2.24 SCLK Clock input for serial interface
J2.50 DVDD 3.3-V digital supply from the PHI controller board
J2.56 EVM_ID_SDA Serial data for the EEPROM (U10)
J2.58 EVM_ID_SCL Serial clock for the EEPROM (U10)
J2.59 EVM_ID_PWR Power supply used only to power the EEPROM (U10) on the EVM board
J2.60 GND Ground connection
www.ti.com Digital Interfaces
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 7
Copyright © 2023 Texas Instruments Incorporated

4 Power Supplies
The ADS8332 ADC analog supply (AVDD) is provided by a low-noise linear regulator (TPS7A4700). The
regulator uses a 5.5-V supply out of a switching regulator from the PHI controller to generate a quiet and stable
5.2-V supply output. The 3.3-V supply to the digital supply of the ADS8332 is provided directly by an LDO
from the PHI controller. The power supply for each active component on the EVM is bypassed with a ceramic
capacitor placed close to that component. Additionally, the EVM layout uses thick traces or large copper filled
areas where possible between bypass capacitors and their loads to minimize inductance along the load current
path.
When using the ADS8332EVMV2 in conjunction with the PHI controller, the PHI controller supplies the AVDD
and DVDD supply. Do not supply external power supply voltages.
Power Supplies www.ti.com
8ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

5 ADS8332EVMV2-PDK Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for the proper
operation of the ADS8332EVMV2-PDK.
5.1 Default Jumper Settings
Make sure jumpers JP1, JP2, and J4 are in the default configuration while interfacing the ADS8332EVMV2
board with the PHI controller as described in Table 5-1. The jumpers can be reconfigured to allow for different
types of operation.
Figure 5-1 details the default jumper settings.Table 5-1 explains the configuration for these jumpers.
Figure 5-1. ADS8332EVMV2 Default Jumper Settings
Table 5-1. Default Jumper Configuration
Jumper Function Default Position Description
JP1 Common pin voltage Shunt on pins 2-3 Shunt on pins 2-3 select ground as the common pin voltage
JP2 Multiplexer output buffer Shunt on pins 1-2 Shunt on pins 1-2 selects to bypass the buffer between
MUXOUT and ADCIN
J4 EEPROM write enable Open Open enables write protect for the EEPROM
www.ti.com ADS8332EVMV2-PDK Initial Setup
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 9
Copyright © 2023 Texas Instruments Incorporated

5.2 EVM Graphical User Interface (GUI) Software Installation
The following steps list the directions to install the software.
CAUTION
Manually disable any antivirus software running on the computer before downloading the EVM GUI
installer onto the local hard disk. Otherwise, depending on the antivirus settings, an error message
may appear or the installer.exe file may be deleted.
Download the latest version of the EVM GUI installer from the Tools and Software folder of the
ADS8332EVMV2-PDK, and run the GUI installer to install the EVM GUI software. Administrator privileges on the
PC are required in order to install the EVM software. Accept the license agreements and follow the on-screen
instructions shown in Figure 5-2 in order to complete the installation.
Figure 5-2. Software Installation Prompts
ADS8332EVMV2-PDK Initial Setup www.ti.com
10 ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

As a part of the ADS8332EVMV2 GUI installation, a prompt with a Device Driver Installation appears on the
screen, as shown in Figure 5-3. Click Next to proceed.
Figure 5-3. ADS8332 Device Driver Installation Wizard Prompts
Note
A notice may appear on the screen stating that Widows cannot verify the publisher of this driver
software. Select Install this driver software anyway.
www.ti.com ADS8332EVMV2-PDK Initial Setup
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 11
Copyright © 2023 Texas Instruments Incorporated

The ADS8332EVMV2-PDK requires LabVIEW™ Run-Time Engine, and may prompt for the installation of this
software, as shown in Figure 5-4, if not already installed.
Figure 5-4. LabVIEW Run-Time Engine Installation
ADS8332EVMV2-PDK Initial Setup www.ti.com
12 ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

After these installations, verify that C:\Program Files (x86)\Texas Instruments\ADS8332EVM is as shown in
Figure 5-5.
Figure 5-5. ADS8332EVM Folder Post-Installation
www.ti.com ADS8332EVMV2-PDK Initial Setup
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 13
Copyright © 2023 Texas Instruments Incorporated

6 ADS8332EVMV2-PDK Operation
The following instructions are a step-by-step guide to connecting the ADS8332EVMV2 to the computer and
evaluating the performance of the ADS8332:
1. Connect the ADS8332EVMV2 to the PHI. Install the two screws as indicated in Figure 6-1.
2. Use the USB cable provided to connect the PHI to the computer.
a. LED D5 on the PHI lights up, indicating that the PHI is powered up.
b. LEDs D1 and D2 on the PHI starts blinking to indicate that the PHI is booted up and communicating with
the PC. The resulting LED indicators are shown in Figure 6-1.
Figure 6-1. ADS8332EVMV2-PDK Hardware Setup and LED Indicators
3. Double click on the ADS8332 EVM.exe file to launch the EVM GUI, as shown in Figure 6-2.
Figure 6-2. Launch the ADS8332EVMV2 GUI Software
ADS8332EVMV2-PDK Operation www.ti.com
14 ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

6.1 EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the voltage levels and timing configuration of the ADC
digital interface, the EVM GUI provides users with high-level control over the ADS8332 sampling rate, channel
selection, and channel scanning.
Figure 6-3 shows the interface configuration pane at the left, through which various functions of the ADS8332
are exercised. These are global settings, and persist across the different GUI testing tools, and the GUI pages
listed in the top left pane.
Figure 6-3. EVM GUI Global Input Parameters
The Channel Select Mode field allows the user to choose to capture data from a single channel or to
automatically scan through the channels.
The Select Channel drop-down menu allows the user to select the single channel to sample (if in manual
channel select mode) or to select the start channel for the automatic scanning (if in auto channel select mode).
The ADS8332EVMV2 device supports sampling rates from 500 kSPS down to 20 kSPS. The Sampling Rate
field allows the user to type in the desired sampling rate in samples per second (SPS).
6.2 Time Domain Display Tool
The time domain display tool allows visualization of the time domain conversion results given a set of analog
input signals.
The GUI Time Domain Display shows the time domain voltage plot for a single channel or for multiple channels if
in auto channel select mode. The sample indices are on the x-axis and there are two y-axes showing the codes
and the corresponding converted analog voltages. The user can choose to select any combination of desired
channels using the Analog Channel X selection buttons at the top right side of the display.
The software captures a contingent number of samples as selected in the Samples field when the user presses
the Capture button as shown in Figure 6-4. In addition, the bottom right side of the GUI provides information
about the converted signals such as the selected channel maximum and minimum code and maximum and
minimum voltage for each channel using the channel drop down in the bottom right. Figure 6-5 shows the time
domain display when all eight channels are captured in auto channel select mode.
www.ti.com ADS8332EVMV2-PDK Operation
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 15
Copyright © 2023 Texas Instruments Incorporated

Figure 6-4. Time Domain Display: Manual
Figure 6-5. Time Domain Display: Auto
ADS8332EVMV2-PDK Operation www.ti.com
16 ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

6.3 Spectral Analysis Tool
The spectral analysis tool, shown in Figure 6-6, is intended to evaluate the dynamic performance (SNR, THD,
SFDR, SINAD, and ENOB) of ADS8332 SAR ADC through single-tone sinusoidal signal FFT analysis using the
7-term Blackman-Harris window setting.
Figure 6-6. Spectral Analysis Tool
For dynamic performance evaluation, the external single-ended source must have better specifications than the
ADS8332 to make sure that the measured system performance is not limited by the performance of the signal
source. Therefore, the external reference source must meet the source requirements mentioned in Table 6-1.
Table 6-1. External Source Requirements for Evaluation of the ADS8332
Specification Description Specification Value
Signal frequency 2 kHz (OSR=0)
External source type Single-ended
External source common-mode 2.048 V
Maximum SNR 100 dB
Maximum THD –110 dB
For 2-kHz SNR and ENOB evaluation at a maximum throughput of 500 kSPS, the optimal number of samples is
32768. More samples brings the noise floor so low that the external source phase noise can dominate the SNR
and ENOB calculations.
Finally, the FFT tool includes windowing options that are required to mitigate the effects of noncoherent sampling
(this discussion is beyond the scope of this document). The 7-Term Blackman Harris window is the default option
and has sufficient dynamic range to resolve the frequency components of up to a 24-bit ADC. The None option
corresponds to not using a window (or using a rectangular window) and is not recommended.
www.ti.com ADS8332EVMV2-PDK Operation
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 17
Copyright © 2023 Texas Instruments Incorporated

6.4 Histogram Tool
Noise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, which is an
indicator of the number of bits of ADC resolution losses resulting from noise generated by the various sources
connected to the ADC when measuring a dc signal. The cumulative effect of noise coupling to the ADC output
from sources such as the input drive circuits, the reference drive circuit, the ADC power supply, and the ADC
is reflected in the standard deviation of the ADC output code histogram that is obtained by performing multiple
conversions of a dc input applied to a given channel.
The histogram corresponding to a dc input is displayed on clicking on the Capture button, as shown in Figure
6-7:
Figure 6-7. Histogram Analysis Tool
ADS8332EVMV2-PDK Operation www.ti.com
18 ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

6.5 Linearity Analysis Tool
The linearity analysis tool, shown in Figure 6-8, measures and generates the performance differential
nonlinearity (DNL) and integral nonlinearity (INL) plots over the entire code range for the ADS8332. A 1-kHz
sinusoidal input signal is required, which is slightly saturated (100 mV to 200 mV outside the full-scale range)
at the input with very low distortion. The external source linearity must be better than the ADC linearity. The
measured system performance must reflect the linearity errors of the ADC and must not be limited by the
performance of the signal source. Jumper JP1 must be put into position with the shunt on pins 1-2 to allow for a
common voltage of 0.2 V to be applied, thus allowing the inputs to be fully saturated. To make sure that the DNL
and INL of the ADC are correctly measured, the external source must meet the requirements in Table 6-2.
Table 6-2. External Source Requirements for ADS8332 Evaluation
Specification Description Specification Value
Signal frequency 1 kHz
External source type Single ended, referred to GND
External source common mode 2.25-V
Signal amplitude 4.2-VPP
Maximum noise 35 µVRMS
Maximum SNR 100 dB
Maximum THD –110 dB
The number-of-hits setting depends on the external noise source. For a 100-dB SNR external source with
approximately 30 µVrms of noise, the total number of hits must be 256.
Note
This analysis can take a couple of minutes to run and the evaluation board must remain undisturbed
during the complete duration of the analysis.
Figure 6-8. Linearity Analysis Tool
www.ti.com ADS8332EVMV2-PDK Operation
SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
ADS8332EVMV2-PDK Evaluation Module 19
Copyright © 2023 Texas Instruments Incorporated

6.6 Input Amplifier Configurations
The ADS8332EVMV2 is designed so the user can configure the input amplifier in many different topologies. The
EVM comes with the input as a unity gain buffer because this is applicable to the majority of SAR ADC designs.
All eight of the input amplifiers have unpopulated components that allow for configurability.
Figure 6-9 shows three different input amplifier options for the ADS8332EVMV2. First, is the buffer configuration
and this is how the EVM will initially be populated. Next, is an inverting configuration for when the dc offset
of the input signal is zero. This topology will superimpose the input signal onto the voltage REF/2. Lastly, the
bottom inverting configuration should be used for an input signal with the dc offset of VREF/2. This amplifier will
maintain the dc offset of VREF/2.
The input amplifiers can be adjusted in many different ways to produce gains, filters, and a number of other
functions. These input configurations are not tested and may require a higher bandwidth amplifier than what is
populated on the ADS8332EVMV2.
+
–
+
–
1 k

40.2 k

1500 pF
1 k

40.2 k

1 k

40.2 k

1 k

1 k

1 k

1 k

REF/4
REF/2
Input With
DC Offset = 0 V
Input
Input With
DC Offset = REF/2
To ADC
To ADC
To ADC
4.096 V
2.048 V
0 V
+2.048 V
0
–2.048 V
4.096 V
2.048 V
0
4.096 V
2.048 V
0 V
4.096 V
2.048 V
0
4.096 V
2.048 V
0
1500 pF
1500 pF
+
–
+
–
+
–
Figure 6-9. Input Amplifier Configuration Examples
ADS8332EVMV2-PDK Operation www.ti.com
20 ADS8332EVMV2-PDK Evaluation Module SBAU251B – JULY 2017 – REVISED FEBRUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated