Texas Instruments TPA3220EVM User manual

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TPA3220 Evaluation Module
User's Guide
SLAU754A–January 2018–Revised August 2019
TPA3220 Evaluation Module
This user's guide describes the characteristics, operation, and use of the TPA3220 evaluation module. A
complete printed-circuit board (PCB) description, schematic diagram, and bill of materials (BOM) are also
included.

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Contents
1 Quick Start (BTL MODE) ................................................................................................... 3
1.1 Required Hardware................................................................................................. 3
1.2 Connections and Board Configuration (BTL MODE) .......................................................... 4
1.3 Power-Up ............................................................................................................ 6
2 Setup By Mode............................................................................................................... 7
2.1 BTL MODE (Stereo - 2 Speaker Outputs)....................................................................... 7
2.2 PBTL MODE (Mono – 1 Speaker Output)....................................................................... 7
3 Hardware Configuration ................................................................................................... 10
3.1 Indicator Overview (OTW_CLIP and FAULT) ................................................................. 10
3.2 PWM Frequency Adjust .......................................................................................... 10
3.3 Modulation Modes (AD Mode and HEAD Mode).............................................................. 11
3.4 Output Mode Selection ........................................................................................... 11
3.5 Audio Front End ................................................................................................... 11
3.6 EVM Power Tree .................................................................................................. 12
3.7 LC Response and Overview..................................................................................... 13
3.8 Reset Circuit and POR ........................................................................................... 14
3.9 Analog-Input-Board Connector (J28) ........................................................................... 14
4 EVM Design Documents .................................................................................................. 16
4.1 TPA3220 Board Layouts ......................................................................................... 16
4.2 TPA3220 Board Layouts ......................................................................................... 18
4.3 TPA3220 EVM Schematics ...................................................................................... 19
4.4 TPA3220EVM Bill of Materials .................................................................................. 22
List of Figures
1 Output Configuration BTL .................................................................................................. 3
2 EVM Board (Top Side)...................................................................................................... 4
3 EVM Board (Bottom Side).................................................................................................. 4
4 Output Configuration PBTL - 4 Inductors................................................................................. 7
5 EVM Board With Connectors and Jumpers.............................................................................. 8
6 Filter Frequency Response .............................................................................................. 13
7 RESET Circuit .............................................................................................................. 14
8 AIB EVM Connector ....................................................................................................... 14
9 TPA3220 EVM Top Composite Assembly .............................................................................. 16
10 TPA3220 EVM Bottom Composite Assembly .......................................................................... 17
11 TPA3220 EVM Board Dimensions....................................................................................... 18
12 TPA3220 EVM Schematic 1.............................................................................................. 19
13 TPA3220 EVM Schematic 2.............................................................................................. 20
14 TPA3220 EVM Schematic 3 .............................................................................................. 21
List of Tables
1 Jumper and Switch Configurations (BTL Mode) ........................................................................ 5
2 Jumper and Switch Configurations (PBTL Mode)....................................................................... 9
3 Fault and Clip Overtemperature Status ................................................................................. 10
4 Frequency Adjust Master Mode Selection (J16)....................................................................... 10
5 HEAD and AD Mode Selection........................................................................................... 11
6 Output Mode and Modulation Mode Selection ......................................................................... 11
7 Power Supply Summary................................................................................................... 12
8 AIB Connector (J28) Pinout............................................................................................... 15
9 AIB Power Rail Specifications............................................................................................ 15
10 TPA3220EVM Bill of Materials ........................................................................................... 22

Class-D
Amplifier
OUT-A
OUT-B
OUT-C
OUT-D
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Trademarks
Sagami is a registered trademark of SAGAMI ELEC CO., LTD.
All other trademarks are the property of their respective owners.
1 Quick Start (BTL MODE)
This section describes the necessary hardware, connections, configuration, and steps to quick start the
EVM into BTL mode with stereo audio playing out of two speakers.
Figure 1 illustrates the BTL mode output configuration.
Figure 1. Output Configuration BTL
1.1 Required Hardware
The following hardware is required for this EVM:
• TPA3220EVM
• Power supply 5–14 A, 12–30 VDC
• Two 2–8 Ωspeaker or resistor loads (ensure speaker or load is appropriately sized for the required
wattage output)
• Four speaker, banana cables
• Four XLR or two RCA input cables
• Analog output audio source

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1.2 Connections and Board Configuration (BTL MODE)
Figure 2 and Figure 3 show the EVM board.
Figure 2. EVM Board (Top Side)
Figure 3. EVM Board (Bottom Side)

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Use the following steps when connecting and configuring the board for BTL MODE:
1. Ensure the power supply is OFF. Connect the power supply positive terminal to J1 PVDD (red) and
negative terminal to J1 GND (black).
2. Connect the left channel speaker, power resistor load (3–8 Ω) to the TPA3220EVM positive output
terminal (J9 OUT1+ (red)) and other side of the speaker, power resistor to the TPA3220EVM negative
output terminal (J9 OUT1– (black)).
3. Connect the right channel speaker, power resistor load (3–8 Ω) to the TPA3220EVM positive output
terminal (J2 OUT2+ (red)) and other side of the speaker, power resistor to the TPA3220EVM negative
output terminal (J2 OUT2– (black)).
4. Check to make sure that the power supply is connected to J1 only and speakers are connected to J9
or J2 only, as their colors are the same.
5. Input Configuration:
A. Differential Inputs: connect one differential XLR audio input to each DIFF IN1 (J14) and DIFF IN2
(J15). Install jumpers J10, J11, J20, and J21 to position 1:2 which is labeled as RCA or XLR.
Jumpers J4 and J12 must be uninstalled for DIFF input.
B. Single-Ended Inputs: connect one single-ended RCA audio input to IN1P (J3) and IN2P (J18).
Install jumpers J10, J11, J20, and J21 to position 1:2 which is labeled as RCA or XLR. Jumpers J4
and J12 must be installed for SE input.
C. Audio Interface Board Input: Install jumpers J10, J11, J20, and J21 to position 2:3 which is
labeled as AIB. Jumpers J4 and J12 must be installed for SE input from the AIB or uninstalled for
DIFF input from the AIB.
6. Ensure that RESET S1 and MUTE S2 are in the lower positions of RESET and MUTE, respectively.
7. Check Table 1 for all jumper and switch configurations
Table 1. Jumper and Switch Configurations (BTL Mode)
Component Component Description Configuration for BTL
J23 Gain/SLV Select MSTR-18dB
J24 N/A IN
J4, J12 Input DIFF or SE Select OUT = DIFF IN, IN = DIFF IN
J10, J11, J20, J21 AIB Input Select Position 1:2 for XLR/RCA, Position 2:3
for AIB
J6 HEAD or AD Mode Select IN
J7, J8 PBTL or BTL Select OUT
J22 VDD SEL Position 2:3 (GVDD)
J25 5V-PU SEL OUT
S1 RESET Control RESET
S2 MUTE Control MUTE
J13 Auto Retry OUT
J29 PVDD-IN IN
J26 12V-IN IN
J5 5V-IN IN
J27 3.3V-IN IN
J19 5V-PU EN OUT
J17 OSC Output No Connection
J16 Master or Slave Select Position 3:4 MASTER MODE

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1.3 Power-Up
Ensure that required connections and configurations have been checked. The TPA3220EVM board can
now be powered on.
1. Enable the power supply from 12 V to 30 V and ensure that LED D5 illuminates. LEDs D2 and D4
should not be illuminated.
2. Bring the EVM out of RESET state by switching RESET (S1) to NORMAL. You should see the FAULT
LED (D4) blink once quickly, then remain unilluminated.
3. Bring the EVM out of MUTE state by switching MUTE (S2) to NORMAL.
4. Note that the EVM does not have volume control, configure your analog input for a reasonable audio
level before beginning audio playback.
5. Enable audio input playback and the EVM should begin driving audio out of the left and right speakers.
If resistor loads are used for testing instead of speakers, they will now be energized.

Class-D
Amplifier
OUT-A
OUT-B
OUT-C
OUT-D
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2 Setup By Mode
The following sections describe the setup and configuration for each output mode. The TPA3220DDV
EVM allows for two output modes: Stereo BTL and Mono PBTL.
2.1 BTL MODE (Stereo - 2 Speaker Outputs)
This mode is the same as described in Quick Start (BTL MODE).
2.2 PBTL MODE (Mono – 1 Speaker Output)
This mode provides one speaker output that is more powerful than each BTL output and is useful when
mono audio is to be played or when more power is needed.
Figure 4 illustrates the PBTL mode output configuration with 4 inductors.
Figure 4. Output Configuration PBTL - 4 Inductors

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2.2.1 Connections and Board Configuration
Figure 5 illustrates the connectors and jumpers on the EVM.
Figure 5. EVM Board With Connectors and Jumpers
Use the following steps when connecting and configuring the board:
1. Ensure the power supply is OFF. Connect power supply positive terminal to J1 PVDD (red) and
negative terminal to J1 GND (black).
2. Connect one speaker, power resistor load (2–8 Ω) to TPA3220EVM positive output terminal (J9
OUT1+ (red)) and other side of speaker, power resistor to TPA3220EVM negative output terminal (J9
OUT1– (black)).
3. Use a short banana cable to connect J2 OUT2+ to J9 OUT1+ and a second banana short banana
cable to connect J2 OUT2– to J9 OUT1–. This forms the parallel connection of both OUTx+ to the one
side of the speaker and parallel connection of both OUTx– to the other side of the speaker.
4. Check to make sure that the power supply is connected to J1 only and the speaker is connected to J9
or J2 only, as their colors are the same.
5. Input Configuration:
1. Differential Inputs: connect one differential XLR audio input to DIFF IN1 (J14). Install jumpers
J10, J11, J20, and J21 to position 1:2 which is labeled as RCA or XLR. Jumpers J4 and J12 must
be uninstalled for DIFF input.
2. Single-Ended Inputs: connect one single-ended RCA audio input to IN1P (J3). Install jumpers
J10, J11, J20, and J21 to position 1:2 which is labeled as RCA or XLR. Jumpers J4 and J12 must
be installed for SE input.
3. Audio Interface Board Input: Install jumpers J10, J11, J20, and J21 to position 2:3 which is
labeled as AIB. Jumpers J4 and J12 must be installed for SE input from the AIB or uninstalled for
DIFF input from the AIB.
6. Ensure that RESET S1 and MUTE S2 are in the lower positions of RESET and MUTE, respectively.
7. Check Table 2 for all necessary jumper and switch configurations.

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Table 2. Jumper and Switch Configurations (PBTL Mode)
Component Component Description Configuration for PBTL
J23 Gain/SLV Select MSTR-18dB
J24 N/A IN
J4, J12 Input DIFF or SE Select OUT = DIFF IN, IN = DIFF IN
J10, J11, J20, J21 AIB Input Select Position 1:2 for RCA/XLR,
Position 2:3 for AIB
J6 HEAD or AD Mode Select IN
J7, J8 PBTL or BTL Select IN
J22 VDD SEL Position 2:3 (GVDD)
J25 5V-PU SEL OUT
S1 RESET Control RESET
S2 MUTE Control MUTE
J13 AUTO RETRY OUT
J29 PVDD-IN IN
J26 12V-IN IN
J5 5V-IN IN
J27 3.3V-IN IN
J19 5V-PU EN OUT
J17 OSC Output No Connection
J16 Master or Slave Select Position 3:4 MASTER MODE
2.2.2 Power-Up
Ensure that required connections and configurations have been checked. The TPA3220EVM board can
now be powered on.
1. Enable the power supply from 12 V to 30 V and ensure that LED D5 illuminates. LEDs D2 and D4
should not be illuminated.
2. Bring the EVM out of RESET state by switching RESET (S1) to NORMAL. You should see the FAULT
LED (D4) blink once quickly, then remain unilluminated.
3. Bring the EVM out of MUTE state by switching MUTE (S2) to NORMAL.
4. Note that the EVM does not have volume control, configure your analog input for a reasonable audio
level before beginning audio playback.
5. Enable audio input playback and the EVM should begin driving audio out of the left and right speakers.
If resistor loads are used for testing instead of speakers, they will now be energized.

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3 Hardware Configuration
3.1 Indicator Overview (OTW_CLIP and FAULT)
The TPA3220EVM is equipped with LED indicators that illuminate when the FAULT or OTW_CLIP pin
goes low. See Table 3 and TPA3220 100-W Peak HD-Audio, Analog-Input, Class-D for more details.
Table 3. Fault and Clip Overtemperature Status
FAULT
LED Status OTW_CLIP LED Status Description
ON ON Overtemperature (OTE) or overload (OLP) or undervoltage (UVP). Junction temperature
higher than 125°C (OTE warning)
ON OFF Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C
OFF ON Junction temperature higher than 125°C (OTE warning)
OFF OFF Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
3.2 PWM Frequency Adjust
The TPA3220EVM allows for three oscillator frequency options by external configuration of the
FREQ_ADJ pin. The frequency adjust can be used to reduce interference problems while using a radio
receiver tuned within the AM band. These values should be chosen such that the nominal and the lower
value switching frequencies together results in the fewest cases of interference throughout the AM band.
The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in
master mode according to Table 4.
Table 4. Frequency Adjust Master Mode Selection (J16)
FREQ_ADJ (J16) Mode Resistor Selected to
GND or Pullup PWM Frequency
Master MODE 49.9 kΩ600 kHz
Master MODE AM1 30 kΩ533 kHz
Master MODE AM2 10 kΩ480 kHz
Slave MODE Pullup to 5 V N/A
Selecting Slave Mode configures the OSC_I/O pins as inputs to be slaved from an external differential
clock. In a master or slave system, interchannel delay is automatically set up between the switching
phases of the audio channels, which can be illustrated by no idle channels switching at the same time.
This will not influence the audio output, but only the switch timing to minimize noise coupling between
audio channels through the power supply. This will optimize audio performance and result in better
operating conditions for the power supply. The inter-channel delay will be set up for a slave device
depending on the polarity of the OSC_I/O connection such that slave mode 1 is selected by connecting
the OSC_I/O of the master device with the OSC_I/O of the slave device with the same polarity (+ to +
and – to –), while slave mode 2 is selected by connecting the OSC_I/Os with the inverse polarity (+ to –
and – to +).

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3.3 Modulation Modes (AD Mode and HEAD Mode)
The TPA3220EVM supports both AD modulation as well as HEAD modulation. In AD mode, each of the
two half-bridge outputs are continuously switching. AD mode is the default mode for the TPA3220EVM.
The EVM also supports HEAD mode modulation. HEAD mode also switches both half bridge outputs but
also optimizes the switching for lower power loss at idle as well as increased EMI performance at cost of
some performance. The device accomplishes this by reducing its duty cycle at idle and while playing small
signals. At higher output levels HEAD mode will also reduce the switching on one of the half bridges. The
modulation mode can be controlled through jumper J6 on the EVM as follows:
Table 5. HEAD and AD Mode Selection
J6 Jumper State Modulation Mode
IN AD Mode
OUT HEAD Mode
More information on the differences between HEAD mode and AD mode as well as performance data is
found in TPA3220 100-W Peak HD-Audio, Analog-Input, Class-D.
3.4 Output Mode Selection
The TPA3220 does not use discrete mode pins and therefore relies solely on the states of the IN2_M and
IN2_P pins. Connecting the IN2_M and IN2_P pins to regular high output impedance audio outputs by
removing J7 and J8 puts the TPA3220 into BTL mode (2 x stereo outputs). Tying the IN2_M and IN2_P
pins to GND by installing J7 and J8 puts the TPA3220 into PBTL mode (1 x mono output). This is
summarized in Table 6:
Table 6. Output Mode and Modulation Mode Selection
Input Jumpers
J7 and J8 Input Mode Output
Configuration Description
IN2_M IN2_P
OUT OUT 1N / 2N + 1 2 × BTL Stereo BTL output configuration
IN IN 1 × PBTL Mono paralleled BTL configuration. Connect OUT1+ to OUT2+ and
OUT1– to OUT2–.
3.5 Audio Front End
The TPA3220EVM includes options for single-ended or differential input signals. A configurable front end
is built into the TPA3220 so that both single-ended and differential inputs can achieve the full scale output
of the TPA3220 device without need for external front end op-amp. Note that when EVM RCA or XLR
connectors are used, jumpers J11, J10, J21, and J20 must be installed in position 1:2 named XLR or
RCA.
• Single-ended input can be provided through RCA to inputs J3 and J18. Uninstall jumpers J4 and J12
using SE input so that the TPA3220 front-end will be configured for SE input.
• Differential input can be provided through XLR to inputs J14 and J15. Install jumpers J4 and J12 when
using DIFF input so that the TPA3220 front-end will be configured for DIFF input.
Input can also be provided through an audio plug-in board on J28. For this input type, change jumpers
J11, J10, J21, and J20 to position 2:3 named AIB.
See the EVM schematic section (Section 4.3) for complete details.

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3.6 EVM Power Tree
The TPA3220EVM includes a few options for power configuration so that various input types can be
evaluated.
3.6.1 TPA3220 Supplies
The TPA3220 device has a few power supplies which each have their own voltage range and rules.
Details for each supply are as shown:
•PVDD – This is the main device supply which accepts from 7 V to 30 V. Power output of the device is
derived solely from PVDD and therefore it is important to configure this supply according to the chosen
output configuration and load. Complete details are included in TPA3220 100-W Peak HD-Audio,
Analog-Input, Class-D.
•VDD – This supply is used for the non-PVDD power of the device for blocks such as the front-end and
control circuitry. The TPA3220 internal 5-V LDO is also powered by this pin. VDD can be powered by 5
V directly if using the TPA3220 with the internal regulator OFF. In this case, tie the GVDD and AVDD
pins directly to VDD using J22 position 2:3. When the internal regulator is used, VDD must be between
7 V and PVDD through J22 position 1:2 or providing an external voltage to V-EXT. GVDD and AVDD
are only 5-V tolerant so J22 cannot be in position 2:3. The 5 V TP or 5 V through J24 must be used to
power GVDD and AVDD separate from VDD in this case.
•GVDD and AVDD – These pins are used for the gate drive and analog supply of the device. These
pins accept only 5 V. When the internal regulator is used, these pins are fed internal to the device, no
external connection is necessary. When the internal regulator is OFF, these pins need 5 V through the
TP or 5 V through J24 as previously mentioned.
Table 7. Power Supply Summary
PVDD (V) VDD (V) AVDD and GVDD Internal Regulator
Status Note
7.0 to 30.0 5.0 Externally Provided OFF Most Efficient
7.0 to 30.0 7.0 to PVDD No Connection to VDD ON 5 V internally generated
X 5.0 to 7.0 - - Not allowed (do not use)
3.6.2 TPA3220EVM Power Options
All options in this section assume the TPA3220 internal 5-V regulator is OFF and that 5 V is provided
externally to VDD, AVDD, and GVDD. J22 must be in position 2:3 to connect VDD to the AVDD and
GVDD nodes. The major input configurations are listed in the following sections by the supplies available.
3.6.2.1 PVDD Only (12 V to 30 V)
This power mode is the default setup when the board is tested and shipped. The user can connect any
valid supply voltage to J1 and the onboard LDOs will generate the required non-PVDD voltages. PVDD
itself always connects directly to the TPA3220 PVDD pins. Setup for this mode is the same as described
in Quick Start (BTL MODE).
3.6.2.2 PVDD (12 V to 30 V) and One Non-5-V Supply
This power mode is useful for certain applications where a system has one higher voltage used for PVDD
and a second lower voltage that may be used for device pullups and other supplies (VDD, GVDD, and
AVDD). The PVDD voltage can still be connected to J1 but jumpers J29 and J24 as well as resistor R37
must be removed.
The non-5-V supply should be connected to jumper V-EXT (7 V to 30 V only) and J25 in position 2:3 to
select V-EXT as the input for U5. Install J19 to enable U5. Install R16 to connect 5VPU-VR to 5V-PU and
J22 in position 2:3 to connect 5V-PU to VDD.

6 Ÿ
3 Ÿ
4 Ÿ
2 Ÿ
8 Ÿ
cut off
1 1 50.3 kHz
2 L C 2 10 H 1 F
-= = =
p ´ p m ´ m
F
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3.6.2.3 PVDD (12 V to 30 V) and 5-V Supply
This power mode is most useful for systems in which a 5-V supply is already available due to additional
circuitry like an MCU or wireless module. On the EVM, this is also the preferred way to measure efficiency
of the TPA3220 device. The PVDD voltage can still be connected to J1 but jumpers J29 and J24 must be
removed. The 5-V supply should be connected to TP33 (5V-PU) or TP34 (5V-EXT).
If R3 is installed, these nodes will be connected and at the same voltage. The same 5-V input will be used
for the TPA3220 supplies (AVDD, VDD, and GVDD), the EVM reset control (U7), all TPA3220 device
pullups (Reset, HEAD, FREQ_ADJ, Fault, OTW_CLIP), and status LEDs D4 and D2.
The two 5-V supplies can be isolated by removing R3. Once R3 is removed, 5 V can be fed to only the
TPA3220 supplies through TP34 (5V-EXT) and all other 5 V needs can be powered through TP33 (5V-
PU).
Either approach can be used to measure efficiency, but the most accurate numbers will be with the two 5-
V supplies separated so the TPA3220 supply voltage is isolated and measured independently of board
LEDs, reset control, and so forth.
3.7 LC Response and Overview
Included near the output of the TPA3220 device are four output LC filters. These output filters filter the
PWM output leaving only the audio content at high power which is fed to the speakers. The board uses a
Sagami®10-µH inductor and 1-µF film capacitor to form this LC filter. Using the equations listed in LC
Filter Design, the filter low pass cut-off is as follows:
(1)
The frequency response of the filter per output load is illustrated in Figure 6.
Figure 6. Filter Frequency Response
Figure 6 is taken directly from the LC Filter Calculator tool available on TI.com (SLAC729). The tool is
configured for BTL common mode with values of 10 µH and 1 µF for the filter. This tool is also helpful
when designing a different board featuring one of TI’s class-D amplifiers.

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The Sagami inductor used (7G14J-100M-R) has a saturation current of 18 A. This was selected for the
EVM since the TPA3220 supports a maximum short-circuit output current of 10 A. The inductance versus
current curve for a selected inductor is very important. It is essential for the inductor to maintain at least 5
µH of inductance at the maximum short-circuit current of the power amplifier. The Sagami inductance
versus current curve is available in the 7G14J-100M-R data sheet on the Sagami web site.
Although not required, shielded inductors are used on the EVM as they reduce EMI.
3.8 Reset Circuit and POR
The TPA3220EVM includes RESET supervision so that the TPA3220 device will remain in reset until all
power rails are up and stable. The RESET supervisor also ensures that the device will be put into reset if
one of the power rails experiences a brown out. This circuit, combined with the RESET switch (S1) help
ensure that the TPA3220 can be placed in reset easily, as needed, or automatically if there is a power
supply issue. Figure 7 illustrates the circuit.
Figure 7. RESET Circuit
3.9 Analog-Input-Board Connector (J28)
The Analog-Input-Board (AIB) connector allows for cross compatibility with several Analog Plug-in
Modules (APMs) offered by TI. This generic connector provides access to common board connections
such as analog input, analog output, Fault and overtemperature warning (OTW) error reporting, common
board voltages (12 V, 3.3 V, and so forth), and EVM reset. These plug-in modules allow for an application-
specific front end to be plugged into the TPA3220EVM with ease. Examples of plug-in modules include
front ends for guitar amplifier, karaoke, wireless sub-woofer, and front-end audio crossover.
Figure 8. AIB EVM Connector

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As Figure 8 shows, the AIB connector includes the following pins, associated specifications are listed in
Table 9.
Table 8. AIB Connector (J28) Pinout
Pin
#Function Description Audio EVM Input/Output
1 Amp Out A Speaker-level output from audio Class-D EVM (SE or one side of BTL) O
2 Amp Out B Speaker-level output from audio Class-D EVM (SE or one side of BTL) O
3 PVDD PVDD voltage supply from audio Class-D EVM (variable voltage depending on Class-D EVM
use) O
4 GND Ground reference between audio plug-in module and audio class-D EVM -
5 NC - -
6 NC - -
7 3.3 V 3.3-V supply from EVM; used for powering Audio Plug-in Module O
8 3.3 V 3.3-V supply from EVM; used for powering Audio Plug-in Module O
9 12 V 12-V supply from EVM; used for powering Audio Plug-in Module O
10 EN and RESET Assert enable and reset control for audio class-D EVM (active low) I
11 Analog IN_A Analog audio input A (analog in EVM) , Master I2S Bus (digital in EVM) I
12 NC - -
13 Analog IN_B Analog audio input B (analog in EVM) , Bit Clock I2S Bus (digital in EVM) I
14 CLIP_OTW Clipping detection, overtemperature warning, or both from audio class-D EVM (active low) O
15 Analog IN_C Analog audio input C (analog in EVM) , Frame Clock I2S Bus (digital in EVM) I
16 FAULT Fault detection from audio Class-D EVM (Active Low) O
17 Analog IN_D Analog audio Input D (analog in EVM) , Data In I2S Bus (digital in EVM) I
18 NC - -
19 NC - -
20 NC - -
21 GND Ground reference between audio plug-in module and audio class-D EVM -
22 GND Ground reference between audio plug-in module and audio class-D EVM -
23 NC - -
24 NC - -
25 NC - -
26 NC - -
27 Amp Out C Speaker-level output from audio class-D EVM (SE or one side of BTL) O
28 Amp Out D Speaker-level output from audio class-D EVM (SE or one side of BTL) O
Table 9. AIB Power Rail Specifications
EVM Power Rails Always Available Voltage Range Max Current Source
PVDD Yes 15–80 V 500 mA External Source
12 V Yes 12 V 500 mA LDO
3.3 V Yes 3.3 V 100 mA LDO

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4 EVM Design Documents
This section contains the EVM board layouts, schematics, and bill of materials (BOM).
4.1 TPA3220 Board Layouts
Figure 9 and Figure 10 illustrate the EVM board layouts.
Figure 9. TPA3220 EVM Top Composite Assembly

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TPA3220 Evaluation Module
Figure 10. TPA3220 EVM Bottom Composite Assembly

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TPA3220 Evaluation Module
4.2 TPA3220 Board Layouts
Figure 11 shows the EVM board dimensions.
Figure 11. TPA3220 EVM Board Dimensions

R48
IN1P
IN1M
OUT1+
OUT1-
IN2P
IN2M
OUT2+
OUT2-
RCA
INPUT 1 XLR
100k
R43
100k
R9
AUDIO
BOARD
IN2+_AIB
IN2-_AIB
IN1-_AIB
IN1+_AIB
FROM DUT OTW_CLIP
FAULT J30
GND
ALIGNMENT
HEADER
AIB
RESET-SW
RESET 1.00k
R57
INTERFACE
OUT1M
OUT1P
OUT2P
OUT2M
RST-AIB
0
R67
3.3V
GND GND
3.3V
12V
PVDD
0R64
0R63
0R66
0R65
TO DUT
From DUT
TO DUT
TO DUT
From DUT
TO DUT
100k
R45
1000pF
C21
100k
R25
1000pF
C57
100k
R70
AUGNDL
AUGNDL
AUGNDL
AUGNDR
AUGNDR
AUGNDR
RCA
INPUT 2 XLR
1
2
3
J10
IN1+
1
2
3
J11
IN1-
22pFC20
18.0k
R47
22pFC23
18.0k
R49
0
R4
0
R12
2.00k
R11
GND
220pF
C26
GND 220pF
C37
0
R52
0
R59
IN1-_XLR
22pFC62
22pF
C65
0
R44
0
R46
GND
220pF
C45
GND 220pF
C61
0
R60
0
R62
1µF
C17
1µF
C28
1µF
C55
1µF
C63
1
2
3
J20
IN2+
1
2
3
J21
IN2-
IN2-_XLR
J12
IN2 SE
GND
GND
J4
IN1 SE
GND
TP17
IN1+
TP29
IN1-
TP30
IN2+
TP31
IN2-
1
3
56
4
2
7
910
8
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
J28
MH1
MH2 1
2
3
4
+
GND
SHIELD
J14
DIFF IN1
MH1
MH2 1
2
3
4
+
GND
SHIELD
J15
DIFF IN2
1
2
3
J3
IN1P
1
2
3
J18
IN2P
10.0k
R20
IN1+_AIB
IN1-_AIB
IN2+_AIB
IN2-_AIB
3.3V
IN1+_RCA-XLR
IN1-_XLR
IN2+_RCA-XLR
IN2-_XLR
IN2+_RCA-XLR
IN1+_RCA-XLR
OUT1M OUT1P
OUT2POUT2M
2.00k
R14
2.00k
R18
2.00k
R22
18.0k
R50
18.0k
R51
1
2
3
J7
IN2P
5V-PU
GND
1
2
3
J8
IN2M
5V-PU
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TPA3220 Evaluation Module
4.3 TPA3220 EVM Schematics
Figure 12 through Figure 14 illustrate the TPA3220 EVM schematics.
Figure 12. TPA3220 EVM Schematic 1

Q2
5V-PU
GND GND
Orange
D2
OTW_CLIP
5V-PU
GND GND
MONITORS
100
R33
100
R35
FAULT
GND GND
GND GND
GND GND
GND GND
GND
PVDD
GND
GND
PVDD
GNDGND
GNDGND
RESET
GND
GND
GVDD
0.1uF
C22
GND
IN1_P
IN1_M
5V-PU
SLAVE MODE
MASTER MODE (600 kHz)
MASTER MODE AM1 (533 kHz)
MASTER MODE AM2 (480 kHz)
GND
FREQUENCY
ADJUST
OUT2_M
IN2_M
IN2_P
1.00k
R29
1.00k
R31
100pF
C64
100
R23
100pF
C58
100
R19
100pF
C30
100
R10
100pF
C19
100
R5
OUT1_P
OUT1_M
OUT1+
OUT1-
OUT2+
OUT2-
12
34
56
78
J16
1µF
C56
3.30
R54
GND
GND
GND
GND
1µF
C53
1µF
C51
1µF
C50
TP2
OUT1_P
TP5
OUT1_M
TP9
OUT2_M
TP4 PVDD
TP8 PVDD
TP3
OUT1+
TP10
OUT1-
TP11
OUT2+
TP12
OUT2-
J13
FAULT
0
R30
VDD
GVDD
FAULT
OTW_CLIP
GND
OSCILLATOR
SYNC
INTERFACE
4
1
2
3
J17
1µF
C41
TP26
FREQ_ADJ
TP21
IN1M
TP22
IN2P
TP23
IN2M
TP19
AVDD
TP15
GVDD
TP16
VDD
1000pF
100V
C25
1000pF
100V
C36
1000pF
100V
C44
1000pF
100V
C60
10µH
L6
TP20
IN1P
OUT1+
OUT1-
OUT2-
OUT2+
IN1P
IN1M
IN2P
IN2M
FROM ANALOG
OTW_CLIP
TO
ANALOG
FRONT END
GNDGND
6
4
5
13
S1
RESET
GND
0.1uF
C67
GND
0.1uF
C18
4.02k
R26
GND
PVDD
100k
R6
GND
GND 1
GND 2 MR
5
RESET 3 VDD
4
U7
TPS3802K33DCKR
GND
RESET CONTROL
RESET-SW
RESET
RESET-SW
Q1
TO AIB
OTW_CLIP
FAULT
CONTROLLER
RESET-SW
1µF
100V
C32
1µF
100V
C33
1µF
100V
C47
1µF
100V
C48
1µF
100V
C42
1µF
100V
C34
Red
D4
FAULT
0.033µF
C27
0.033µF
C29
OUT2_P
TP7
OUT2_P
0.033µF
C52
0.033µF
C54
TP6
GND
GND
OSCM
OSCP
OSCM
OSCP
FREQ_ADJ
FREQ_ADJ
TP1
OTW_CLIP
TP14
FAULT
5V-PU
J6
HEAD
GND
TP18
HEAD
10.0k
R68
49.9k
R15
30.0k
R17
47.0k
R24
47.0k
R28
HEAD
CMUTE
IN1_P
IN1_M
IN2_P
IN2_M
GAIN/SLV
VDD
AVDD
100k
R76
GAIN/SLV MATRIX
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J23
Gain/SLV Select
47.0k
R72
100k
R77
5.60k
R41
GND GND GNDGND GND GND GND
16.0k
R36
GND
MSTR-18dB
MSTR-24dB
MSTR-30dB
MSTR-34dB
SLV-18dB
SLV-24dB
SLV-30dB
SLV-34dB
100k
R42
100k
R61
75.0k
R73
51.0k
R74
39.0k
R34
47.0k
R27
51.0k
R21
AVDD
GND
6
4
5
13
S2
CMUTE
GND
5V-PU
PVDD
GVDD
3.32
R75
1µF
C66
Using 10uH and 1uF, Cut-off is 50kHz
10µH
L2
10µH
L3
10µH
L4
10µH
L5
1µF
C24
1µF
C35
1µF
C43
1µF
C59
NT2
Net-Tie
AUGNDR
AUGNDR
AUGNDR
AUGNDL
AUGNDL
NT1
Net-Tie
AUGNDL
OUT1_P
OUT1_M
OUT2_P
OUT2_M
TP24
GAIN/SLV
1.00k
R38
0.033µF
C16
GND
47.0k
R1
5V-PU
5V-PU
5V-PU
FRONT END
1.00k
R32
3.30
R55
3.30
R56
3.30
R53
V-EXT
1
2
3
J22
VDD SEL
0
R37
GVDD
TP34
5V-EXT
TP33
5V-PU 5V
0
R3
1000µF
C31
1000µF
C46
TP35
CMUTE
J24
J9
J2
TP13
RESET
VDD-SEL
GVDD
20.0k
R69
39.0k
R71
75.0k
R78
VDD
1
CMUTE
17
IN1_P
8
IN1_M
9
FREQ_ADJ 14
OSCM
12
OSCP
13
GND 5
GND 6
AVDD
21
HEAD
11
IN2_P
15
IN2_M
16
RESET
10
FAULT 4
GAIN/SLV
2
OTW_CLIP 3
GVDD
22
BST1_P 44
BST1_M 43
BST2_M 23
BST2_P 24
GND 42
GND 41
GND 25
GND 26
GND 34
GND 33
OUT1_P 40
OUT1_P 39
OUT1_M 35
OUT2_P 32
OUT2_M 27
OUT2_M 28
PVDD
38 PVDD
37 PVDD
36
PVDD
31 PVDD
30 PVDD
29
GND 18
GND 19
GND 20
GND 7
GND 45
TPA3220DDWR
U4
10.0k
R79
10.0k
R80
GND
5V-PU
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TPA3220 Evaluation Module
Figure 13. TPA3220 EVM Schematic 2