Texas Instruments eInfochips TMDXEVM6657L Product manual

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012 TMDXEVM6657LE
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TMDXEVM6657L / TMDXEVM6657LE
Technical Reference Manual
Version 1.1
Literature Number: SPRUHG7
Revised August 2012
Document Copyright
Publication Title:
C6657 Lite EVM Technical Reference Manual
All Rights Reserved. Reproduction, adaptation, or
translation without prior written permission is
prohibited, except as allowed under the copyright laws.

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SPRUHG7 - Revised August 2012 TMDXEVM6657LE
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EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMER
Not for Diagnostic Use: For Feasibility Evaluation Only in Laboratory/Development Environments
The EVM may not be used for diagnostic purposes.
This EVM is intended solely for evaluation and development purposes. It is not intended for use and may not be
used as all or part of an end equipment product.
This EVM should be used solely by qualified engineers and technicians who are familiar with the risks associated
with handling electrical and mechanical components, systems and subsystems.
Your Obligations and Responsibilities
Please consult the EVM documentation, including but not limited to any user guides, set up guides or getting
started guides and other warnings prior to using the EVM. Any use of the EVM outside of the specified operating
range may cause danger to the users and/or produce unintended results, inaccurate operation, and permanent
damage to the EVM and associated electronics. You acknowledge and agree that:
You are responsible for compliance with all applicable Federal, State and local regulatory
requirements (including but not limited to Food and Drug Administration regulations, UL, CSA, VDE, CE,
RoHS and WEEE,) that relate to your use (and that of your employees, contractors or designees) of the EVM
for evaluation, testing and other purposes.
You are responsible for the safety of you and your employees and contractors when using or handling the
EVM. Further, you are responsible for ensuring that any contacts or interfaces between the EVM and any
human body are designed to be safe and to avoid the risk of electrical shock.
You will defend, indemnify and hold TI, its licensors and their representatives harmless from and against any
and all claims, damages, losses, expenses, costs and liabilities (collectively, “Claims”) arising out of or in
connection with any use of the EVM that is not in accordance with the terms of this agreement. This
obligation shall apply whether Claims arise under the law of tort or contract or any other legal theory, and
even if the EVM fails to perform as described or expected.
Warning
The EVM board may get very hot during use. Specifically, the DSP, its heat sink and power supply circuits all
heat up during operation. This will not harm the EVM. Use care when touching the unit when operating or
allow it to cool after use before handling. If unit is operated in an environment that limits free air flow, a fan
may be needed.

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Preface
About this Document
This document is a Technical Reference Manual for the TMS320C6657 Evaluation Module
(C6657 Lite EVM) designed and developed by eInfochips Limited for Texas Instruments, Inc.
Notational Conventions
This document uses the following conventions:
Program listings, program examples, and interactive displays are shown in a mono-spaced
font. Examples use bold for emphasis, and interactive displays use bold to distinguish
commands that you enter from items that the system displays (such as prompts, command
output, error messages, etc.).
Square brackets ( [ and ] ) identify an optional parameter. If you use an optional parameter,
you specify the information within the brackets. Unless the square brackets are in a bold
typeface, do not enter the brackets themselves.
Underlined, italicized non-bold text in a command is used to mark place holder text that should
be replaced by the appropriate value for the user‟s configuration.

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Trademarks
The Texas Instruments logo and Texas Instruments are registered trademarks of Texas Instruments.
Trademarks of Texas Instruments include: TI, XDS, Code Composer, Code Composer Studio, Probe Point, Code
Explorer, DSP/BIOS, RTDX, Online DSP Lab, TMS320, TMS320C54x, TMS320C55x, TMS320C62x,
TMS320C64x, TMS320C67x, TMS320C5000, and TMS320C6000.
MS-DOS, Windows, Windows XP, and Windows NT are trademarks of Microsoft Corporation.
UNIX is a registered trademark of The Open Group in the United States and other countries.
MicroTCA and AMC (or AdvancedMC) are trademarks of PICMG.
All other brand, product names, and service names are trademarks or registered trademarks of their respective
companies or organizations.

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Document Revision History
Release
Chapter
Description of Change
0.1
All
Initial Draft
1.1
1.1
TMDXEVM6657LE image changed
Acronyms
Acronym
Description
AMC or AdvancedMC
Advanced Mezzanine Card
CCS
Code Composer Studio
DDR3
Double Data Rate 3 Interface
DIP
Dual-In-Line Package
DSP
Digital Signal Processor
DTE
Data Terminal Equipment
EEPROM
Electrically Erasable Programmable Read Only Memory
EMAC
Ethernet Media Access Controller
EMIF
External Memory Interface
EVM
Evaluation Module
FPGA
Field Programmable Gate Array
I2C
Inter Integrated Circuit
IPMB
Intelligent Platform Management Bus
IPMI
Intelligent Platform Management Interface
JTAG
Joint Test Action Group
LED
Light Emitting Diode
McBSP
Multi Channel Buffered Serial Port
MCH
MicroTCA Carrier Hub
MTCA or MicroTCA
Micro Telecommunication Computing Architecture
MMC
Module Management Controller
PCIe
PCI Express
PICMG®
PCI Industrial Computer Manufacturers Group
RFU
Reserved for Future Use
SDRAM
Synchronous Dynamic Random Access Memory
SERDES
Serializer-Deserializer
SGMII
Serial Gigabit Media Independent Interface
SRIO
Serial RapidIO
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
XDS560v2
Texas Instruments’ System Trace Emulator

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Table of Contents
1. OVERVIEW............................................................................................................................................................ 11
1.1 KEY FEATURES .............................................................................................................................................. 11
1.2 FUNCTIONAL OVERVIEW.............................................................................................................................. 12
1.3 BASIC OPERATION ........................................................................................................................................ 14
1.4 BOOT MODE AND BOOT CONFIGURATION SWITCH SETTING............................................................. 15
1.5 POWER SUPPLY............................................................................................................................................. 16
2. INTRODUCTION TO THE C6657 LITE EVM BOARD ...................................................................................... 17
2.1 MEMORY MAP................................................................................................................................................. 17
2.2 EVM BOOT MODE AND BOOT CONFIGURATION SWITCH SETTINGS................................................. 22
2.3 BOARD REVISION ID...................................................................................................................................... 23
2.4 JTAG - EMULATION OVERVIEW.................................................................................................................. 24
2.4.1 JTAG –TMDXEVM6657L ............................................................................................................................... 24
2.4.2 JTAG –TMDXEVM6657LE............................................................................................................................. 25
2.4.2.1. XDS560V2 MEZZANINE EMULATOR BOOTING.................................................................................... 26
2.5 CLOCK DOMAINS ........................................................................................................................................... 27
2.6 I2C BOOT EEPROM / SPI NOR FLASH........................................................................................................ 28
2.7 FPGA................................................................................................................................................................. 29
2.8 ETHERNET SWITCH ....................................................................................................................................... 30
2.9 SERIAL RAPIDIO (SRIO) INTERFACE ......................................................................................................... 31
2.10 DDR3 EXTERNAL MEMORY INTERFACE................................................................................................... 31
2.11 16-BIT ASYNCHRONOUS EXTERNAL MEMORY INTERFACE (EMIF-16) & UPP ................................. 32
2.12 HYPERLINK INTERFACE............................................................................................................................... 33
2.13 PCIE INTERFACE............................................................................................................................................ 33
2.14 MCBSP INTERFACE....................................................................................................................................... 34
2.15 UART INTERFACE .......................................................................................................................................... 35
2.16 MODULE MANAGEMENT CONTROLLER (MMC) FOR IPMI..................................................................... 36
2.17 EXPANSION HEADER .................................................................................................................................... 36
3. C6657 LITE EVM BOARD PHYSICAL SPECIFICATIONS .............................................................................. 37
3.1 BOARD LAYOUT............................................................................................................................................. 37
3.2 CONNECTOR INDEX....................................................................................................................................... 38
3.2.1 560V2_PWR1, XDS560V2 MEZZANINE POWER CONNECTOR............................................................... 39
3.2.2 AMC1, AMC EDGE CONNECTOR................................................................................................................. 39

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3.2.3 COM1, UART 3-PIN CONNECTOR................................................................................................................ 41
3.2.4 COM_SEL1, UART ROUTE SELECT CONNECTOR................................................................................... 41
3.2.5 DC_IN1, DC POWER INPUT JACK CONNECTOR...................................................................................... 42
3.2.6 EMU1, TI 60 PIN DSP JTAG CONNECTOR.................................................................................................. 42
3.2.7 HYPERLINK1, HYPERLINK CONNECTOR.................................................................................................. 43
3.2.8 J4 AND J5, EMULATION PATH SELECTION CONNECTOR..................................................................... 44
3.2.9 LAN1, ETHERNET CONNECTOR.................................................................................................................. 44
3.2.10 PMBUS1, PMBUS CONNECTOR FOR SMART REFLEX CONTROL................................................... 45
3.2.11 TAP_FPGA1, FPGA JTAG CONNECTOR (FOR FACTORY USE ONLY) ............................................ 45
3.2.12 SBW_MMC1, MSP430 SPYBIWIRE CONNECTOR (FOR FACTORY USE ONLY)............................. 45
3.2.13 TEST_PH1, EXPANSION HEADER (EMIF-16, SPI, GPIO, TIMER I/O, I2C, MCBSP AND UART).... 46
3.2.14 USB1, MINI USB CONNECTOR ................................................................................................................ 47
3.3 DIP AND PUSHBUTTON SWITCHES............................................................................................................ 48
3.3.1 RST_COLD1, COLD RESET........................................................................................................................... 48
3.3.2 RST_FULL1, FULL RESET............................................................................................................................. 48
3.3.3 RST_WARM1, WARM RESET........................................................................................................................ 48
3.3.4 SW3, DSP CONFIGURATION ........................................................................................................................ 48
3.3.5 SW4, DSP BOOT MODE................................................................................................................................. 49
3.4 TEST POINTS................................................................................................................................................... 50
3.5 SYSTEM LEDS................................................................................................................................................. 51
4. C6657 LITE EVM SYSTEM POWER REQUIREMENTS................................................................................... 54
4.1 POWER REQUIREMENTS.............................................................................................................................. 54
4.2 POWER SUPPLY DISTRIBUTION................................................................................................................. 56
4.2.1 CVDD AND VCC1V0 DESIGN........................................................................................................................ 57
4.2.2 VCC3V3_AUX AND VCC1V5 DESIGN.......................................................................................................... 58
4.2.3 VCC5 DESIGN.................................................................................................................................................. 59
4.3 POWER SUPPLY BOOT SEQUENCE........................................................................................................... 59
5. C6657 LITE EVM FPGA FUNCTIONAL DESCRIPTION .................................................................................. 63
5.1 FPGA OVERVIEW............................................................................................................................................ 63
5.2 FPGA SIGNALS DESCRIPTION.................................................................................................................... 63
5.3 SEQUENCE OF OPERATION ........................................................................................................................ 68
5.3.1 POWER-ON SEQUENCE................................................................................................................................ 69
5.3.2 POWER OFF SEQUENCE .............................................................................................................................. 69
5.3.3 BOOT CONFIGURATION TIMING ................................................................................................................. 70

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5.3.4 BOOT CONFIGURATION FORCED IN I2C BOOT....................................................................................... 71
5.4 RESET DEFINITION ........................................................................................................................................ 71
5.4.1 RESET BEHAVIOR.......................................................................................................................................... 71
5.4.2 RESET SWITCHES AND TRIGGERS............................................................................................................ 71
5.5 SPI PROTOCOL............................................................................................................................................... 72
5.5.1 FPGA-DSP SPI PROTOCOL .......................................................................................................................... 72
5.5.2FPGA- CDCE62005 (CLOCK GENERATOR) SPI PROTOCOL.................................................................. 74
5.6 FPGA CONFIGURATION REGISTERS......................................................................................................... 75
5.6.1 FPGA CONFIGURATION REGISTERS SUMMARY .................................................................................... 75
5.6.2 FPGA CONFIGURATION REGISTERS DESCRIPTIONS............................................................................ 76

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List of Figures
FIGURE 1.1: BLOCK DIAGRAM OF TMDXEVM6657L.............................................................................................................12
FIGURE 1.2: BLOCK DIAGRAM OF TMDXEVM6657LE..........................................................................................................13
FIGURE 1.3: TMDXEVM6657L ..............................................................................................................................................14
FIGURE 1.4: TMDXEVM6657LE............................................................................................................................................15
FIGURE 2.1: EVM BOARD REVISION .......................................................................................................................................23
FIGURE 2.2: TMDXEVM6657L JTAG EMULATION................................................................................................................24
FIGURE 2.3: TMDXEVM6657LE JTAG EMULATION.............................................................................................................25
FIGURE 2.3: C6657 LITE EVM CLOCK DOMAINS....................................................................................................................27
FIGURE 2.4: C6657 LITE EVM CLOCK DOMAINS....................................................................................................................28
FIGURE 2.5: C6657 LITE EVM FPGA CONNECTIONS............................................................................................................29
FIGURE 2.6: C6657 LITE EVM ETHERNET PHY ROUTING.....................................................................................................30
FIGURE 2.7: C6657 LITE EVM SRIO PORT CONNECTIONS ..................................................................................................31
FIGURE 2.8: C6657 LITE EVM DDR3 INTERFACE .................................................................................................................31
FIGURE 2.9: C6657 LITE EVM EMIF16 INTERFACE ..............................................................................................................32
FIGURE 2.10: C6657 LITE EVM HYPERLINK INTERFACE.......................................................................................................33
FIGURE 2.11: C6657 LITE EVM PCIE INTERFACE .................................................................................................................33
FIGURE 2.12: C6657 LITE EVM MCBSP INTERFACE ............................................................................................................34
FIGURE 2.13: C6657 LITE EVM MCBSP CLOCK GENERATION BY FPGA............................................................................34
FIGURE 2.14: C6657 LITE EVM UART CONNECTIONS .........................................................................................................35
FIGURE 2.15: C6657 LITE EVM MMC CONNECTIONS FOR IPMI..........................................................................................36
FIGURE 3.1: C6657 LITE EVM BOARD ASSEMBLY LAYOUT –TOP VIEW..............................................................................37
FIGURE 3.2: C6657 LITE EVM BOARD LAYOUT –BOTTOM VIEW...........................................................................................38
FIGURE 3.3: COM_SEL1 JUMPER SETTINGS.........................................................................................................................41
FIGURE 3.4: HYPERLINK CONNECTOR ....................................................................................................................................43
FIGURE 3.5: SW3 DEFAULT SETTINGS.....................................................................................................................................48
FIGURE 3.6: SW5 DEFAULT SETTINGS.....................................................................................................................................49
FIGURE 3.7: BOARD TEST POINTS (TOP)................................................................................................................................50
FIGURE 3.8: BOARD TEST POINTS (BOTTOM).........................................................................................................................50
FIGURE 3.9: BOARD LEDS.......................................................................................................................................................52
FIGURE 3.10: TMDXEVM6657LE BOARD ADDITIONAL LEDS..............................................................................................52
FIGURE 4.1: C6657 LITE EVM POWER CONSUMPTION .........................................................................................................55
FIGURE 4.2: C6657 LITE EVM POWER GENERATION TOPOLOGY.........................................................................................56
FIGURE 4.3: CVDD AND VCC1V0 DESIGN ON C6657 LITE EVM.........................................................................................57
FIGURE 4.4: VCC3V3_AUX DESIGN ON C6657 LITE EVM..................................................................................................58
FIGURE 4.5: VCC1V5 POWER DESIGN ON C6657 LITE EVM...............................................................................................58
FIGURE 4.6: VCC5 POWER DESIGN ON C6657 LITE EVM....................................................................................................59
FIGURE 4.7: INITIAL POWER UP SEQUENCE TIMING DIAGRAM...............................................................................................61
FIGURE 4.8: POWER DOWN SEQUENCE TIMING DIAGRAM .....................................................................................................62
FIGURE 5.1: POWER-ON RESET BOOT CONFIGURATION TIMING...........................................................................................70
FIGURE 5.2: RESET-FULL SWITCH/TRIGGER BOOT CONFIGURATION TIMING........................................................................70
FIGURE 5.3: SPI ACCESS FROM TMS320C6657 TO FPGA (WRITE /HIGH LEVEL)............................................................73
FIGURE 5.4: SPI ACCESS FROM TMS320C6657 TO FPGA (WRITE)..................................................................................73
FIGURE 5.5: SPI ACCESS FROM TMS320C6657 TO FPGA (READ /HIGH LEVEL)..............................................................73
FIGURE 5.6: SPI ACCESS FROM TMS320C6657 TO FPGA (READ)....................................................................................74
FIGURE 5.7: SPI ACCESS FROM FPGA TO CDCE62005 (WRITE)......................................................................................74
FIGURE 5.8: SPI ACCESS FROM FPGA TO CDCE62005 (READ)........................................................................................74

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List of Tables
TABLE 2.1: TMS320C6657 MEMORY MAP.............................................................................................................................18
TABLE 2.2: BOOT CONFIGURATION SELECTION ......................................................................................................................22
TABLE 2.3: PCA/PCB REVISION DESCRIPTION .......................................................................................................................23
TABLE 2.4: EMULATOR SELECTION USING J4 AND J5.............................................................................................................25
TABLE 2.5: CLOCK CONFIGURATION........................................................................................................................................27
TABLE 2.6: LED INDICATION....................................................................................................................................................30
TABLE 2.7: MCBSP CLOCK AND FRAME SYNC GENERATION FROM TCLK ...........................................................................35
TABLE 3.1: C6657 LITE EVM BOARD CONNECTORS .............................................................................................................38
TABLE 3.2: XDS560V2POWER CONNECTOR PIN OUT...........................................................................................................39
TABLE 3.3: AMC EDGE CONNECTOR......................................................................................................................................39
TABLE 3.4: UART CONNECTOR PIN OUT.................................................................................................................................41
TABLE 3.5: UART PATH SELECT CONNECTOR PIN OUT .........................................................................................................41
TABLE 3.6: DC_IN1 CONNECTOR PIN OUT..............................................................................................................................42
TABLE 3.7: DSP JTAG CONNECTOR PIN OUT ........................................................................................................................42
TABLE 3.8: DSP JTAG CONNECTOR PIN OUT ........................................................................................................................43
TABLE 3.9: J4 CONNECTOR PIN OUT .......................................................................................................................................44
TABLE 3.10: J5 CONNECTOR PIN OUT .....................................................................................................................................44
TABLE 3.11: ETHERNET CONNECTOR PIN OUT........................................................................................................................44
TABLE 3.12: PMBUS CONNECTOR PIN OUT..........................................................................................................................45
TABLE 3.13: FPGA JTAG HEADER PIN OUT..........................................................................................................................45
TABLE 3.14: MSP430 SPYBIWIRE CONNECTOR PIN OUT.....................................................................................................45
TABLE 3.15: 80-PIN EXPANSION HEADER PIN OUT.................................................................................................................46
TABLE 3.16: MINI-USB CONNECTOR PIN OUT.........................................................................................................................47
TABLE 3.17: C6657 LITE EVM BOARD SWITCHES.................................................................................................................48
TABLE 3.18: SW3, DSP CONFIGURATION SWITCH ................................................................................................................49
TABLE 3.19: SW4, DSP BOOT MODE SELECTION SWITCH....................................................................................................49
TABLE 3.20: C6657 LITE EVM BOARD TEST POINTS ............................................................................................................51
TABLE 3.21: C6657 LITE EVM BOARD LEDS........................................................................................................................51
TABLE 3.22: TMDXEVM6657LE BOARD ADDITIONAL LEDS................................................................................................53
TABLE 4.1: CURRENT CONSUMPTION ON EACH VOLTAGE RAIL.............................................................................................54
TABLE 4.2: POWER-UP AND DOWN TIMING ON C6657 LITE EVM...........................................................................................59
TABLE 5.1: PIN TYPE NOTATION INTERPRETATION.................................................................................................................64
TABLE 5.2: C6657 LITE EVM FPGA PIN DESCRIPTION.........................................................................................................64
TABLE 5.3: C6657 LITE EVM FPGA PIN DESCRIPTION.........................................................................................................75
TABLE 5.4: FPGA CONFIGURATION REGISTERS SUMMARY...................................................................................................75

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1. Overview
This chapter provides an overview of the C6657 Lite EVM along with the key features and block diagram.
1.1 Key Features
1.2 Functional Overview
1.3 Basic Operation
1.4 Configuration Switch Settings
1.5 Power Supply
1.1Key Features
The C6657 Lite EVM is a high performance, cost-efficient, standalone development platform that enables users
to evaluate and develop applications for the Texas Instruments‟ TMS320C6657 Digital Signal Processor (DSP).
The Evaluation Module (EVM) also serves as a hardware reference design platform for the TMS320C6657 DSP.
The EVM‟s form-factor is equivalent to a single-wide PICMG® AMC.0 R2.0 AdvancedMC module.
TMDSEVM6657LE comes with an integrated, high speed, system trace capable XDS560v2 Mezzanine Emulator
Schematics, code examples and application notes are available, to ease the hardware development process and
to reduce the time to market.
The key features of the C6657 Lite EVM are:
Texas Instruments' fixed point DSP - TMS320C6657
512 Mbytes of DDR3 Memory (up to 1024Mbytes supported)
128 Mbytes of NAND Flash
16 Mbytes of NOR Flash
One Gigabit Ethernet port supporting 10/100/1000 Mbps data rate –switched between RJ-45 connector
and AMC fingers
170 pin B+ style AMC Interface
High performance connector for HyperLink
128 kbytes I2C EEPROM for booting
4 User Indication LEDs, 4 Software Controlled LEDs and 3 User DIP Switches
RS232 Serial interface on 3-Pin header or UART over mini-USB connector
UPP, Timer, SPI, McBSP, UART interfaces on 80-pin expansion header
On-Board XDS100 type Emulation using USB 2.0 interface
TI 60-Pin JTAG header to support External Emulator[1]
High Speed Integrated XDS560v2 Mezzanine Emulator[2]
Module Management Controller (MMC) for Intelligent Platform Management Interface (IPMI)
Powered by DC power-brick adaptor (12V/2.5A) or AMC Carrier back-plane
PICMG® AMC.0 R2.0 single width, full height AdvancedMC module
Note: [1] - Available in TMDXEVM6657L only.
[2] - Available in TMDXEVM6657LE only.

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1.2Functional Overview
The C6657 Lite EVM contains dual TMS320C6657 fixed point Digital Signal Processor. The TMS320C6657
device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word
(VLIW) architecture, developed by Texas Instruments (TI), designed specifically for high density wireline /
wireless media gateway infrastructure. This device is an excellent choice for IP border gateways, video
transcoding and translation, video-server and intelligent voice and video recognition applications. The C66x
devices are backward code-compatible from previous devices that are part of the C6000™ DSP platform.
The functional block diagram of TMDXEVM6657L is shown in below figure:
GAUSS
(TMS320C6657)
FPGA
(XC3S200AN-4FT2.7559G256C)
AMC
(170
pins)
DDR3A
EMAC
EMIF16/ UPP
SRIO X4
PCIe X2
MDIO
IPMB-L(I2C)
MMC_GA[2:0]
ENABLE#
MMC
(MSP430F5435)
VMCM 0,1 X8
JTAG,EMU[1:0]
EMU[17:2]
TEST
HDR
SFM-
150-L2-
S-D-LC Timer[1:0]
UART1
McBSP[1:0] SPI
16
8
SRIO X4
PCIe X2
LVL TXL
(PCA9306)
24
Hyperlink 50Gbps
32
4
NAND Flash
128M X8
(MT29F1G08ABCHC)
32
DDR3-1600
128M X16
(MT41J128M16HA-125)
48
2
Gigbit Eth PHY
88E1112 SGMII
LVL TXL
(PCA9306)
MDIO 3.3V
JACK
(101112FHBMAM
404ZA) MDI
10/100/1000
Mbps
4
EMU[2:17]
4
14
GPIO[15:0] 16
DSP SPI
DSP GPIO
JTAG
Pwr Seq Ctrl
Clk Gen
(CDCE62005)
JTAG
TSW-108-07-S-S
(Boot Config, PCIESSEN,
User Switch)
SYSPG_LED
Debug LED x 4
Clk_SPI
DIP SW x 3
GPIO
McBSP_AMC_EN#
DSP Rst &
Int Ctrl
ON BOARD
Power
Regulators
SpyWire
(640454-4)
On Board
CLOCK
SOURCE
0.75V
1.0V CVDD1
1.5V
1.8V
3.3V
250.0MHz (HyperLink CLKP/N)
250.0MHz (SRIO CLKP/N)
100.0MHz (PCIe CLKP/N)
100.0MHz (Core CLKP/N)
66.67MHz (DDR3 CLKP/N)
48.0MHz (FPGA)
25.0MHz (Ethernet)
12.0MHz (FT2232HL)
32.768kHz (MSP430)
AMC_JTAG
5.0V
HyperLink
CONN
768670011
16MB NOR Flash
(N25Q032A11ESE40F)
Multiplexer
(IDT557-08)
RESET &
INTERRUPT
McBSP CLK/FS
Protection
Ckt
14
48
Mini-USB LVL TXL
(TXS0108)
SWITCH
(TS3L301)
RS-232
(MAX3221)
3 Pin
Header
XDS100- On Board Emulator
TI 60-Pin
Header
(SOLC-115-02-
S-Q-A-K)
SWITCH
(TS3L301) AMC_JTAG
3.3V_JTAG
1.8V
USB_JTAG
USB-JTAG
(FT2232H)
LVL TXL
(SN74AVC4T245)
DSP_UART
DSP_I2C 4
JTAG, EMU[0:1]
UART0
2
DDR3 (ECC)
128M X16
(MT41J128M16HA-125)
S_Px
F_Px
I2C
128KB EEPROM
(AT24C1024B)
2KB EEPROM
(24LC02B-I/ST)
I2C
McBSP_Clk/FS
(from FPGA)
4
2
2
DSP_SPI
GPIO [15:14]
DSP_I2C
DSP_SPI
AMC_McBSP_Data LVL TXL
(SN74AVC4T245) McBSP_Data
4
4
+12V DC (AMC)
14
10
(from AMC)
McBSP_Data
4
MMC_Ctrl
SEL_LOGIC
(from FPGA)
0.9-1.1V CVDD
1.2V
2.5V
8
HyperLink, DDR,
SRIO, Core Clks
PCIE_REF_CLK
(from AMC)
PCIECLK
2
Reset x3
MMC_Ctrl
MMC_SPI
MMC_SPI
Mux_Ctrl
2
PCIe Clk
AMC_TCLK
GPIO 10
4
GPIO
GPIO
GPIO
PGood
GPIO
Clk_Ctrl
+12V DC
(JACK)
+12V DC (AMC)
2
8
5
Smart Reflex
(UCD9222) GPIO
Pwr_Ctrl
4
4
16
DSP_UART
2
2
AMC_SGMII x 1 4
McBSP_AMC_EN#
GPIO
Figure 1.1: Block Diagram of TMDXEVM6657L

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The functional block diagram of TMDXEVM6657LE is shown in below figure:
GAUSS
(TMS320C6657)
FPGA
(XC3S200AN-4FT2.7559G256C)
AMC
(170
pins)
DDR3A
EMAC
EMIF16/ UPP
SRIO X4
PCIe X2
MDIO
IPMB-L(I2C)
MMC_GA[2:0]
ENABLE#
MMC
(MSP430F5435)
VMCM 0,1 X8
JTAG,EMU[1:0]
EMU[17:2]
TEST
HDR
SFM-
150-L2-
S-D-LC Timer[1:0]
UART1
McBSP[1:0] SPI
16
8
SRIO X4
PCIe X2
LVL TXL
(PCA9306)
24
Hyperlink 50Gbps
32
4
NAND Flash
128M X8
(MT29F1G08ABCHC)
32
DDR3-1600
128M X16
(MT41J128M16HA-125)
48
2
Gigbit Eth PHY
88E1112 SGMII
LVL TXL
(PCA9306)
MDIO 3.3V
JACK
(101112FHBMAM
404ZA) MDI
10/100/1000
Mbps
4
EMU[2:17]
4
14
GPIO[15:0] 16
DSP SPI
DSP GPIO
JTAG
Pwr Seq Ctrl
Clk Gen
(CDCE62005)
JTAG
TSW-108-07-S-S
(Boot Config, PCIESSEN,
User Switch)
SYSPG_LED
Debug LED x 4
Clk_SPI
DIP SW x 3
GPIO
McBSP_AMC_EN#
DSP Rst &
Int Ctrl
ON BOARD
Power
Regulators
SpyWire
(640454-4)
On Board
CLOCK
SOURCE
0.75V
1.0V CVDD1
1.5V
1.8V
3.3V
250.0MHz (HyperLink CLKP/N)
250.0MHz (SRIO CLKP/N)
100.0MHz (PCIe CLKP/N)
100.0MHz (Core CLKP/N)
66.67MHz (DDR3 CLKP/N)
48.0MHz (FPGA)
25.0MHz (Ethernet)
12.0MHz (FT2232HL)
32.768kHz (MSP430)
AMC_JTAG
5.0V
HyperLink
CONN
768670011
16MB NOR Flash
(N25Q032A11ESE40F)
Multiplexer
(IDT557-08)
RESET &
INTERRUPT
McBSP CLK/FS
Protection
Ckt
14
48
Mini-USB LVL TXL
(TXS0108)
SWITCH
(TS3L301)
RS-232
(MAX3221)
3 Pin
Header
XDS100- On Board Emulator
TI 60-Pin
Header
(SOLC-115-02-
S-Q-A-K)
SWITCH
(TS3L301) AMC_JTAG
3.3V_JTAG
1.8V
USB_JTAG
USB-JTAG
(FT2232H)
LVL TXL
(SN74AVC4T245)
DSP_UART
DSP_I2C 4
JTAG, EMU[0:1]
UART0
2
DDR3 (ECC)
128M X16
(MT41J128M16HA-125)
S_Px
F_Px
I2C
128KB EEPROM
(AT24C1024B)
2KB EEPROM
(24LC02B-I/ST)
I2C
McBSP_Clk/FS
(from FPGA)
4
2
2
DSP_SPI
GPIO [15:14]
DSP_I2C
DSP_SPI
AMC_McBSP_Data LVL TXL
(SN74AVC4T245) McBSP_Data
4
4
+12V DC (AMC)
14
10
(from AMC)
McBSP_Data
4
MMC_Ctrl
SEL_LOGIC
(from FPGA)
0.9-1.1V CVDD
1.2V
2.5V
8
HyperLink, DDR,
SRIO, Core Clks
PCIE_REF_CLK
(from AMC)
PCIECLK
2
Reset x3
MMC_Ctrl
MMC_SPI
MMC_SPI
Mux_Ctrl
2
PCIe Clk
AMC_TCLK
GPIO 10
4
GPIO
GPIO
GPIO
PGood
GPIO
Clk_Ctrl
+12V DC
(JACK)
+12V DC (AMC)
2
8
5
Smart Reflex
(UCD9222) GPIO
Pwr_Ctrl
4
4
16
DSP_UART
2
2
AMC_SGMII x 1 4
XDS560v2
Mezzanine Card
USB
Mini AB
TI_60
For XDS560v2
Emulation
McBSP_AMC_EN#
GPIO
Figure 1.2: Block Diagram of TMDXEVM6657LE

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1.3Basic Operation
The C6657 Lite EVM platform is designed to work with TI‟s Code Composer Studio (CCS) development
environment and ships with a version specifically tailored for this board. CCS can interfaces with the board via
on-board emulation circuitry using the USB cable supplied along with this EVM or through external emulator.
The EVM comes with the Texas Instruments Multicore Software Development Kit (MCSDK) for SYS/BIOS OS.
The BIOS MCSDK provides the core foundational building blocks that facilitate application software development
on TI's high performance and multicore DSPs. It also includes an out-of-box demonstration. Follow the instruction
in BIOS MCSDK Getting Started Guide to install all the necessary development tools, drivers and
documentation.
To start operating the board, follow instructions in the Quick Start Guide. This guide provides instruction for
proper connections and configuration for running the POST and OOB Demos. After completing the POST and
OOB Demos, proceed with installing CCS and the EVM support files by following the instructions on the DVD.
This process will install all the necessary development tools, drivers and documentation.
After the installation is completed, follow below steps to run Code Composer Studio.
1. Power ON the board using power brick adaptor (12V/2.5A) supplied along with this EVM or Insert this
EVM board into MicroTCA chassis or AMC carrier back-plane.
2. Connect USB cable from host PC to EVM board.
3. Launch Code Composer Studio from host PC by double clicking on its icon at PC desktop.
Detailed information about the EVM including examples and reference material is available in the DVD available
with this EVM kit.
Figure 1.3: TMDXEVM6657L

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Figure 1.4: TMDXEVM6657LE
1.4Boot Mode and Boot Configuration Switch Setting
The C6657 Lite EVM has 18 sliding DIP switches (Board Ref. SW3, SW5 and SW9) to determine boot mode,
boot configuration, device number, Endian mode, CorePac PLL clock and PCIe mode selection. Mode selection
options latch at every reset of the DSP.

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1.5Power Supply
C6657 Lite EVM can be powered from a single +12V / 2.5A DC (30W) external power supply connected to the
DC power jack (DC_IN1)). Internally, +12V input is converted into required voltage levels using local DC-DC
converters.
CVDD (+0.90V~+1.05V) used for the DSP Core logic
+1.0V is used for DSP internal memory and HyperLink/SRIO/SGMII/PCIe SERDES termination of DSP
+1.5V is used for DDR3 buffers of DSP, HyperLink/SRIO/SGMII/PCIe SERDES regulators in DSP and
DDR3 DRAM chips
+1.8V is used for DSP PLLs, DSP LVCMOS I/Os and FPGA I/Os driving the DSP
+2.5V is used for Gigabit Ethernet PHY core
+1.2V is used for FPGA core and Gigabit Ethernet PHY core
+3.3V is used for FPGA I/Os
+5V and +3.3V is used to power optional XDS560v2 Mezzanine card
The DC power jack connector is a 2.5mm barrel-type plug with center-tip as positive polarity
The C6657 Lite EVM can also draw power from the AMC edge connector (AMC1). If the board is inserted into a
PICMG® MicroTCA.0 R1.0 compliant system chassis or AMC Carrier back-plane, an external +12V supply from
DC jack (DC_IN1) is not required.

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2. Introduction to the C6657 Lite EVM board
This chapter provides an introduction and details of interfaces for the C6657 Lite EVM board. It contains:
2.1 Memory Map
2.2 EVM Boot mode and Boot configuration switch settings
2.3 Board Revision ID
2.4 JTAG - Emulation Overview
2.5 Clock Domains
2.6 I2C boot EEPROM / SPI NOR Flash
2.7 FPGA
2.8 Gigabit Ethernet PHY
2.9 Serial RapidIO(SRIO) Interface
2.10 DDR3 External Memory Interface
2.11 16-bit Asynchronous External Memory Interface or UPP
2.12 HyperLink Interface
2.13 PCIe Interface
2.14 UART Interface
2.15 Module Management Controller for IPMI
2.16 Additional Headers
2.1Memory Map
The memory map of the TMS320C6657 device is as shown in Table 2.1. The external memory configuration
register address ranges in the C6657 device begin at the hex address location 0x7000 0000 for EMIFA and hex
address location 0x7800 0000 for DDR3 Memory Controller.

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Table 2.1: TMS320C6657 Memory Map

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